JP2001144591A - Variable delay circuit and timing control circuit using the same - Google Patents

Abstract

(57) Abstract: A variable delay circuit capable of miniaturizing a minimum unit of a variable delay time to less than a delay time of a gate circuit and capable of adjusting a delay time with high accuracy without increasing power consumption. A variable delay circuit includes a multi-input logic gate circuit having three or more input terminals.
Is provided. A delay based on a time constant determined by a diffusion layer capacitance and an output resistance of a single MOS transistor connected to each input terminal, which is a MOS transistor constituting a multi-input logic gate circuit, is used as a minimum unit of the variable delay time. The delay time difference of the signal passing through the multi-input logic gate circuit changes in the minimum unit delay step according to the difference in the input terminals used by the multi-input logic gate circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a variable delay circuit for changing a delay of a signal in an electronic circuit, and a timing control circuit for controlling timing using the variable delay circuit.

[0002]

2. Description of the Related Art In recent years, it has become necessary to increase the speed of an interface with various other electronic circuits as the speed of a CPU clock in a computer system increases.

Conventionally, a clock access time in a synchronous LSI, that is, a time required for the LSI to output a data signal after receiving a clock signal, is mainly a delay of a clock signal in an input clock buffer and a long route. The speed is controlled by the delay of the clock signal in the wiring and the delay of the data signal in the output data buffer. In addition, process variations, power supply voltage,
Due to the temperature fluctuation, the delay time in the input clock buffer and the output data buffer varies, and the data output timing in the synchronous LSI varies. If the clock used becomes faster and the cycle time becomes shorter, the time range in which data can be received on the data receiving side becomes narrower, which is a factor that makes system design difficult.

FIG. 7A is a block diagram for explaining a conventional clock signal path from an external clock terminal to an output data buffer. FIG. 7B is a timing chart for explaining the delay of the clock signal in the above path. The delay of a clock signal from a conventional external clock terminal to an output data buffer will be described with reference to these drawings.

In FIG. 7A, an external clock terminal 70
1 enters the output data buffer 706 via the input clock buffer 702, the long wiring 703, and the data register 705, and outputs the output data terminal 707.
Output the output data signal DATAOUT. The external clock terminal 701 is a terminal for receiving a clock signal CLK received by the LSI. FIG. 7B shows an external clock terminal 701.
Clock signal CLK at the input clock buffer 70
2, the clock signal CIBCLK entering the long wiring 703, the clock signal REGCLK propagating from the long wiring 703 to the data register 705, and the data terminal 70 of the output buffer 706.
7 is a timing chart of the output signal DATAOUT in FIG.

As shown in FIG. 7B, in the path of the clock signal entering the conventional output data buffer 706,
The delay time td1 and the long wiring 703 generated in the input clock buffer 702 until the clock signal CLK reaches the output data buffer 706 from the external clock terminal 701
, The delay time td1 + td2 of the delay time td2 is generated. In addition, delay time td1, which occurs in the input clock buffer due to process variations, power supply voltage, and temperature fluctuations,
The delay time td2 generated by the long wiring and the delay time td3 generated by the data register and the output buffer have variations, and the sum of the delay times td = td1 + td2 + td3.
Had large variations.

In order to solve the above problem, it is known to use a timing control circuit (for example, there are literatures 1 and 2 described later). This is L
In order to eliminate a delay time generated between the clock signal received by the SI and the clock signal received by the output data buffer, the phase of the clock signal propagating through the LSI is changed using a timing control circuit, and the clock signal received by the output data buffer is changed. Is synchronized with the clock signal received by the LSI.

FIG. 8A is a block diagram for explaining a path of a clock signal from an external clock terminal to an output data buffer when a timing control circuit is used. FIG. 8B is a timing chart showing the delay of the clock signal in the above path. With reference to these drawings, a method for synchronizing a clock signal received by an output data buffer with a clock signal received by an LSI when a timing control circuit is used will be described.

As shown in FIG. 8A, a timing control circuit 801 is inserted between an input clock buffer 702 and a long wiring 703 in this path. The clock signal CIBCLK generated by the input clock buffer is applied to the clock signal CL at the external clock terminal 701 as shown in FIG.
K is delayed by td1. Next, the timing control circuit 801 causes a delay of tck- (td1 + td2). This allows the clock signal DL generated by the timing control circuit to be generated.
LCLK is a clock signal at the external clock terminal 701
CLK is delayed by tck-td2. Here, tck is a clock cycle time.

As a result, the clock signal BUFCLK propagating to the output data buffer 708 (corresponding to the combination of the data register 705 and the output buffer 706 in FIG. 7) has a time tck with respect to the clock signal CLK at the external clock terminal 701. That is, it is delayed by one clock cycle. However, this is equivalent to being synchronized with the clock signal CLK at the external clock terminal 701.

In this manner, the timing control circuit 801
Is used to receive the clock signal BUFCLK propagating to the output data buffer 708
Can be synchronized to CLK.

Further, there are fluctuations in the process, the power supply voltage, and the temperature, and the delay time t generated in the input clock buffer 702 varies.
Even if d1, the delay time td2 generated by the long wiring 703, and the delay time td3 generated by the output data buffer (data register and output buffer) 708 fluctuate, the timing control circuit 801 produces a delay of tck− (td1 + td2 + td3) with a certain accuracy. , Data output timing with clock signal
Since it is synchronized with CLK, data output timing variations can be reduced within the above accuracy.

As a timing control circuit, a phase-locked loop (PLL) is generally used.
Circuit, delay locked loop (DLL: Delay-Lock
ed Loop) circuits are known. References cited as examples of PLL circuits include the IEEE Journal of Solid-State Circuits, Vo.
l.27, No.11, pp.1599-1607, Ian A. Young et al., `` AP
LL Clock Generator with 5 to 110MHz of Lock Range
for Microprocessors "(hereinafter referred to as Document 1).

References cited as examples of DLL circuits include an English journal published by the Institute of Electronics, Information and Communication Engineers, June 1996, VOL. E79-C, No. 6, pp. 798-807, Yoshinori.
Okajima et al., `` Digital Delay Locked Loop and Desi
gn Technique for High-Speed Synchronous Interfac
e "(hereinafter referred to as Document 2).

The DLL circuit is mainly composed of a variable delay circuit, a phase comparison circuit, and a delay control circuit. Particularly, in the circuit disclosed in Reference 2, the variable delay circuit includes a two-input NAND circuit and an inverter. It has a multi-stage configuration of a digital circuit having one circuit, and changes the phase of the signal by controlling the number of circuit stages through which the signal passes. In other words, there is an advantage that power consumption is small because the digital circuit is used.

Hereinafter, the variable delay circuit introduced in the above reference 2 will be described with reference to FIG. FIG. 2 is a configuration example of a variable delay circuit having four delay steps.
This circuit includes an input terminal 217, an output terminal 218, delay control terminals S1, S2, S3, and S4, an inverter circuit 220, and four unit delay circuits 221, 222, 223, and 22.
4. Further, one unit delay circuit (for example, 221) includes the first NAND circuit 205 and the second NA
The ND circuit 209 and the inverter circuit 213 are configured, and the other unit delay circuits 222 to 224 have the same configuration. The terminal 219 is supplied with a “high (H)” level signal.

In this variable delay circuit, the input terminal 21
7, the signal CLKIN is output as the output signal CLKOUT from the output terminal 218 through the inverter circuit 220 and one of four stages of the unit delay circuit, and as the number of delay stages through which the signal passes increases, Delay time increases. The number of unit delay circuits through which signals pass is determined by delay control terminals S1 and S1.
2, S3 and S4 can be changed by selectively providing one "H" level signal and the remaining "low (L)" level.

Here, for example, "H" is applied to the delay control terminal S1.
When the level is given and selected, the signal CLKIN input to the input terminal 217 is supplied to the inverter circuit 220 and the first NAND circuit 205 and the second NAN of one unit delay circuit 221.
After passing through the D circuit 209 and the inverter circuit 213,
A delay time corresponding to two NAND circuits and two inverter circuits is realized.

Similarly, if the delay control terminal S2 is selected,
The signal CLKIN input to the input terminal 217 is output from the inverter circuit 2
20 and two unit delay circuits 222 and 221 to realize delay times for three NAND circuits and three inverter circuits. If the delay control terminal S3 is selected, the signal CLKIN input to the input terminal 217 is output from the inverter circuit 220 and the three unit delay circuits 223, 222, 2
21 and a delay time corresponding to four NAND circuits and four inverter circuits. Further, the delay control terminal S
4, the signal input to the input terminal 217 is output to the inverter circuit 220 and the four unit delay circuits 224 and 22.
3, 222, and 221 to realize a delay time for five NAND circuits and five inverter circuits.

As described above, in the conventional variable delay circuit, the minimum unit of the delay time is the delay time of one NAND circuit and one inverter circuit.

[0021]

In the conventional variable delay circuit of the DLL circuit according to the above-mentioned reference 2, the delay is quantized, and the minimum unit of the timing control of the clock signal is the delay time by the two-input NAND circuit and the inverter circuit. . For this reason, the precision of the timing control of the clock signal is as low as two delay steps.

In view of the above-mentioned problems of the conventional timing control circuit, an object of the present invention is to provide a multi-input logic gate capable of miniaturizing the minimum unit of the variable delay time to less than the delay time of the gate circuit. To provide a variable delay circuit.

It is also an object of the present invention to provide a timing control circuit which uses this variable delay circuit to increase the precision of clock signal timing control without increasing power consumption.

Further, the present invention also provides a method for controlling a variable delay circuit constituted by the multi-input logic gate.

[0025]

In order to achieve the above object, a variable delay circuit according to the present invention has a multi-input logic gate circuit having at least three input terminals, and the multi-input logic circuit for inputting a signal. The delay time difference between signals passing through the multi-input logic gate due to the difference in the input terminals of the gate circuit is configured as the minimum unit of the variable delay time.

Further, the variable delay circuit according to the present invention comprises a multi-layer structure comprising at least three parallel-connected first conductivity type MOS transistors and at least three series-connected second conductivity type MOS transistors. An input NAND circuit having a gate connected to each input terminal of the multi-input NAND circuit, and a variable delay time having a time constant determined by an output resistance and a diffusion layer capacitance of the MOS transistor of the second conductivity type. It is preferable that the minimum unit of time is set, and the delay of the input signal is varied in the minimum unit delay time step in accordance with the difference of the input terminal to be input.

In this case, on the output current path of the serially connected second conductivity type MOS transistor of the multi-input NAND circuit, a second conductivity type MOS transistor whose gate is connected to a constant voltage source is further connected in series. May be inserted. Thus, the delay time can be adjusted.

In addition, the timing control circuit according to the present invention includes the input clock buffer and the output clock for synchronizing the clock signal from the input clock buffer with the clock signal reaching the output data buffer via the wiring. In a timing control circuit having a variable delay circuit provided between a data buffer and a data buffer, a variable delay circuit having any one of the above-described configurations is used as the variable delay circuit.

The control method of the variable delay circuit according to the present invention is as follows.
A method for controlling a variable delay circuit comprising a multi-input logic gate circuit having at least three input terminals, wherein the variable delay circuit passes through the multi-input logic gate circuit caused by a difference between input terminals for inputting signals of the multi-input logic gate circuit. The delay time is controlled using the signal delay time difference as a minimum unit of the variable delay time.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the variable delay circuit according to the present invention has a multi-input logic gate circuit having at least three input terminals, and inputs the signal to the multi-input logic gate circuit. The delay time difference due to the terminal difference is configured as the minimum unit of the variable delay time.

An embodiment of the timing control circuit according to the present invention is a control circuit provided between an input control signal buffer (that is, an input clock buffer) and an output data buffer. In order to synchronize a control signal, that is, a clock signal with a clock signal received by an input clock buffer, the phase of the clock signal is controlled using the variable delay circuit including a multi-input logic gate circuit having at least three input terminals. Is a DLL circuit configured as described above.

In general, the signal delay time in a normal logic gate circuit is the sum of the transition time of the MOS transistor in the logic gate circuit and the delay time of the time constant formed by the output resistance of the logic gate circuit and the gate input capacitance of the next stage. is there.

On the other hand, in a multi-input logic gate, the number of MOS transistors through which a signal passes differs depending on the terminal to which the signal is input. When a signal passes through the MOS transistor, a delay time of a time constant generated by the output resistance and the diffusion layer capacitance of the MOS transistor alone occurs, so that the signal delay time differs when the number of MOS transistors through which the signal passes differs.

According to the above-described embodiment of the variable delay circuit according to the present invention, the delay time can be varied with a minimum delay unit being a signal delay time difference passing through the multi-input logic gate circuit due to the difference of the input terminal. it can. That is, the minimum delay time unit of the variable delay circuit of the present invention is a time constant delay time formed from the output resistance of the MOS transistor and the diffusion layer capacitance. This delay time is smaller than the signal delay time in the normal logic gate circuit. Therefore, by configuring a variable delay circuit with a multi-input logic gate,
A plurality of delay steps can be generated by one logic gate, and the delay step can be set to the minimum delay time, so that the delay time can be controlled with high accuracy.

When the variable delay circuit of the present invention and the conventional variable delay circuit comprising a two-input NAND circuit and an inverter circuit are each configured in multiple stages, the number of gate stages required to generate the same delay time is as follows. Since they are equal, the power consumption does not change.

Accordingly, D using the variable delay circuit of the present invention
The timing control circuit having the LL circuit configuration can make the minimum delay time unit finer than before, without increasing the power consumption as compared with the conventional technology, and can perform low-power and high-accuracy timing control.

[0037]

Next, specific embodiments of the variable delay circuit and the timing control circuit according to the present invention will be described in detail with reference to the accompanying drawings.

First, an example of the configuration of a timing control circuit for a synchronous memory will be described with reference to FIGS. FIG.
FIG. 3 is a block diagram for describing a configuration example of a timing control circuit. Here, the input signal of the timing control circuit in FIG. 8 is described as EXTCLK, and the output signal is described as INTCLK. Note that this configuration example is similar to the DLL described in the above reference 2. This DLL includes a first variable delay circuit 301, a second variable delay circuit 302, a phase comparison circuit 30
3, a delay control circuit 304, a divide-by-8 circuit 305, a dummy delay circuit 307, an input clock terminal 308, and an output clock terminal 309.

First, the clock signal EXTCLK is supplied from the input clock buffer 702 in FIG.
08 is input. This clock signal EXTCLK is divided into two paths, one into the divide-by-8 circuit 305 and the other into the first variable delay circuit 301, and after a predetermined delay time, as an output clock signal INTCLK, Terminal 30
9 is output.

The divide-by-8 circuit 305 receives the input clock signal EX.
TCLK is divided by 8 (cycle is multiplied by 8). There are two divide-by-8 input clock signals, and the first divide-by-8 clock 310 is supplied to the second variable delay circuit 302 by the second divide-by-8 clock 3.
11 enters the first input terminal a of the phase comparison circuit 303.
The second divided-by-8 clock 311 is the first divided-by-8 clock 3
One cycle is delayed from 10. The configuration of the second variable delay circuit 302 is the same as the configuration of the first variable delay circuit, and each variable delay circuit is controlled by the delay control circuit 304 so as to have the same delay time.

The clock signal divided by 8 that has passed through the second variable delay circuit 302 enters the second input terminal b of the phase comparison circuit 303 via the dummy delay circuit 307. The dummy delay circuit 307 is a delay circuit designed to have a delay time substantially equal to the delay time td1 + td2 in the input clock buffer 702 and the long wiring 703. Here, assuming that the delay time of the variable delay circuits 301 and 302 is tdx, the signal 312 input to the second input terminal b of the phase comparison circuit 303 is different from the signal 311 input to the first input terminal a.
It is delayed by the time of tdx + td1 + td2.

The phase comparison circuit 303 has a second input terminal b
If the phase of the signal 312 entering the first input terminal a is ahead of the phase of the signal 311 entering the first input terminal a, an "H" level signal is output. The output signal of the phase comparison circuit enters the delay control circuit 304.

The delay control circuit 304 includes the variable delay circuit 30
The delay time of 1,302 is controlled. If the signal from the phase comparison circuit is at "H" level, the delay is increased by one step, and if the signal is at "L" level, the delay is reduced by one step.
The delay control circuit 304 is constituted by a bidirectional shift register. When the number of delay steps of the variable delay circuits 301 and 302 is N, the delay control circuit 304
There are N signals to be output to 1,302. The delay control circuit 304 determines that only one of the N output signals is “H”.
The bit pattern is bidirectionally shifted with respect to the signal from the phase comparison circuit 303.

Each of the variable delay circuits 301 and 302 generates a delay time having a delay step corresponding to one output signal line at "H" level among the N output signal lines of the delay control circuit.

With the above circuit configuration, the phase comparison circuit 30
3, the delay tdx + td1 + t of the signal input to the second input terminal b
If d2 is ahead of the input clock signal EXTCLK, the delay times of the variable delay circuits 301 and 302 increase, and if d2 is late, the delay times of the variable delay circuits 301 and 302 decrease.

By this feedback control, the delay control circuit 304 sets the cycle time tck to tck = tdx + td1 +
An operation of controlling the delay step is performed so as to satisfy td2, and the delay time tdx of the first and second variable delay circuits 301 and 302 is close to tck- (td1 + td2).

FIG. 10 shows an example of the configuration of the divide-by-8 circuit 305. FIG. 10A is a block diagram of a divide-by-8 circuit, and FIG. 10B is a circuit configuration diagram of a divide-by-2 circuit used in the divide-by-8 circuit. As shown in FIG. 10A, the divide-by-8 circuit 305 includes a clock signal input terminal 1001, a reset signal input terminal 1003, a first divide-by-8 clock signal output terminal 1002, and a second divide-by-8 clock signal output terminal 100.
4, three divide-by-2 circuits 1005 and flip-flop 1
007. This divide-by-2 circuit 1005
Is composed of a flip-flop and an inverter, as shown in FIG.
A terminal for applying a reset signal RESET for initializing to a level, an input terminal for applying a clock signal CLKIN, and an output signal CLK2OUT obtained by dividing the input signal by 2 (doubling the cycle).
Output terminal.

Prior to operation, the divide-by-8 circuit 305 receives a reset signal RESET having a positive pulse waveform at a reset signal input terminal 1003, and outputs the outputs of the divide-by-2 circuit 1005 and the flip-flop 1007 in the circuit. Initialize to “L” level.

Next, when the clock signal CLKIN is input to the clock signal input terminal 1001, the clock signal CLKIN
Passes through three divide-by-2 circuits 1005 to become a divide-by-8 clock signal CLK8OUT, which is output from a first divide-by-8 clock signal output terminal 1002 as a first divide-by-8 clock signal CLK8OUT1.

The eight-frequency-divided clock signal CLK8OUT
Passes through the flip-flop 1007 and is delayed by one clock cycle from the first divide-by-8 clock signal CLK8OUT1,
A second 分 frequency-divided clock signal output terminal 1004 outputs the second と し て frequency-divided clock signal CLK8OUT2.

Next, the variable delay circuit according to the present embodiment will be described with reference to FIGS. 1, 4, 5, 6, and 9. FIG. FIG. 1 is a circuit diagram showing an embodiment of a variable delay circuit according to the present invention, which is a variable delay circuit having eight delay steps.

This variable delay circuit comprises an input terminal 123, an output terminal 124, delay control terminals S1 to S8, an inverter circuit 126 and two unit delay circuits 109 and 110, and one unit delay circuit (for example, 109). Is 4
It is composed of NAND circuits 111 to 114, a 5-input NAND circuit 119, and an inverter circuit 120. Note that an “H” level signal is supplied to the terminal 125.

FIG. 4 shows the variable delay circuit 10 shown in FIG.
FIG. 9 is a circuit diagram of a 5-input NAND used in 9, 110. This circuit includes five input terminals IN0 to IN4,
An output terminal OUT, six n-channel MOS transistors MN0 to MN4, MN4C, and five p-channel MOs
It is composed of S transistors MP0 to MP4. Although the MOS transistor MN4c whose gate is connected to the high-potential-side power supply is not always necessary, the MOS transistor MN4c is inserted on the output current path for adjusting the delay increment in the unit delay circuit. Transistor. In this case, it is provided for adjusting the delay increment between the input terminals IN3 and IN4.

In the case of the five-input NAND circuit 119 in the variable delay circuit 109 shown in FIG. 1, the input terminal IN0 is the output of the inverter circuit 122, and the input terminal IN1 is the NAND circuit 111.
, IN2 is the output of the NAND circuit 112, IN2
3 is connected to the output of the NAND circuit 113, and IN4 is connected to the output of the NAND circuit 114. In the case of the 5-input NAND circuit 121 in the variable delay circuit 110 shown in FIG. 1, the input terminal IN0 is the output of the terminal 125, and the input terminal IN1 is N
IN2 of the output of the AND circuit 115 is the NAND circuit 11
6, IN3 is the output of NAND circuit 117,
N4 is connected to the output of the NAND circuit 118.

FIGS. 5 and 6 are equivalent circuit models of a five-input NAND used in the variable delay circuit of this embodiment. FIG. 5A shows a case where a rising clock signal enters the input terminal IN2, FIG. 5B shows a case where a falling clock signal enters the input terminal IN2, and FIG. FIG. 6B shows a case where the falling clock signal enters the input terminal IN3 when the signal enters the input terminal IN3.

The equivalent circuit includes the output resistance RN0 and diffusion layer capacitance CN0 of the MOS transistor MN0, the output resistance RN1 and diffusion layer capacitance CN of the MOS transistor MN1.
1, output resistance RN2 and diffusion layer capacitance CN2 of MOS transistor MN2, output resistance RN3 and diffusion layer capacitance CN3 of MOS transistor MN3, output resistance RN4 of MOS transistor MN4, output resistance RP2 of MOS transistor MP2, output resistance of MOS transistor MP3 RP3, output resistance RN4 of MOS transistor MN4c
c.

Here, MO is set so that RP3> RP2.
The circuit constants of the S transistors MP2 and MP3 are designed. The rising clock signal is input terminal IN2
5A, the load formed on the path of the flowing current is the output resistance RN of the MOS transistor as shown in FIG.
0, RN1, RN2, RN3, RN4c, RN4 and diffusion layer capacitors CN0, CN1, CN2. When a rising clock signal enters the input terminal IN3, as shown in FIG. The load that can be made in the path is the output resistance RN0, RN1, RN of the MOS transistor.
2, RN3, RN4c, RN4 and diffusion layer capacitance CN
0, CN1, CN2, CN3, and the diffusion layer capacitance CN3
Only increase by.

When the falling clock signal enters the input terminal IN2, as shown in FIG. 5 (b), the load that can be made in the path of the flowing current is the output resistances RP2, RN0, RN1 of the MOS transistor and the diffusion layer. Capacity CN0,
When the rising clock signal is input to the input terminal IN3, the load that can flow in the flowing current is the output resistance RP3, RN0, RN1, of the MOS transistor as shown in FIG. 6B. RN2 and diffusion layer capacitances CN0, CN1, CN2, and CN3, and the difference between the output resistances RP3 and RP2 (RP3-RP2), the output resistance RN2, and the diffusion layer capacitance CN3 increase. Here, when transistors of the same size are used as the MOS transistors MP0 to MP4, the difference between the output resistances (RP3 to RP2) is substantially 0, and the output resistances RN2 and the diffusion layer capacitance CN3 increase. It's only for minutes.

As described above, in the variable delay circuit of this embodiment, the input terminal of the 5-input NAND circuit to which the input signal is input is 1
As a result, the load on the path through which the signal flows increases by the amount of the increase in the diffusion layer capacitance and output resistance of one MOS transistor, and the delay time differs. This occurs not only when the input terminal for receiving the clock signal changes from IN2 to IN3, but also from IN1 to IN2 or IN2.
The same applies to the case of changing from 3 to IN4.

This difference in delay time is the minimum unit of the delay time in the variable delay circuit of this embodiment, and is about 30 to 60 picoseconds. This is smaller than the delay time of one NAND circuit and one inverter circuit, which is the minimum unit of the delay time in the conventional variable delay circuit, which is about 100 to 200 picoseconds.

FIG. 9 is a diagram for explaining how the waveform of the input signal is delayed in the variable delay circuit of this embodiment shown in FIG. As shown in the drawing, the delay control signal terminals S1, S2,
The waveforms of the signal CLKOUT at the output terminal 124 when S3, S4, and S5 are selected are CLKOUT (S1) and CLKOUT, respectively.
(S2), CLKOUT (S3), CLKOUT (S4), CLKOUT (S5).

Here, the output signals CLKOUT (S1), CLKOUT (S
2), CLKOUT (S3) and CLKOUT (S4) are made up of only two stages of the inverter circuit 126 and the unit delay circuit 109, while the output signal CLKOUT (S5) is generated by the inverter circuit 126 and the unit delay circuit 1
Made by three stages 09 and 110. That is, the delay of the output signal CLKOUT (S5) is
Unlike the delay of UT (S4), the delay by the 5-input NAND circuit 119 when a signal is input from the input terminal IN0 of the inverter circuit 126 and the unit delay circuit 109, and the input terminals of the inverter circuit 120 and the unit delay circuit 110 This is the sum of the delay caused by the 5-input NAND circuit 121 when a signal is input from IN1.

Therefore, in order to monotonically increase the delay time of the variable delay circuit composed of the unit delay circuits 109 and 110 in the order of the delay control signal terminals S1 to S8, the output signals CLKOUT (S4) and CLKOUT ( It is necessary to ensure that the magnitude of the delay time does not reverse during S5). That is, as shown in FIG. 9, the input terminal 123 of the output signal CLKOUT (S4)
And the five-input NAND circuit 11 when a signal is input from the input terminal IN0.
9 and the delay time td0 due to the inverter circuit 120 and the delay time td1 of the output signal CLKOUT (S1) with respect to the input signal CLKIN need to satisfy td4 <td0 + td1.

It is also important to make the delay increment closer to a constant value to increase the linearity of the delay time with respect to the delay control signal. These adjust the output resistance and diffusion layer resistance of the MOS transistor in the five-input NAND circuit, and as described above, load correction MOS transistor MN4c.
In the output current path of the five-input NAND circuit. The output resistance and the diffusion layer resistance of the MOS transistor can be adjusted by adjusting the gate width and the gate length of the MOS transistor.

Compared with the conventional variable delay circuit, when the same delay time is generated, the number of stages of the unit delay circuit is almost the same, and the number of gates does not change much, so that the power consumption is the same as in the conventional example. However, the delay time can be adjusted with high accuracy. Therefore, by using the variable delay circuit of the present embodiment for the first and second variable delay circuits of the timing control circuit shown in FIG. The phase of the clock signal according to the cycle of the
A timing control circuit capable of appropriately controlling with high accuracy without increasing power consumption can be obtained.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. It is. For example, in the embodiment, the case where the variable delay circuit of the present invention has two stages of unit delay circuits using a five-input NAND circuit has been described, but the configuration of the variable delay circuit is not limited to this, and the number of input terminals of the NAND circuit is Needless to say, the number of stages of the unit delay circuit can be freely selected.

[0067]

As is apparent from the above-described embodiment, according to the variable delay circuit of the present invention, in addition to the delay caused by the gate circuit in the conventional variable delay circuit, the MOS transistor alone has a diffusion layer capacitance and output resistance. Since a minute delay using a load is used, the minimum unit of the delay time can be reduced without increasing power consumption as compared with the conventional variable delay circuit.

Further, the timing control circuit using the variable delay circuit of the present invention can perform low power and highly accurate timing control.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a variable delay circuit according to the present invention.

FIG. 2 is a circuit diagram showing a conventional example of a variable delay circuit.

FIG. 3 is a block diagram showing a configuration example of a timing control circuit to which the variable delay circuit of the present invention is applied.

FIG. 4 is a 5-input NA used in the variable delay circuit shown in FIG.
FIG. 3 is a configuration diagram of an ND circuit.

5 is an input terminal I of the 5-input NAND circuit shown in FIG.
FIG. 9 is an equivalent circuit model diagram when a clock signal is input to N2.

FIG. 6 shows an input terminal I of the five-input NAND circuit shown in FIG.
FIG. 9 is an equivalent circuit model diagram when a clock signal is input to N3.

FIG. 7 is a diagram showing a conventional example of a clock access path, where (a) is a block diagram showing a clock access path;
(B) is the timing chart.

8A and 8B are diagrams showing a clock access path when a timing control circuit to which the variable delay circuit of the present invention is applied is used, FIG. 8A is a block diagram of the clock access path, and FIG. 8B is a timing chart thereof. .

FIG. 9 is an explanatory diagram showing a state of signal delay by the variable delay circuit according to the present invention.

FIG. 10 is a diagram illustrating a configuration example of a divide-by-8 circuit illustrated in FIG. 3;

[Explanation of symbols]

109, 110... Unit delay circuits, 111 to 118.
ND circuit, 119, 121... 5-input NAND circuit, 12
0, 122, 126: inverter circuit, 123: input terminal, 124: output terminal, 125: terminal, 301, 302
... variable delay circuit, 303 ... phase comparison circuit, 304 ... delay control circuit, 305 ... 8 frequency divider circuit, 307 ... dummy delay circuit, 308 ... input clock terminal, 309 ... output clock terminal, 701 ... external clock terminal, 702 ... Input clock buffer, 703: long wiring, 707: data terminal, 7
08: output data buffer, 801: timing control circuit, CLKIN: input signal, CLKOUT, CLKOUT (S1) to CLKOUT (S
5) ... output signal, CN0 to CN3 ... diffusion layer capacity, IN0
IN4... Input terminals of a five-input NAND circuit, MN0 to MN
4, MN4c... N-channel MOS transistor, MP0
~ MP4 ... p-channel MOS transistor, RN0-R
N4, RN4c: output resistance of n-channel MOS transistor, RP2, RP3: output resistance of p-channel MOS transistor, S1 to S8: delay control terminal, tck: cycle time, td0 to td4: delay time.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yoshinobu Nakagome 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5J001 AA04 BB05 BB10 BB12 BB14 BB24 CC00 DD02 DD03 DD05 5J042 AA10 BA00 CA00 CA09 CA12 CA15 CA18 CA24 CA27 CA28 DA00 DA02 DA03

Claims (5)

[Claims] 1. A multi-input logic gate circuit having at least three input terminals, wherein a delay time difference of a signal passing through a multi-input logic gate due to a difference between input terminals of the multi-input logic gate circuit for inputting a signal is determined. A variable delay circuit configured as a minimum unit of a variable delay time. 2. A multi-input NAND circuit comprising at least three MOS transistors of the first conductivity type connected in parallel and at least three MOS transistors of the second conductivity type connected in series. A delay time of a time constant determined by the output resistance and the diffusion layer capacitance of the MOS transistor of the second conductivity type, the gate of which is connected to each input terminal of the input NAND circuit, is input as the minimum unit of the variable delay time. A variable delay circuit, wherein a delay of a signal is varied in the minimum unit delay time step in accordance with a difference between the input terminals to which the signal is input. 3. A second conductivity type MOS transistor having a gate connected to a constant voltage source on an output current path of a serially connected second conductivity type MOS transistor constituting the multi-input NAND circuit.
An OS transistor is further inserted in series.
A variable delay circuit as described. 4. A variable circuit provided between the input clock buffer and the output data buffer for synchronizing a clock signal from the input clock buffer with the clock signal reaching the output data buffer via a wiring. A timing control circuit having a delay circuit, wherein the variable delay circuit according to claim 1 is used as the variable delay circuit. 5. A method for controlling a variable delay circuit comprising a multi-input logic gate circuit having at least three input terminals, wherein the multi-input logic circuit is caused by a difference between input terminals for inputting signals of the multi-input logic gate circuit. A method of controlling a variable delay circuit, wherein a delay time is controlled using a signal delay time difference passing through a gate circuit as a minimum unit of the variable delay time.