JP2001143488A - Semiconductor storage device, data reading method thereof, and semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: A semiconductor memory device and a semiconductor integrated circuit device capable of reducing power consumption during data reading. The present invention relates to a memory cell array having a plurality of memory cells, a row address decoder for controlling a word line voltage, a column decoder for controlling a column line voltage, and a specific memory cell. A sense amplifier 5 for amplifying data read from the latch 1, a latch circuit 6 for latching the output of the sense amplifier 5, and an output buffer 7 for buffering the output of the latch circuit 6 and supplying the output to a data output terminal. Sense amplifier 5 and output buffer 7
After latching the output of the sense amplifier 5 by the latch circuit 6 and transmitting the latch output of the latch circuit 6 to the output buffer 7, the latch circuit 6 Even if the sensing operation of No. 5 is stopped, the data read from the memory can be output normally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as an SRAM or a flash memory, and more particularly to a technique for reducing power consumption.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing the configuration of external pins of a general read-only memory. In the figure, VDD and VSS are power supply pins, A0 to A7 are address input pins, D0 to D7 are 8-bit data output pins for outputting data corresponding to each address, CE is a chip enable terminal for selecting a chip, OE is an output enable terminal for switching whether to enable data output of D0 to D7.

FIG. 5 is a block diagram showing the internal configuration of a conventional memory, and FIG. 6 is a timing chart of each input / output terminal of the memory of FIG. 5, a memory cell array 2 including a plurality of memory cells, a sense amplifier 5 for amplifying data read from a specific memory cell in the memory cell array 2, and an output buffer 7 are provided.

When the chip enable CE goes high, the sense amplifier 5 starts the sensing operation, and the current consumption increases accordingly. When both the chip enable CE and the output enable OE go high, the output of the AND gate G1 in FIG. 5 goes high,
The output buffer 7 outputs a logical signal according to the output of the sense amplifier 5.

As shown in FIG. 6, the current consumption Idd of the memory increases when the chip enable CE goes high. In particular, when the chip enable CE changes from the low level to the high level, the internal circuit starts operating, and the current consumption transiently increases sharply.

Further, even if the logic of the chip enable CE does not change, if the addresses A0 to A7 change, the current consumption Idd transiently increases.

FIG. 7 shows the current consumption when the memory read cycle is short, and FIG. 8 shows the current consumption when the memory read cycle is long. As shown in these figures, as the read cycle of the memory becomes longer, the amount of transient current consumption accompanying a change in address decreases, so that the average power consumption decreases.

However, the illustrated portion of the consumption current Idd in FIG. 7 or the portion B in FIG. 8 is a current that constantly flows while the chip enable CE is at the high level, and this current Idd is read out. It does not decrease even if the period is lengthened.
In order to reduce the current consumption Idd, it is desirable to disable (unselect) the chip enable CE.

[0009]

FIG. 9 is a timing chart showing an example in which the period during which the chip enable CE is enabled (selected) is shortened. As illustrated, when the chip enable CE is changed from “H” to “L” (non-selected state), data cannot be read from the memory, so that the chip enable CE cannot be unnecessarily set to the non-selected state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption at the time of data reading, a data reading method thereof, and a semiconductor integrated circuit device. To provide.

[0011]

According to one aspect of the present invention, there is provided a memory cell array, a sense amplifier for amplifying data read from a specific memory cell in the memory cell array, and An output buffer connected to an output terminal of a sense amplifier, comprising: a latch circuit connected between the sense amplifier and the output buffer for latching an output of the sense amplifier; The output of the sense amplifier is latched by the latch circuit in a state where the output of the buffer is in a high impedance state, and a signal corresponding to the latch output of the latch circuit is output in a state in which the sense operation of the sense amplifier is stopped. Output from the buffer.

Since the output of the sense amplifier is latched by the latch circuit and then supplied to the output buffer, the sense operation of the sense amplifier can be stopped after the latch, and power consumption can be reduced.

According to the second aspect of the present invention, since the operation state of the sense amplifier is switched independently of the transition of the address signal to the memory cell array, it is possible to perform control to shorten the sense operation time of the sense amplifier as much as possible.

According to the third aspect of the present invention, the sense amplifier performs the sensing operation only when the first enable signal (for example, a chip enable signal) has the first logic (for example, high level), and the latch circuit performs Only when the 1 enable signal switches from the first logic to the second logic (for example, low level), the output of the sense amplifier is latched.

According to a fourth aspect of the present invention, after the latch circuit latches the output of the sense amplifier, the sense operation of the sense amplifier is stopped, and thereafter, the output buffer is enabled, and the signal corresponding to the latch output of the latch circuit is output. Is output.

According to the fifth aspect of the present invention, the power consumption of a chip in which a semiconductor memory device and a central processing unit (CPU) are mounted can be reduced. If such a chip is mounted on an IC card or the like, the battery life is improved and the usability is improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device and a semiconductor integrated circuit device according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an internal configuration of a semiconductor memory device according to the present invention. The semiconductor memory device of FIG. 1 includes a memory cell array 2 having a plurality of memory cells 1 connected to intersections of word lines W1 to Wn arranged in a row direction and bit lines B1 to Bm arranged in a column direction; , A column decoder 4 for controlling a column line voltage, a sense amplifier 5 for amplifying data read from a specific memory cell 1, and a latch for latching the output of the sense amplifier 5. Circuit 6
And the output of the latch circuit 6 and the data output terminal 8
And an output buffer 7 for supplying the same.

The sense amplifier 5 has a chip enable CE.
Performs a sensing operation only when is at a high level. The latch circuit 6 latches the output of the sense amplifier 5 when the chip enable CE changes from the high level to the low level. The output buffer 7 has an output enable OE
Is high only when the output of the latch circuit 6 is fetched. When the output enable OE is at a low level, the output of the output buffer 7 enters a high impedance state.

FIG. 2 is a timing chart of input / output signals of the semiconductor memory device of FIG.
Current consumption Idd, chip enable CE, output
3 shows timing waveforms of output signals D0 to D7 output from the enable OE and the data output terminal 8.

Hereinafter, the read operation of the semiconductor memory device of FIG. 1 will be described with reference to the timing chart of FIG. When the addresses A0 to A7 to be read are determined (at time t in FIG. 2).
1), the chip enable CE is enabled (high level). As a result, the sense amplifier 5 starts the sensing operation, and the consumption current Idd increases.

In this state, data read from the specific memory cell 1 corresponding to the addresses A0 to A7 is input to the sense amplifier 5 and amplified.

At time t2, chip enable CE
Is disabled (low level), the sense amplifier 5 stops the sensing operation, and the latch circuit 6 latches the output of the sense amplifier 5. In this state, since the output enable OE is in the disabled state (low level), the output of the output buffer 7 is in the high impedance state.

At time t3, output enable OE is enabled (high level), and output buffer 7 latches the output of latch circuit 6. Thereby, the data of the specific memory cell 1 is read from the output terminal.

As described above, in the present embodiment, in each memory cycle, the period in which the chip enable CE is enabled and the output enable OE is disabled (period A in FIG. 2), the chip enable CE and the output In this case, a period is provided in which both the signal enable OE is in the disabled state (period B in FIG. 2) and a period in which the chip enable CE is in the disabled state and the output enable OE is in the enabled state (period C in FIG. 2). There are features.

That is, conventionally, data cannot be written or read unless the chip enable CE which is a control signal for activating the chip is in an enabled state. For this reason, the chip enable CE cannot be disabled indiscriminately, and the current consumption Idd cannot be suppressed.

On the other hand, in the present embodiment, the data read from the memory cell is sensed by the sense amplifier 4 and then the chip enable CE is disabled to temporarily latch the output data from the sense amplifier 5. The data is held in the circuit 6 and output to the outside of the chip via the output buffer 7. By adopting such a configuration, the period in which the chip enable CE is in the enable state is shortened, and the current consumption is suppressed.

Further, in this embodiment, as shown in FIG. 1, since the output of the sense amplifier 5 is temporarily latched by the latch circuit 6, after the latch, the chip enable CE is latched.
Is disabled, the output of the latch circuit 6 can be supplied to the output buffer 7 even when the sense operation of the sense amplifier 5 is stopped.

FIG. 3 shows the semiconductor memory device of this embodiment and the CP.
FIG. 14 is a diagram showing an example in which U is mounted in the same chip. FIG.
Chips are a CPU 11, a mask ROM 12, an SR
AM (Static RAM) 13 and EEPROM (Electrically Erasab)
le and Programmable ROM) 14 and a logic circuit unit 15. A program executed by the CPU 11 is stored in the mask ROM 12. The SRAM 13 is used as a high-speed accessible work area such as a data cache. The EEPROM 14 is used as a nonvolatile and rewritable data recording medium.

The logic circuit section 15 controls the timing of each block in the chip. The above-described chip enable CE and output enable OE are output from the logic circuit unit 15.

The mask ROM 12, SRAM 13, FIG.
At least one of the EEPROM 14 and the EEPROM 14 is configured by a circuit similar to that of FIG. Thereby, the power consumption of the chip can be reduced.

If the chip shown in FIG. 3 is mounted on an IC card medium, a high-performance IC card with low power consumption can be realized.
Further, a communication circuit may be mounted on the IC card.
Thereby, various kinds of information can be transmitted and received without contact.

As described above, in the present embodiment, the latch circuit 6 is provided between the sense amplifier 5 and the output buffer 7, and after the output of the sense amplifier 5 is latched by the latch circuit 6, the latch output of the latch circuit 6 is output. Since the data is transmitted to the output buffer 7, the data read from the memory can be normally output even after the sense operation of the sense amplifier 5 is stopped after the data is latched by the latch circuit 6. Therefore, the sensing operation time of the sense amplifier 5 can be reduced, and power consumption can be reduced.

The mounting form of the semiconductor memory device according to the present invention is not necessarily limited to that shown in FIG. Further, the present invention may be applied to other types of memories such as a DRAM (Dynamic RAM).

[0035]

As described above in detail, according to the present invention, the latch circuit is provided between the sense amplifier and the output buffer, and the output of the sense amplifier is latched by the latch circuit. Can reliably read data from a specific memory cell even when the sense operation of the sense amplifier is stopped. Therefore, the sense operation time of the sense amplifier can be reduced, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart of input / output signals of the semiconductor memory device of FIG. 1;

FIG. 3 is a diagram showing an example in which the semiconductor memory device of the embodiment and a CPU are mounted in the same chip.

FIG. 4 is a diagram showing a configuration of external pins of a general read-only memory.

FIG. 5 is a schematic block diagram showing the internal configuration of a conventional memory.

FIG. 6 is a timing chart of each input / output terminal of the memory.

FIG. 7 is a diagram showing current consumption when a read cycle of a memory is short.

FIG. 8 is a diagram showing current consumption when a read cycle of a memory is long.

FIG. 9 is a timing chart showing an example in which the period during which the chip enable CE is set to the enable state (selection state) is shortened.

[Explanation of symbols]

 1 Memory Cell 2 Memory Cell Array 3 Row Address Decoder 4 Column Decoder 5 Sense Amplifier 6 Latch Circuit 7 Output Buffer 8 Output Pad

Claims (7)

[Claims] 1. A memory cell array, a decoder circuit for selecting a specific memory cell in the memory cell array, and an operation state switched in accordance with a logic of a first control signal to read from the specific memory cell A sense amplifier that amplifies the read data, and an output buffer that outputs data corresponding to an output signal of the sense amplifier. The semiconductor memory device, comprising: a sense amplifier connected between the sense amplifier and the output buffer; A latch circuit for holding an output of the amplifier, wherein the output of the sense amplifier is held by the latch circuit, and the sense circuit is held by the latch circuit in a state where the sense operation of the sense amplifier is stopped by the first control signal. A signal corresponding to the received data is output from the output buffer by the second control signal.憶 apparatus. 2. The semiconductor memory device according to claim 1, wherein an operation state of said sense amplifier is switched separately from a transition of an address signal to said memory cell array. 3. The sense amplifier performs a sensing operation only when the first control signal has a first logic, and the latch circuit determines that the first control signal is a second logic from the first logic. The output buffer holds the output of the sense amplifier when changing to a logic, and outputs a signal corresponding to the output of the latch circuit only when the second control signal has a predetermined logic. 3. The semiconductor memory device according to claim 1, wherein the output is in a high-impedance state other than the above. 4. The method according to claim 1, wherein the first control signal is set to the first logic, the first control signal is set to the second logic, and then the second control signal is set to the predetermined logic. 4. The semiconductor memory device according to claim 3, further comprising a control circuit for setting a logic value. 5. A memory cell array, a decoder circuit for selecting a specific memory cell in the memory cell array, a sense amplifier for amplifying data read from a specific memory cell in the memory cell array, and the sense amplifier A data read method for a semiconductor memory device, comprising: an output buffer that outputs data according to the output signal of (b), wherein an output of the sense amplifier is held by a latch circuit, and then the sense operation of the sense amplifier is stopped. And outputting a signal corresponding to a latch output of the latch circuit from the output buffer in a state. 6. The data reading method according to claim 5, wherein the operation state of said sense amplifier is switched separately from a transition of an address signal to said memory cell array. 7. A semiconductor integrated circuit device, wherein the semiconductor memory device according to claim 1 and a central processing unit are mounted on the same chip.