JP2001142774A - Memory card and address conversion method applied to the card - Google Patents

Abstract

(57) Abstract: An object of the present invention is to prevent an increase in a volatile memory area for an address conversion table even when the storage capacity of a rewritable nonvolatile memory increases. An LTPb 152-i having an entry group in which a physical address of a block to which a logical block address is assigned is registered in the flash memory 15 in units of a block group having a common content of a predetermined field of the logical block address. , One of the LTPb 152-i is R
Stored in AM14. When given a logical address from the host system, the microprocessor 121 checks whether or not the corresponding LTPb 152-i exists in the RAM 14. If not, the microprocessor 121 copies the LTPb 152-i from the flash memory 15 to the RAM 14 and then exists. At this time, the conversion to the physical address is performed by referring to the corresponding entry of the LTPb 152-i on the RAM 14 by the logical block address in the logical address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card having a rewritable nonvolatile memory, and more particularly to an address conversion mechanism for converting a logical address given to access the nonvolatile memory into a physical address. The present invention relates to a memory card provided and an address conversion method applied to the card.

[0002]

2. Description of the Related Art In recent years, as a storage device for storing various digital information represented by image data and music data, a rewritable non-volatile memory which does not lose stored information even when the power is turned off is mounted. Memory cards are spreading.

A typical rewritable nonvolatile memory is a NAND flash memory. This type of flash memory is managed in block units. That is, information erasure (generally, data in which all bits are “1”, that is, operation of writing all “1” data) is performed in block units. Each block is assigned a logical block address. Each block is composed of a plurality of sectors. This sector is the minimum unit of reading / writing in the flash memory, and is composed of, for example, 512 bytes. Each sector has a redundant part separately from the data part. A logical block address assigned to a block to which a corresponding sector belongs is registered in a predetermined field of the redundant section.

In order to access a flash memory (rewritable nonvolatile memory), an address translation table (address translation mechanism) for translating a logical address into a physical address of the memory is required. The reason that this address conversion is necessary is that even if a defective block occurs in the flash memory and it is replaced with another free block, the same logical address is used regardless of whether or not the replacement is performed, without the host being aware of this. This is to allow access at

The number of entries in the address conversion table matches the number of blocks in the flash memory, and one sector has five entries.
12 bytes, that is, 0.5 KB (kilobyte), and one block has 32 sectors, that is, 16 MB of 16 KB
Taking a case where a (megabyte) flash memory is used as an example, 16 MB / 16 KB = 1K = 1,024.
The address translation table generally has an R as a volatile memory.
It is used by storing it in an area (RAM area) secured on the AM. Therefore, in the above example, if one entry is 2 bytes, the RAM area required to store the address conversion table is 2 KB.

On the other hand, recently, the storage capacity of the flash memory has increased due to the advance of the semiconductor manufacturing technology, and the number of blocks is 2,048, the 32 MB flash memory is 16 KB in one block, or the number of blocks is 4,096, A 64 MB flash memory having a block size of 16 KB has also appeared.

[0007] However, as the storage capacity of the flash memory increases, an R for holding the address conversion table is required.
The AM area must also be large. For example, 32M
A 4 KB RAM area is required for the B flash memory, and an 8 KB RAM area is required for the address translation table for the 64 MB flash memory. In other words, a RAM area that is twice or four times as large as that of the 16 MB flash memory is required.

[0008]

As described above, in a conventional memory card equipped with a rewritable nonvolatile memory typified by a flash memory, when the storage capacity of the memory increases, the memory is accessed. In addition, the area of the volatile memory typified by the RAM, which is necessary to hold the address conversion table for converting the logical address given to the block into the physical address of the block, has to be increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the need for increasing the volatile memory area for the address conversion table even when the storage capacity of the rewritable nonvolatile memory increases. A card and an address conversion method applied to the card.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a memory card having a rewritable nonvolatile memory, which is used for converting a logical address given to access the rewritable nonvolatile memory into a physical address. A plurality of address translation tables respectively associated with different logical address ranges, the plurality of address translation tables stored in the rewritable nonvolatile memory, and the plurality of address translations on the rewritable nonvolatile memory. When a volatile memory for securing an address translation table area for storing one of the tables and a logical address for accessing the rewritable nonvolatile memory are provided, the address translation on the volatile memory is performed. Convert the logical address to a physical address using the table. Characterized by comprising an address converting means for.

In such a configuration, an address conversion table for converting a logical address into a physical address is divided into different logical address ranges, and is stored in a rewritable nonvolatile memory as a plurality of address conversion tables. On the other hand, one of them is placed in the address conversion table area on the volatile memory. Here, when a logical address for accessing the rewritable nonvolatile memory is given, an address conversion for converting the logical address into a physical address is performed using an address conversion table on the volatile memory.

As described above, since only a part of the address translation table is placed in the volatile memory and used for address translation from the logical address to the physical address, the case where the entire address translation table is placed in the volatile memory No,
Even if the capacity of the rewritable nonvolatile memory increases,
It is possible to suppress an increase in the storage capacity of the rewritable nonvolatile memory.

Here, if the address translation table stored in the volatile memory is not the address translation table corresponding to the logical address range to which the given logical address belongs, the address translation cannot be performed.

Therefore, when a logical address for accessing the rewritable nonvolatile memory is given, it is determined whether or not an address conversion table corresponding to the logical address range to which the logical address belongs exists in the volatile memory. Hit / miss hit determination means and the hit / miss
Copy means for copying the corresponding address translation table from the rewritable nonvolatile memory to the address translation table area on the volatile memory when the corresponding address translation table is determined not to be present in the volatile memory by the mishit decision means. And should be added.

In this way, even if the address translation table required to translate a given logical address to a physical address does not exist in the table area (mis-hit), the table is stored in the rewritable nonvolatile memory. Since the data is copied to the table area, the conversion from the logical address to the physical address can be performed quickly.

Here, unlike the above configuration of the present invention,
If each of the address conversion tables is not prepared in the rewritable nonvolatile memory and only one of the address conversion tables is created and held in the table area, an address on the table area is used. If the conversion table is a mishit that is not a table necessary for address conversion, the necessary table must be created again, and real-time performance is required as in the case of reading (reproducing) video data and audio data. This is a problem when That is, the penalty at the time of a table mistake is large. In order to avoid this, it is conceivable to create and hold all tables in the table area, but this causes a large increase in the storage capacity of the rewritable nonvolatile memory.

On the other hand, in the present invention, since all the address conversion tables are prepared in the rewritable nonvolatile memory, even if a table error occurs, the necessary address conversion tables are volatilized from the rewritable nonvolatile memory. The address conversion process can be performed promptly only by copying to the table area of the dynamic memory, and the penalty at the time of a table error can be reduced. Therefore, in the present invention, even if a small-capacity rewritable nonvolatile memory is used, that is, even if a table area having a sufficient size cannot be secured, it is possible to reduce a penalty at the time of a table error, and to realize a real-time application Applicable.

In the present invention, it is necessary to secure an area for storing all the address conversion tables in the rewritable nonvolatile memory, but the capacity of the rewritable nonvolatile memory is larger than that of the volatile memory. This is not a problem unlike the configuration in which all tables are placed on the volatile memory.

Here, in order to copy the address conversion table required for the address conversion from the rewritable nonvolatile memory to the table area more quickly, the address conversion table is stored in the rewritable nonvolatile memory in which each address conversion table is stored. It is preferable to provide a pointer table in which the storage location information is registered in association with a logical address range unique to the address conversion table.

Further, the pointer table is also stored in the volatile memory (pointer table area secured in the volatile memory), and a storage location of a required address conversion table is stored using the pointer table on the volatile memory. With the configuration for acquiring information, the address conversion table can be more quickly copied from the rewritable nonvolatile memory to the table area.

Further, if a reference table designating means for designating which of the address conversion tables is stored in the volatile memory is added, the judgment by the hit / miss hit judging means (table hit) / Judgment) can be performed promptly.

In the memory card of the present invention, the rewritable nonvolatile memory can be specified by a logical block address in a logical address in consideration of the fact that the rewritable nonvolatile memory generally comprises a plurality of blocks to which a unique logical block address is assigned. A plurality of address conversion tables each having a group of entries in which physical addresses of the rewritable nonvolatile memory of the block to which the logical block address is assigned are registered, wherein the contents of a predetermined field of the logical block address are common. A plurality of address conversion tables prepared in groups and stored in the rewritable nonvolatile memory, and an address conversion table area for storing one of the plurality of address conversion tables on the rewritable nonvolatile memory are provided. Volatile memory reserved and Hit / mishit determining means for determining whether an address conversion table corresponding to the predetermined field of the obtained logical address exists in the volatile memory; and storing the corresponding address conversion table in the volatile memory. When it is determined that the address conversion table does not exist, a copy unit that copies the address conversion table from the rewritable nonvolatile memory to the address conversion table area on the volatile memory, and the corresponding address conversion table exists on the volatile memory. If it is determined that it does not exist, if it is determined that the address does not exist, it waits for the address conversion table to be copied to the volatile memory, and then, based on the logical block address in the given logical address, Refer to the corresponding entry in the address translation table in memory Also characterized in that it comprises an address conversion means for converting a logical address into a physical address.

Here, it is possible to set the contents of each entry of each address translation table in advance, but first, only the framework of the table is prepared and the entry of the address translation table referred to by the address translation means is prepared. If the physical address (or physical block address) is not registered in the rewritable nonvolatile memory, a free block in the rewritable nonvolatile memory is searched, and a logical block address in the requested logical address is allocated to the block, and the physical block of the block is assigned. Address (or physical block address)
May be written into the above-mentioned reference entry and the corresponding entry of the address conversion table in the rewritable nonvolatile memory by the physical address registration means. As a result, it is possible to eliminate the waste of pre-registering even the information of the entry in the address conversion table corresponding to the block that is unlikely to be used.

When a block error occurs as a result of writing to the rewritable nonvolatile memory by using the physical address converted by the address conversion means, a free block in the rewritable nonvolatile memory is searched for the block. Is assigned a logical block address in the given logical address, and the reference entry and the corresponding address translation table entry in the rewritable nonvolatile memory are updated with the physical address (or physical block address) of the block. Block alternatives may be added. By providing such a block replacement means, even if a block error occurs at the time of writing, it is possible to reliably perform the block replacement processing.

At the time of startup, a table creation judging means for judging whether or not an address conversion table is created and stored in the rewritable nonvolatile memory is added, and it is determined that the address conversion table is created and stored. In this case, any one of the address conversion tables may be copied to the address conversion table area on the volatile memory by the copying unit. At this time, the pointer table may be copied to the pointer table area on the volatile memory.

The present invention relating to the above-described apparatus (memory card) is also realized as an invention relating to a method (address conversion method).

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a memory card according to one embodiment of the present invention.

The memory card is used by being mounted on various electronic devices such as a personal computer, an electronic camera, and a game machine. As shown in FIG. 1, the memory card includes an interface (host interface) 11 with an electronic device main body (hereinafter, referred to as a host system) to which the card is mounted, and a control unit 12 that controls the entire card.
And a ROM 13 as a read-only nonvolatile memory
And a RAM 14 as a volatile memory and a flash memory 15 as a rewritable nonvolatile memory.

The control unit 12 includes a host interface 11
Interprets the command received via the ROM 13 according to a control program (firmware) stored in the ROM 13.
It has a microprocessor (MPU) 121 to execute, and a register (REG) 122 to be described later.

The ROM 13 is used to store a control program, fixed data for management, and the like in advance. RAM1
Reference numeral 4 denotes a work area (not shown) of the control unit 12 (the microprocessor 121 therein) and an LTPa 151 described later.
LTPa area 141 for storing the
An LTPb area 142 for storing the 52-i is provided. Here, the size of the LTPb area 142 is 2 KB.

The flash memory 15 is, for example, a NAND
The area of the flash memory 15, which is a flash memory, is allocated to a management area 153 and a data area 154 for storing digital contents such as image data and music data.

The flash memory 15 is composed of a plurality of blocks as shown in FIG. This block is a unit of data erasing, and a logical block address in a logical address (Logical Address; LA) is assigned in units of the block. That is, the flash memory 1
5 is managed in units of blocks.

Each block of the flash memory 15 is composed of a plurality of sectors which are the minimum unit for writing / reading data to / from the memory 15. Therefore, when the data write target area requested by the host system is a part of a sector, the operation of once reading the data of the sector, replacing the relevant part with the write data, and writing the replaced data to the sector is performed. Is performed. Similarly, when the data read target area requested by the host system is part of a sector,
The operation of reading the data of the sector, selecting the data of the corresponding part from the data and sending it to the request source is performed.

Each sector is provided with a redundant portion. In this redundant portion, in addition to the error detection code ECC, a logical block address assigned to a block to which the sector belongs is set.

In this embodiment, one block of the flash memory 15 is composed of 32 sectors, and one sector is 51 sectors.
It shall consist of 2 bytes. That is, in the present embodiment, one block is composed of 16 KB. In this case, assuming that the logical address (LA) is composed of 32 bits, as shown in FIG. 3, the lower 9 bits of the logical address become an address in the sector indicating the position of byte data in the sector. The 5 bits following the upper side of the intra-sector address become the sector address indicating the sector position (within the block). The remaining 18 bits are a logical block address indicating a logical block position (hereinafter, referred to as an 18-bit logical block address). However, in the present embodiment, the upper 14 bits excluding the 4 most significant bits of the logical address, that is, the remaining 14 bits excluding the upper 4 bits of the 18-bit logical block address are used as the substantial logical block address (hereinafter, 14 bits). (A bit logical block address). The reason is as follows.

First, the maximum capacity of the flash memory 15 of the memory card applicable in the present embodiment is limited to 256 MB. In this case, the upper 4 bits of the 32-bit logical address (18-bit logical block address) for accessing the flash memory 15 are always "0". Therefore, a logical block can be specified only with (the logical block address of) the remaining 14 bits excluding these 4 bits.

In this embodiment, the flash memory 1
It is assumed that a 64 MB flash memory is used for 5. In this case, the number of blocks in the flash memory 15 is
As described above, since one block is 16 KB,
64 MB / 16 KB = 4K = 4,096.

In the management area 153 of the flash memory 15, LTPa 151 as a pointer table and a plurality of LTPb 152-i (i
= 0 to 2 ^m -1) is stored. This LTPa 151 is also stored in the LTPa area 141 of the RAM 14 as described above. That is, the LTPa 151 is resident in the RAM 14. Further, any one of the plurality of LTPb 152-i is stored in the LTPb area 14 of the RAM 14 as described above.
2 is also stored.

The total number of entries of a plurality (2 ^m ) of LTPb 152-i is equal to the number of blocks of the flash memory 15, and is 4K when the flash memory 15 is 64 MB.
(4,096). Also, one LTPb 152-i
Is the size of the LTPb area 1 that can be secured on the RAM 14.
42 size. Here, the LTPb area 142
Is 2 KB in size. Therefore, LTPb152
Assuming that the size of one entry of -i is 2 bytes, the number of entries of LTPb 152-i that can be stored in the 2KB LTPb area 142 is 2KB / 2 bytes = 1K (= 1,024)
It is. In this case, the number of LTPb 152-i (2 ^m )
Means that the number of blocks in the flash memory 15 is 4K (= 4,
096), 4K / 1K = 4 (m = 2)
Becomes That is, in the present embodiment, as shown in FIG.
LTPb 152-0 to 152-3 are flash memory 1
5 in the management area 153.

Here, the entry contents of LTPb 152-i will be described. In the present embodiment, in which the maximum capacity of the flash memory 15 is limited to 256 MB, the value of the upper 8 bits of the 18-bit logical block address (the upper 4 bits of the 14-bit logical block address) is 2 ^{10 of the} LTPb 152-i. = 1,24 blocks, the physical addresses (Phys of the blocks on the flash memory 15)
of the physical address (PA), excluding the sector address and the intra-sector address, that is, the physical block address (as a block pointer) is set to 1,24 entries (entries set in association with the corresponding logical block address). 0 to 1023).

By using the above LTPb152-i,
The logical address (LA) is changed to the physical address (PA) of the flash memory 15 corresponding to the logical address (LA).
(Logical address To Physical addres
s translation (LTP). Specifically, by referring to the LTPb 152-i using the 14-bit logical block address in the logical address (LA), the logical block address is changed to the physical block address registered in the corresponding entry as shown in FIG. Convert to The lower 14 bits of the logical address (LA) (14 bits consisting of a sector address and an intra-sector address) are connected to the lower side of the physical block address, so that the physical address corresponding to the logical address (LA) is obtained. (PA).

Next, the LTPa 15 will be described. LTP
a151 is the (start position) of the plurality of LTPb 152-i.
The physical address of the storage start (Physical Addre) as information (storage position information) indicating the storage destination on the flash memory 15
ss; PA) (as LTPb pointer)
Of entries set in association with the value of. The number of entries of this LTPa 151 is four in the example where the number of LTPb 152-i is four. Therefore, LTPa15
One entry can be referenced (specified) by the lower two bits of the upper four bits of the 14-bit logical block address. However, the maximum capacity of the flash memory 15 is 2
In the present embodiment in which the LTPb area 142 is 2 KB and the LTPb area 142 is 2 KB, the 14-bit LTPb 152-i is used so that the same procedure can be performed as when the capacity of the flash memory 15 is 64 MB. The entry of the LTPa 151 is referred to by the value of the upper 4 bits of the logical block address. This LTPa15
By using 1, it is possible to acquire information on the storage location of LTPb 152-i necessary for converting a logical address (LA) into a physical address (PA).

At a predetermined position, for example, the head of the management area 153 of the flash memory 15, the head physical address PAa of the LTPa 151 in the flash memory 15 is set to LT.
It is set as a Pa pointer.

Next, with respect to the operation of the memory card having the configuration shown in FIG. 1, (1) a process at the time of startup and (2) a process at the time of receiving an access request will be sequentially described.

(1) Processing at Startup First, processing at the start-up of the memory card of FIG. 1, for example, at power-on, will be described with reference to the flowchart of FIG.

Microprocessor 121 in control unit 12
When, for example, the power of the host system is supplied to the memory card in FIG. 1, the LTPa 151 and the LTPb 152-i
Is created or stored in the flash memory 15 (step S1). This determination process is performed by checking whether or not data is written at, for example, the head address of the flash memory 15 (specifically, whether or not data is all “1”, that is, whether or not the flash memory 15 is in an erased state). Will be

The microprocessor 121 has the LTPa1
When it is determined that the LTPb 152-i and the LTPb 152-i have not been created and stored, the number of entries A of the LTPb 152-i is determined (step S2). The number A of entries of the LTPb 152-i is determined by, for example, A = B / C from a predetermined size B of the LTPb area 142 and a size C of one entry of the LTPb 152-i. Here, assuming that B = 2 KB and C = 2 bytes, A
= 2KB / 2 bytes = 1K = 1,024.

Next, the microprocessor 121 executes the LTP
The number D of b152-i is determined (step S3). This L
The number D (= 2 ^m ) of TPb 152-i is obtained by changing the number E of blocks of the flash memory 15 to the number A of entries of LTPb 152-i.
, That is, D = E / A. The number E of blocks of the flash memory 15 is 1
From the size H (= F × G) of one block calculated from the number F of sectors of the block and the number G of bytes of one sector, and the capacity I of the flash memory 15, E = I / H = I / (F
× G). Here, assuming that the number of sectors F in one block is 32 and the number of bytes in one sector is 512,
The size H of one block is 32 × 512 = 16 KB. Therefore, the number E of blocks in the flash memory 15 with I = 64 MB is E = I / H = 64 MB / 16 KB = 4.
K = 4,096.

The microprocessor 121 has the LTPb1
When the number D of the 52-i and the number A of the entries of the LTPb 152-i are determined, the framework (format) of the LTPb 152-i having the determined number of entries A is changed to the management area 153 of the flash memory 15 by the determined number D. It is created and stored on the top (step S4). Here, A = 1,
024 and D = 4, as shown in FIG. 4, four LTPb 152-0 to 15 having 1,024 entries.
A 2-3 frame is created and stored in the management area 153 of the flash memory 15. At this point, LTPb
Nothing is written in each of the entries 152-0 to 152-3. Then, the microprocessor 121 creates an LTPa 151 having a group of entries in which information (head physical address) of storage positions of the created and stored D (= 4) LTPb 152-i on the flash memory 15 is registered. Then, it is stored in the management area 153 of the flash memory 15 (step S5). At this time, the microprocessor 121
Registers the information of the storage position of the LTPa 151 on the flash memory 15 (head physical address PAa), for example, at the head position of the flash memory 15. This allows
In the subsequent startup processing, LTPa 151 and LTP
It is determined that b152-i has been created and stored. In step S5, the microprocessor 121 stores the created LTPa 151 in the LT of the RAM 14.
It is stored in the Pa area 141. If the LTPa 151 is created on the LTPa area 141, this storing operation is not required.

Next, at step S1, the LTPa 15
1 and LTPb 152-i will be described when it is determined that they have been created and stored. In this case, the microprocessor 121
An LTPa 151 is stored in the LTPa area 141 of the M14, and one of the LTPb 152-i is stored in the LTPb area 142 of the RAM 14 from the flash memory 15 (here, LTPb1).
52-0 to 152-3, for example, LTPb152-0)
Are copied (step S6). Then, the microprocessor 121 reads the LTPb area 1 of the RAM 14
The information indicating the LTPb 152-i copied to the RAM 42, that is, the information indicating that the LTPb 152-i exists on the RAM 14 is set in the register 122 (step S7). In the present embodiment, the register 122 holds valid flags V0 to V15 for 16 tables in consideration of the number of LTPb 152-i generated and stored when the capacity of the flash memory 15 is 256 MB. The configuration has been applied. Therefore, the LTPb area 142 of the RAM 14
By turning on only the valid flag Vi corresponding to the LTPb 152-i copied to the
TPb152-i can be identified. That is, in the present embodiment, the valid flag Vi is set to the L
This is information indicating TPb 152-i.

(2) Processing when Access Request is Accepted Next, in the memory card shown in FIG. 1, processing when an access request to the flash memory 15 from the host system is received by the host interface 11 and accepted by the microprocessor 121 , Will be described with reference to the flowcharts of FIGS.

First, the access request sent from the host system includes a command indicating write or read access, and a logical address (LA) indicating a head position of an access target area in a logical address space.
And the size of the area.

The microprocessor 121 checks whether the logical address in the access request from the host system is within the range of the logical address space allocated to the data area 154 of the flash memory 15 (Step S11). .

If the value is outside the above range, the microprocessor 121 notifies the host system of an error as an access violation. On the other hand, if it is within the range, the microprocessor 121 determines whether or not the LTPb 152-i corresponding to the requested logical address exists in the RAM 14 (Step S12). Before this step S12, it is checked from the requested logical address and size whether the access request extends over a plurality of blocks. If so, an access violation is returned. It is preferable to proceed to step S12. In addition, when an access request extends over a plurality of blocks, the access request may be converted into an access request for each block, and internally processed as a plurality of access requests.

Here, the determination method in step S12 will be described. First, the microprocessor 121 refers to the valid flag Vi in the register 122 specified by the value i of the upper 4 bits of the 14-bit logical block address in the requested logical address. Then, the microprocessor 121 determines whether or not the LTPb 152-i corresponding to the requested logical address exists in the RAM 14 based on whether or not the valid flag Vi referred to is on. It should be noted that a selector for selecting the corresponding valid flag Vi according to the value i of the upper 4 bits of the 14-bit logical block address may be prepared, and the above determination may be made according to the logical state of the output of this selector.

When it is determined that the LTPb 152-i corresponding to the requested logical address does not exist in the RAM 14, the microprocessor 121 transfers the LT from the flash memory 15 to the LTPb area 142 of the RAM 14.
The Pb 152-i is copied (step S13). This L
The information (physical address) of the storage location of the TPb 152-i on the flash memory 15 is determined by the value of the upper 4 bits i of the 14-bit logical block address in the logical address, and the LTPa 15 in the LTPa area 141 of the RAM 14.
1 can be obtained by referring to the corresponding entry.

Then, the microprocessor 121 turns on the validity flag Vi in the register 122 specified by the value i of the upper 4 bits of the 14-bit logical block address in the logical address (step S14). At this time, if there is another valid flag that is already on, the valid flag is turned off.

The microprocessor 121 stores the LTPb 152-i corresponding to the requested logical address in the RAM 14
If it is determined that the information does not exist on the upper side, the above-described step S1 is performed.
3. After S14, if it is determined that the address exists, the process directly proceeds to step S15 to perform an address conversion process of converting the requested logical address into a physical address using the LTPb 152-i in the LTPb area 142. .

The details of the address conversion process in step S15 will be described below with reference to the flowchart in FIG.
First, the microprocessor 121 uses the 14-bit logical block address in the requested logical address to write the RA
LTPb located on the LTPb area 142 of M14
The corresponding entry of 152-i is referred to (step S3).
1).

Next, the microprocessor 121 determines whether or not the data is written in the referenced entry (whether the data is in the erased state or all "1"), and determines the physical address of the block designated by the 14-bit logical block address. It is determined whether or not (PA) is set (step S32). In the present embodiment, what is actually registered in the entry of LTPb 152-i is the lower one of the physical address.
This is a physical block address excluding 4 bits. But,
1 in which all bits are “0” at the lower side of the physical block address
If 4-bit data, that is, 14-bit all “0” data is concatenated, it indicates the head physical address of the corresponding block, and is substantially the same as the registration of the physical address.

When the physical address (physical block address) is not set in the reference entry, the microprocessor 121
4, one empty block in which no logical block address is written is reserved in the empty area, that is, the redundant section of each sector in the block, and the requested logical address is stored in the redundant section of each sector of the empty block. The middle logical block address is written (step S33). That is, a logical block address in the requested logical address is allocated to the reserved empty block.

Next, the microprocessor 121 has a RAM
LTPb1 located on the 14 LTPb area 142
The reference entry 52-i and the LTPb 152 of the plurality of LTPb stored in the flash memory 15
-i corresponding entry (entry specified by 14-bit logical block address in requested logical address)
Then, the head physical address (the 14-bit physical block address therein) of the secured (the logical block address has been allocated) block is written (step S3).
4).

If a physical address (physical block address) is set in the entry referred to, the microprocessor 121 sets the physical address (physical block address) if it is not set. The newly written physical address (physical block address) is obtained (step S35). In the configuration in which the physical block address is obtained as in this embodiment, the lower 14 bits of the requested logical address (that is, the 5-bit sector address and the 9-bit sector By concatenating (14 bits consisting of an address), a target physical address can be obtained. When applying a configuration in which a physical address whose lower 14 bits are all “0” is applied, the lower 1 bit of the requested logical address is added to the physical address.
The target physical address can also be obtained by adding 4 bits. Thus, the address conversion processing in step S15 ends.

When the microprocessor 121 obtains the physical address (PA) of the flash memory 15 corresponding to the requested logical address (LA) in the address conversion end processing in step S15, the microprocessor 121
The flash memory 15 is accessed using A), and the requested writing or reading is performed on the area of the requested size starting from the position specified by the physical address (PA) (step S16). here,
At the time of read access, read data is transferred to the host system via the host interface 11.

Next, the microprocessor 121 checks whether the access is a write access or a read access (step S17). If the access is a read access, the microprocessor 121 terminates a series of processing at the time of accepting an access request.

On the other hand, in the case of a write access, the microprocessor 121 determines whether there is a write error (step S18). This determination is made by reading the written data and comparing the read data with the original write data. If the comparison result indicates a mismatch, a write error is determined.

If there is no write error, the microprocessor 121 ends a series of processing at the time of accepting an access request. On the other hand, if there is a write error, the microprocessor 121 determines that the entire block including the sector in which the write error has occurred is defective, that is, the block 121 The processing for substitution is performed as follows.

First, the microprocessor 121 secures one free block from the flash memory 15 of the flash memory 15 as an alternative block, and stores the logical portion of the requested logical address in the redundant portion of each sector of the free block. A process similar to the above-mentioned step S33 for writing the block address is performed (step S19).

Next, the microprocessor 121 has a RAM
LTPb1 located on the 14 LTPb area 142
52-i and the corresponding entries in LTPb 152-i of the plurality of LTPbs stored in the flash memory 15, that is, the contents of both entries specified by the 14-bit logical block address in the requested logical address Is updated to the first physical address (the 14-bit physical block address therein) of the reserved alternative block (the logical block address has been allocated) (step S20).

Next, the microprocessor 121 copies the data of the old block determined as a block error to the replacement destination block (step S21). Then, the microprocessor 121 sends the physical address (P) acquired from the physical block address updated in step S20.
Using A), the flash memory 15 is accessed again,
The requested writing is performed on the area of the requested size starting from the position specified by the physical address (PA) (step S22).

If writing is normally performed by this re-access, a series of processing at the time of accepting an access request ends. On the other hand, if a write error occurs again, the block replacement process of step S19 and subsequent steps and the rewrite process for the replacement destination block are performed. If the above processing is repeated a predetermined number of times and the writing is not performed normally, an error ends.

In the above embodiment, the LTPb 152
-i has been described on the assumption that only the framework is created in the initial state, but the LTP in which the entry contents are registered from the beginning
b152-i may be created.

[0073]

As described above in detail, according to the present invention, an address translation table for translating a logical address into a physical address is divided into a plurality of address translation tables and stored in a rewritable nonvolatile memory. On the other hand, only one of them is placed in the address conversion table area on the volatile memory and used for the address conversion. Therefore, even if the storage capacity of the rewritable nonvolatile memory is increased, the capacity of the volatile memory is increased. The increase can be suppressed.

Further, according to the present invention, when the address translation table corresponding to the logical address given to access the rewritable nonvolatile memory is not present in the volatile memory, the address translation table is deleted. Is copied from the rewritable non-volatile memory to the volatile memory and subjected to address conversion. Therefore, even if the storage capacity of the rewritable non-volatile memory is increased, the increase in the capacity of the volatile memory is suppressed. The penalty at the time of a mistake can be minimized and it can respond to real-time use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a memory card according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a block as a management unit of the flash memory 15 in FIG. 1;

FIG. 3 is an exemplary view for explaining a correspondence relationship between a logical address and a physical address applied in the embodiment;

FIG. 4 shows LTPas 151 and L applied in the embodiment.
The figure for demonstrating TPb152-i.

FIG. 5 is a flowchart for explaining startup processing according to the embodiment;

FIG. 6 is an exemplary view showing a part of a flowchart for explaining processing at the time of receiving an access request in the embodiment;

FIG. 7 is an exemplary remaining portion of the flowchart for explaining the process at the time of accepting an access request according to the embodiment;

FIG. 8 is a flowchart illustrating a detailed procedure of an address conversion process in step S15 in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 12 ... Control part 13 ... ROM 14 ... RAM (volatile memory) 15 ... Flash memory (rewritable nonvolatile memory) 121 ... Microprocessor (MPU, address conversion means, hit / miss hit determination means, copy means, physical address registration) Means, block replacement means, table creation determination means, table creation means) 122 ... register (REG, reference table designating means) 141 ... LTPa area (pointer table area) 142 ... LTPb area (address conversion table area) 151 ... LTPa ( Pointer table) 152-0 to 152-3, 152-i LTPb (address conversion table) 153 Management area 154 Data area

Claims (11)

[Claims] 1. A memory card equipped with a rewritable nonvolatile memory, wherein different logical address ranges used to convert a logical address given to access the rewritable nonvolatile memory into a physical address are provided. A plurality of address translation tables associated with each other, wherein one of the plurality of address translation tables stored in the rewritable nonvolatile memory and the plurality of address translation tables on the rewritable nonvolatile memory is stored. And a logical memory for accessing the rewritable non-volatile memory provided with an address conversion table area for the logical memory using the address conversion table on the volatile memory. Address translator that translates addresses into physical addresses A memory card comprising: a step; 2. When a logical address for accessing the rewritable nonvolatile memory is given, whether or not the address conversion table corresponding to a logical address range to which the logical address belongs exists in the volatile memory. Hit / mishit determining means for determining whether or not the corresponding address translation table does not exist in the volatile memory by the hit / mishit determining means. 2. The memory card according to claim 1, further comprising: copying means for copying from the volatile memory to the address conversion table area on the volatile memory. 3. A pointer table in which storage position information in the rewritable nonvolatile memory in which each of the plurality of address conversion tables is stored is associated with a logical address range unique to the address conversion table. When the hit / mishit determination unit determines that the corresponding address conversion table does not exist on the volatile memory, the copy unit refers to the pointer table and stores corresponding storage position information. 3. The memory card according to claim 2, wherein the memory card is acquired and the address translation table on the rewritable nonvolatile memory indicated by the storage location information is copied to the address translation table area on the volatile memory. 4. The apparatus according to claim 1, further comprising a reference table designating unit for designating which of the plurality of address conversion tables is stored in the volatile memory, wherein the hit / mishit determination unit is configured to determine whether the hit / miss hit is determined by the given address conversion table. And determining whether or not the address conversion table corresponding to the logical address range to which the selected logical address belongs exists in the volatile memory based on the contents specified by the reference table specifying means. The memory card as described. 5. A memory card equipped with a rewritable nonvolatile memory composed of a plurality of blocks to which a unique logical block address is assigned, wherein the logical block address, which can be designated by a logical block address in the logical address, is assigned. A plurality of address conversion tables each having a group of entries in which physical addresses of the rewritable nonvolatile memory of the blocks are registered, wherein contents of a predetermined field of the logical block address are prepared in units of a common block group. A plurality of address translation tables stored in a rewritable nonvolatile memory; a volatile memory in which an address translation table area for storing one of the plurality of address translation tables on the rewritable nonvolatile memory is secured; The rewritable nonvolatile When a logical address for accessing a volatile memory is given, hit / mishit determination is performed to determine whether the address conversion table corresponding to the predetermined field of the logical address exists in the volatile memory. Means, when the hit / mishit determination means determines that the corresponding address conversion table does not exist in the volatile memory, reads the address conversion table from the rewritable nonvolatile memory to the volatile memory. Copy means for copying to the address conversion table area; and when the hit / mishit determination means determines that the corresponding address conversion table exists on the volatile memory, it is determined that the corresponding address conversion table does not exist. The address conversion table is previously stored by the copying means. Waiting to be copied to the volatile memory, and referring to the corresponding entry of the address translation table on the volatile memory by the logical block address in the given logical address, the given logical address And an address conversion means for converting the data into a corresponding physical address. 6. When the physical address is not registered in an entry of the address translation table referred to by the address translation means, a search is made for a free block in the rewritable nonvolatile memory, and There is further provided physical address registration means for allocating a logical block address in the logical address and writing the physical address of the block into the reference entry and the corresponding entry in the address conversion table on the rewritable nonvolatile memory. 6. The memory card according to claim 5, wherein: 7. When a block error occurs as a result of writing to the rewritable nonvolatile memory using the physical address converted by the address conversion means, an empty block on the rewritable nonvolatile memory is searched for. A block for allocating a logical block address in the given logical address to the block and updating the reference entry and the corresponding entry of the address translation table on the rewritable nonvolatile memory with the physical address of the block The memory card according to claim 5, further comprising alternative means. 8. The system according to claim 1, further comprising a table creation determining unit configured to determine whether or not the address conversion table is created and stored in the rewritable nonvolatile memory at the time of startup. When it is determined by the means that the plurality of address conversion tables are created and stored in the rewritable nonvolatile memory,
6. The memory card according to claim 5, wherein one of the plurality of address conversion tables is copied to the address conversion table area on the volatile memory. 9. When the table creation determining means determines that the plurality of address conversion tables are not created and stored in the rewritable nonvolatile memory, a framework of the plurality of address conversion tables and the pointer table 9. The memory card according to claim 8, further comprising: a table creating unit for creating a table and storing the table in the rewritable nonvolatile memory. 10. An address conversion method applied to a memory card equipped with a rewritable nonvolatile memory, wherein the method is used to convert a logical address given to access the rewritable nonvolatile memory into a physical address. A plurality of address translation tables, each of which is associated with a different logical address range, is stored in the rewritable nonvolatile memory, and one of the address translation tables is secured in a volatile memory. When a logical address for accessing the rewritable nonvolatile memory is given, the logical address is converted to a physical address using the address conversion table on the volatile memory. Address translation method characterized by performing 11. An address conversion method applied to a memory card equipped with a rewritable nonvolatile memory composed of a plurality of blocks to which a unique logical address is assigned, wherein the address conversion method can be specified by a logical block address in the logical address. An address conversion table having a group of entries in which physical addresses of the rewritable nonvolatile memory of a block to which a logical block address is assigned is prepared for each block group having a common content of a predetermined field of the logical block address. While storing in the rewritable nonvolatile memory, one of the address conversion tables is stored in an address conversion table area secured on the volatile memory, and the logical address for accessing the rewritable nonvolatile memory is If given, It is determined whether or not the address translation table corresponding to the predetermined field of the logical address exists on the volatile memory. If it is determined that the corresponding address translation table does not exist on the volatile memory, The address translation table is copied from the rewritable nonvolatile memory to the address translation table area on the volatile memory. If it is determined that the corresponding address translation table exists on the volatile memory, the address translation table does not exist. If it is determined that the address translation table is copied to the volatile memory, the logical block address in the given logical address refers to the corresponding entry of the address translation table on the volatile memory. And the corresponding logical address is An address translation method characterized by translating into a physical address.