JP2001034571A - Information processing device - Google Patents

Abstract

(57) Abstract: A single personal computer realizes a fault tolerance equivalent to multiplexing by a plurality of personal computers while suppressing an increase in cost. Kind Code: A1 An internal register means for setting a physical division operation mode, an internal register means for setting a plurality of compatible PCI bus spaces, and a plurality of PCI buses for DMA transfer.
34, means for determining from which of
A means for designating which of the plurality of PCI buses 131 to 134 is to be performed irrespective of the physical address; a means for allocating the plurality of main storage connection ports 103 and 113 to a plurality of groups; Buses 102 and 112 and a plurality of PCI buses 131 to 13
4 can operate independently of each other.
02 so that a single multiprocessor system can be operated as a plurality of personal computers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing technology, and more particularly to a technology effective when applied to a bus memory controller in an information processing device such as a personal computer having a multiprocessor configuration.

[0002]

2. Description of the Related Art In recent years, personal computers (hereinafter, referred to as personal computers).
Tightly-coupled multiprocessor configurations that share main memory have become widespread in higher-order models of PCs (abbreviated as PCs) and PC server machines, and systems with a plurality of processor buses or a plurality of PCI buses have increased, resulting in reduced system cost and cost. Improving reliability has become an important issue. In a tightly coupled multiprocessor system, multiple C
If even one of the PUs fails, the whole system goes down. Therefore, in order to improve the reliability of the entire system, the entire system is multiplexed by a hot standby configuration or the like. Regarding the multiplexing of the entire system, it is common to install a plurality of systems themselves and use them as an active system and a standby system.

In addition to the hot standby configuration, in terms of system operation, for example, a system that can be configured with one PC server having a maximum of 8 CPUs is configured with two PC servers having a maximum of 4 CPUs, thereby distributing the risk against a failure. What you do is generally done.

[0004] A method of installing a plurality of systems themselves to make an active system and a standby system is described in, for example, Japanese Patent Publication No. 7-60399.
No., published in Japanese Unexamined Patent Publication No. For a PC having a configuration having a plurality of processor buses and a plurality of PCI buses, for example, "8-processor Xeon server machine Japanese manufacturer will take the lead" (Nikkei Electronics, 1998
September 21, pp. 47-54).

[0005]

In the prior art in which a plurality of the above systems are installed and used as an active system and a standby system, for example, in the case of a duplex system, the hardware costs including a housing, a power supply, etc. are all doubled. As a result, there is a technical problem that the cost of the entire system becomes very large. Therefore, a plurality of processor buses and a plurality of PCIs
In a higher-level model of a PC having a bus and a PC server machine, the plurality of processor buses and the plurality of PCI buses are divided into a plurality of groups, and a physical dividing function for operating each group independently of each other is provided. This system can be operated as a plurality of PCs to be used as an active system and a standby system, or a method of distributing risks to failures can be considered.

If this method is used, for example, a maximum of 8 CPUs
PC servers can be operated as two PC servers having a maximum of 4 CPUs. However, in a PC, it is necessary to provide a compatible PCI bus arranged at the same physical address in each group that operates independently. The logic of the conventional bus / memory controller does not take into account the physical division function including this point at all, and it is only possible to perform software processing such as division of the physical address area on the conventional bus / memory controller. There is a technical problem that the physical division function cannot be realized.

An object of the present invention is to provide a technology capable of operating an information processing device such as a personal computer having one multiprocessor configuration as a plurality of information processing devices that operate independently of each other. .

Another object of the present invention is to provide an information processing apparatus such as a personal computer having a single multi-processor configuration, while suppressing an increase in cost and providing a fault tolerance equivalent to multiplexing by a plurality of information processing apparatuses. It is to provide a technology that can be realized.

Another object of the present invention is to operate a high-order model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine as a plurality of PCs which operate independently of each other, thereby realizing risk distribution for failure. It is to provide the technology to do.

[0010] Another object of the present invention is to improve the reliability of a system equivalent to that of multiplexing while suppressing an increase in cost in a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine. It is an object of the present invention to provide a technique for improving the level, that is, the level at which a standby system is switched to an equivalent-sized standby system when a failure occurs in the active system.

[0011]

SUMMARY OF THE INVENTION The present invention relates to an information processing apparatus comprising a main memory, a plurality of processor buses, and a plurality of external input / output buses connected via a bus memory controller. A plurality of processor buses and a plurality of external input / output buses are divided into a plurality of groups, and a physical dividing function is provided for operating the respective groups independently of each other.

More specifically, as an example, in the present invention, a physical partitioning operation mode is provided as an internal register means in a bus memory controller of an upper model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine. For setting up a computer, and a plurality of compatible PCs
Means for setting the I bus space is provided. That is, when the physical division operation mode is set, the plurality of independently operating groups each use only the corresponding compatible PCI bus space setting means, and when the physical division operation mode is not set. In this case, only one of the plurality of compatible PCI bus spaces is used. Thus, a compatible PCI bus arranged at the same physical address can be provided in each of the groups that operate independently.

According to the present invention, a plurality of PCI buses are connected via a high-level I / O bus.
In the memory controller, D on the upper I / O bus
When the MA transfer is performed, the DMA transfer
Means for determining which of the plurality of PCI buses the PIO access is to be performed from when the PIO access is performed on the upper I / O bus; There is a means to specify the address regardless of the address. That is, the bus / memory controller
At the time of the DMA transfer, by determining from which of the plurality of PCI buses the DMA transfer is performed,
The process determines whether the MA transfer belongs to one of the plurality of groups that operate independently of each other, and performs processing.
At the time of O access, the PIO access is performed by designating the PCI bus of the group to which the PIO access belongs regardless of the physical address. As a result, the upper I / Os of the plurality of PCI buses are set.
In a PC configured to be connected via the O bus, the plurality of PCI buses, including those arranged at the same physical address, can be divided into the plurality of independently operating groups.

In the present invention, when the bus memory controller has a plurality of main storage connection ports, the plurality of main storage connection ports are divided into a plurality of groups when the group is divided by the physical division function. When the bus / memory controller has only a single main memory connection port or when the plurality of groups share the main memory connection port, Means for dividing the main memory into a plurality of groups according to the range of physical address values by register setting. Thereby, the main memory can be divided into the plurality of groups that operate independently of each other.

As described above, according to the present invention, in a high-order model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine, the plurality of processor buses and the plurality of PCI buses are divided into a plurality of groups. ,
By providing a physical division function for operating each group independently of each other, a single system can be operated as a plurality of PCs. In addition, by using the plurality of PCs as an active system and a standby system, a hot standby configuration can be achieved.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 and FIG. 2 show a plurality of processor buses and a plurality of PCI buses when physical division is performed in a higher-level model of a PC, a PC server, or the like, which is an embodiment of the information processing apparatus of the present invention. FIG. 3 is a block diagram illustrating an example of a hardware system configuration having the same.

FIG. 3 is a register map showing an example of an internal register configuration of a bus memory controller mounted on the information processing apparatus according to the embodiment. FIG. 4 is a bus memory mounted on the information processing apparatus according to the embodiment. FIG. 3 is a block diagram illustrating an example of an internal hardware configuration of a controller.

FIG. 5 is a block diagram showing an example of a connection configuration between the bus / memory controller of the present embodiment, a higher-level I / O bus and a plurality of PCI buses having a hierarchical structure, and FIG. 13 is a flowchart illustrating an example of a start-up operation procedure of a physical division configuration by the information processing device.

FIGS. 7 and 8 are block diagrams showing an example of a hardware system configuration of an upper model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine according to the present invention.

First, referring to FIGS. 1 and 2 and FIGS. 7 and 8, an explanation will be given on the implementation of the physical division function in the upper model of the PC and the PC server machine of the present embodiment.

FIG. 7 shows a multiprocessor P having a plurality of processor buses and a plurality of PCI buses according to the reference technology.
FIG. 4 is a block diagram illustrating a first hardware configuration example of C. In FIG. 7, 101 and 111 indicate a plurality of CPs.
U, 102 and 112 have two processor buses, 1
03 and 113 are two main memory connection ports, 104
And 114 are main memory, 110 is one or more LS
I bus memory controller, 12
0 is the upper I which is a path for accessing a plurality of PCI buses.
I / O buses 121 to 124 are bus converters (BC) for connecting the first to fourth PCI buses to the upper I / O bus 120, respectively, and 131 to 134 are first to fourth PCI buses.
A bus 130 is connected to a compatible PCI bus and is generally referred to as legacy logic (LL).
/ O group.

In FIG. 7, the bus / memory controller 11
0 indicates two processor buses 102 and 112,
Main storage connection ports 103 and 113 of the system,
Upper I / O bus 12 serving as a path for accessing the CI bus
Connected to 0. For the two processor buses 102 and 112, a bus / memory controller 110
Performs cache coherency matching control, and constitutes a single tightly-coupled multiprocessor system as a whole. With respect to the two main memory connection ports 103 and 113, the bus / memory controller 110 performs interleave control to form a single memory address space as a whole. The first to fourth PCI buses 131 to 134 connected via the upper I / O bus 120
Are assigned different physical addresses, and the method of assigning the physical addresses is determined by the PCI bus specifications. Among these, the first PCI bus 131 is a compatible PCI bus, and the LL 130 is connected. The physical address of the compatible PCI bus 131 has a fixed value in order to maintain software compatibility of the PC. Next, a case will be described in which the bus / memory controller according to the present invention is applied to the PC in FIG. 7 to perform the physical division function.

FIG. 1 is a block diagram showing an example of a hardware configuration when a physical division function is implemented by applying the bus / memory controller according to the present embodiment to the PC in FIG. In FIG. 1, reference numerals 201 and 202 denote the first (N) divided by the physical division function according to the present embodiment.
mode1) and the second (Node2) group, 21
Reference numeral 0 denotes a bus / memory controller which is constituted by one or more LSIs and has a physical division function as described later. Reference numeral 220 denotes an upper I / O bus to which a function corresponding to the physical division function of the present embodiment is added. , 231 and 232 are legacy logic (LL) connected to the first and second groups, respectively. Components denoted by the same reference numerals as those in FIG. 7 are the same components as those in FIG.

In FIG. 1, the bus / memory controller 21
0 indicates two processor buses 102 and 112,
The system main storage connection ports 103 and 113, the first to fourth PCI buses 131 to 134 are connected to the processor bus 102, the main storage connection port 103, the Node 1 including the two PCI buses 131 and 132, and the processor bus 112, Main memory connection port 113, two-system PCI
Node2 composed of buses 133 and 134 is divided into two groups. Each group has an independent P
Operate as C.

Therefore, the bus / memory controller 210
Does not perform interleave control on the two main memory connection ports 103 and 113, but controls them as two independent memory address spaces.
Memory accesses from the system PCI buses 131 and 132 are made to the main memory 104, and memory accesses from the processor bus 112 and the two system PCI buses 133 and 134 are made to the main memory 114. The contents of this function will be described later.

Also, the two groups have two PCI buses each.
Each node has a PCI bus 1
Reference numeral 31 denotes a compatible PCI bus, and in Node 2, the PCI bus 133 is a compatible PCI bus. Therefore, the PCI bus 131 and the PCI bus 133 are connected to the LL 231 and the LL 232, respectively, and are assigned the same physical address.

In the present embodiment, means for determining which of a plurality of PCI buses the DMA transfer is to be performed when the DMA transfer is performed on the upper I / O bus 220 by the bus / memory controller 210. In addition, when a PIO access is performed on the upper I / O bus 220, means for designating which of the plurality of PCI buses the PIO access is performed irrespective of the physical address is provided. As a result, the bus / memory controller 210
At the time of MA transfer, the DMA transfer is determined by determining from which of the plurality of PCI buses the DMA transfer is being performed.
Processing is performed by determining whether the transfer belongs to Node1 or Node2, and at the time of PIO access, the PIO access is performed by specifying the PCI bus of the group to which the PIO access belongs, regardless of the physical address. The contents of this function will be described later.

FIG. 8 shows a multiprocessor P having a plurality of processor buses and a plurality of PCI buses according to the reference technology.
FIG. 13 is a block diagram illustrating a second hardware configuration example of C. 8, reference numerals 301 and 311 denote a plurality of CPs.
U, 302 and 312 are multiple processor buses, 32
0 is a main memory, 321 is a main memory connection port, 310 is a bus / memory controller constituted by one or more LSIs, 304 and 314 are a plurality of I / O connection ports, and 303 and 304 are I / O connection ports 2 each
A bus converter (BC) for connecting a system PCI bus,
331 to 334 are first to fourth PCI buses, 330
Is legacy logic (LL).

The difference between FIG. 8 and FIG. 7 is that in FIG. 8, the bus memory controller 310 has a single main memory connection port 3
21 is connected to the I / O connection port 304 and the I / O connection port 314 of two systems, and the other configuration is the same as that of FIG. Next, a case will be described in which the bus / memory controller according to the present embodiment is applied to the PC in FIG. 8 to perform the physical division function.

FIG. 2 is a block diagram showing an example of a hardware configuration in the case where the bus / memory controller according to the present embodiment is applied to the PC in FIG. 8 to perform a physical division function. In FIG. 2, reference numerals 401 and 402 denote the first (No.) divided by the physical division function in the present embodiment.
de1) and second (Node2) groups, 410
Is a bus / memory controller according to the present embodiment constituted by one or a plurality of LSIs; 420 is a main memory which is divided into two groups by the physical division function according to the present embodiment according to a range of physical address values; And 4
32 is a legacy logic (LL) connected to the first and second groups, respectively. Components denoted by the same reference numerals as those in FIG. 8 are the same components as those in FIG.

In FIG. 2, the bus / memory controller 41
0 indicates two processor buses 102 and 112, a main memory connection port 321, and two I / O connection ports 30.
Nos. 4 and 314 are connected to a Nod comprising a processor bus 302, a main memory connection port 321, and an I / O connection port 304.
e1, processor bus 312, main memory connection port 32
1, Node 2 composed of I / O connection port 314, 2
Divided into groups. Main memory connection port 321
Is shared by two groups, and each group operates as an independent PC.

Since the main memory connection port 321 is shared by the two groups, in this embodiment, the bus memory controller 410 divides the main memory 420 into a plurality of groups according to the range of physical address values by register setting. Is provided. As a result, the main memory 420 is divided into a plurality of groups that operate independently of each other. The bus and memory controller 410 controls each processor bus and I / O
The main memory access from the O connection port is internally converted according to a certain rule of the physical address, and the memory access from the processor bus 302 and the I / O connection port 304 is performed with respect to the physical address range of Node 1 of the main memory 420. Memory access from the processor bus 312 and the I / O connection port 314
This is performed for the physical address range of de2. The contents of this function will be described later.

Also, the two groups have two PCI buses each.
Each node has one system, but the Node 1 has a PCI bus 3
Reference numeral 31 denotes a compatible PCI bus, and in Node 2, the PCI bus 333 is a compatible PCI bus. Therefore, LL431 and LL432 are connected to the PCI bus 331 and the PCI bus 333, respectively, and the same physical address is allocated. The bus / memory controller 410 receives the PIO from the processor bus 102
Access is made to the I / O connection port 304, and PIO access from the processor bus 312 is made to the I / O connection port 314.

As described above, according to the present embodiment, the physical division function of the multiprocessor PC having a plurality of processor buses and a plurality of PCI buses can be implemented. Next, the contents of each of the above functions necessary for implementing the physical division function will be described with reference to FIGS.

FIG. 3 shows a bus according to the embodiment of FIG.
4 is a register map illustrating an example of an internal register configuration of a memory controller 410. In the embodiment of FIG. 2, as an example, three types of internal registers are added to the internal register configuration of the bus / memory controller according to the reference technology of FIGS.

In FIG. 3, the internal register configuration of the bus / memory controller according to the reference technology is shown by a common register group 50.
1. Compatible PCI bus space setting register 511,
The main storage attribute setting register 521 is shown as being classified into three types. Among them, 511 is a register group for setting the attribute of the physical address space of the compatible PCI bus.
Reference numeral 521 denotes a register group for setting the configuration / attribute of the memory address space, both of which are general in a PC bus / memory controller. The common register group 501 is a general term for internal registers other than the compatible PCI bus space setting register 511 and the main memory attribute setting register 521.

In this embodiment, as means for realizing the physical division function, the above-mentioned internal registers include a physical division mode setting register 502, a second compatible PCI bus space setting register 512, and a second main storage attribute. Three types of internal registers of the setting register 522 are added.

The physical division mode setting register 502 is a register for setting whether or not to operate by performing the physical division function according to the present embodiment.
a and a mode setting notification bit 502b. The mode defining bit 502a is a bit set by an external pin input of the bus memory controller 410 at the time of power-on, and when the hardware configuration of the system is configured to perform the physical division function, that is, when a plurality of LLs are This bit is set when connected.
This mode defining bit 502a is referred to in a system start-up operation described later. Mode setting notification bit 502
b is a flag bit set by the CPU, and is a flag that is set when the internal register setting for performing the physical division function and operating is completed. When this flag is set, the bus / memory controller 4
10 operates by implementing a physical partitioning function.

The second compatible PCI bus space setting register 512 is a register group similar to 511, and when operating by executing the physical division function, 511 is Nod.
e1 (group 401 in FIG. 2), 512 is N
mode2 (group 402 in FIG. 2). This allows each group to have a compatible PCI bus. If the physical division function is not performed, 512 is not used.

The second main memory attribute setting register 522 is
A register group similar to 521 operates when the physical division function is performed, and 521 is applied to Node1 (group 401 in FIG. 2) and 522 is applied to Node2 (group 402 in FIG. 2). In this case, since the main storage connection port 321 is shared by two groups, in this embodiment, by setting this register, the main storage 420 is divided into a plurality of groups according to the range of the physical address value. If you do not implement the physical partition function,
522 is not used.

FIG. 4 shows a bus according to the embodiment of FIG.
FIG. 3 is a block diagram illustrating an example of an internal hardware configuration of a memory controller 410. In FIG. 4, 602 and 6
12 is an interface control logic connected to the processor buses 302 and 312, 621 is an interface control logic connected to the main memory connection port 321, 602 and 612 are interface control logics connected to the I / O connection ports 304 and 314, 631 Is a main sequencer, and 632 is an address / data buffer. Those denoted by the same reference numerals as those in FIG. 2 are the same components as those in FIG. The internal register group shown in FIG. 3 is provided in the main sequencer 631.

In FIG. 4, a total of five interface control logics 602, 612, 621, 604, 614
Address data is input / output to / from the address / data buffer 632 for each connected interface. The address / data buffer 632 is composed of a so-called 10-port memory that can perform reading / writing independently from five directions. The main sequencer 631 has five interface control logics 602, 612, 621, 6
04, 614 and the address / data buffer 632, and controls the operation as the bus memory controller 410.

The main sequencer 631 has a mode setting notification bit 5 of the physical division mode setting register 502 shown in FIG.
When 02b is not set, the operation is the same as that of the reference technology of FIG. 8, and when the mode setting notification bit 502b is set, the operation is performed by executing the physical division function. When operating with a physical partitioning function, the PIO access from interface control logic 602 is conveyed to interface control logic 604 and interface control logic 612.
Access from the interface control logic 614
Control to transmit to.

In the present embodiment, when the four interface control logics 602, 612, 604, and 614 operate by implementing the physical division function, the main memory access from each processor bus and I / O connection port is performed. about,
The physical address is converted according to a certain rule, the memory access from the processor bus 302 and the I / O connection port 304 is performed to the physical address range of Node 1 of the main memory 420, and the processor bus 312 and the I / O connection port 314 Memory access from the main memory 420
This is performed for the physical address range of de2.

This conversion is performed, for example, by increasing or decreasing a fixed offset value in the address value when reading / writing the address / data buffer 632. For example, Node1 and Node2 both use a 1 gigabyte main storage space from physical address (0) to (1 giga-1), and main storage 420 has a physical address (1 gigabyte) to (3 giga-1). ) Consider the case where there is 2 gigabytes to the address. In this case, the offset value is set to 1 giga for Node 1, the offset is set to 2 giga for Node 2, and four interface control logics 60 are used.
2, 612, 604, and 614, the address value is added to the address value when writing the address / data buffer 632, and the read value is subtracted from the address value for each group. . The offset value is stored in the main memory attribute setting register 5 in FIG.
The main sequencer 631 calculates the four interface control logics 602, 612, 604, and 614 from the setting values of the first and second main storage attribute setting registers 522.
To communicate. As a result, the processor bus 302 and the I / O
Memory access from the O connection port 304 is
0 may be performed on the physical address range of Node1 and the memory access from the processor bus 312 and the I / O connection port 314 may be performed on the physical address range of Node2 of the main memory 420.

The internal configuration of the bus / memory controller 210 of FIG. 1 can be the same as that of FIG.
However, in the bus memory controller 210, there are two interface control logics corresponding to the plurality of main memory connection ports 103 and 113 for connection to the main memories 104 and 114, and for connection to I / O. Top I
In this configuration, there is only one interface control logic connected to the / O bus 220.

Also in this case, when the mode setting notification bit 502b of the physical division mode setting register 502 of FIG. 3 is not set, the main sequencer 631 operates in the same manner as the reference technique of FIG.
Is set, the operation is performed by implementing the physical division function. When operating by implementing the physical division function, two main storage connection ports 103 and 113 are assigned to each group one by one, and each operates as being connected to an independent main storage space. However, a special control function is required for the I / O connection because the interface control logic is single. Hereinafter, this control function will be described.

FIG. 5 shows a bus / memory controller 210 and an upper I / O bus according to this embodiment of the PC shown in FIG. 1 having a configuration in which a plurality of PCI buses 131 to 134 are connected via a common upper I / O bus 220. FIG. 2 is a block diagram showing a connection configuration example of 220.

In FIG. 5, reference numeral 701 denotes the upper I / O bus 2
20, an address / data bus 702, a control bus 702 of the upper I / O bus 220, and 703 and 704, groups 201 (Node 1) and 202 (Node
PIO access signals corresponding to each of 2), bus switch circuits 711 to 714 corresponding to four BCs 121 to 124, and 721 to 724 upper I / Os corresponding to four BCs 121 to 124, respectively. This is an arbitration signal of the O bus 220. Components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. The connection of the bus / memory controller 210 to components other than the upper I / O bus 220 is omitted.

In FIG. 5, the two groups each have two PCI buses.
CI bus 131 is a compatible PCI bus, and No
In de2, the PCI bus 133 is compatible PC
It is an I bus. Therefore, the LLs 231 and 232 are connected to the PCI bus 131 and the PCI bus 133, respectively, and the same physical address is allocated. Therefore, in the present invention, when the DMA transfer is performed on the upper I / O bus 220, the bus memory controller 210 determines which of the plurality of PCI buses the DMA transfer is performed from, and determines the DMA transfer. Is determined by which group it belongs to, and processing is performed.
When the IO access is performed, it is necessary to specify which of the plurality of PCI buses the PIO access is performed irrespective of the physical address, and transmit the PIO access to the PCI bus of the group to which the PIO access belongs.

In FIG. 5, DM on the upper I / O bus 220
In order to determine from which of the plurality of PCI buses 131 to 134 the DMA transfer is performed when the A transfer is performed, the arbiter of the upper I / O bus 220 is changed to the upper I / O bus of the bus memory controller 210. The high-level I / O bus 220 corresponding to four BCs 121 to 124 is incorporated in the interface control logic connected to the
Arbitration signals 721 to 724 are connected to the bus / memory controller 210. With this, when the DMA transfer is performed on the upper I / O bus 220, which of the four BCs 121 to 124 determines which DMA transfer is performed from which of the plurality of PCI buses 131 to 134 is higher. The determination can be made depending on whether the I / O bus 220 is used. The arbiter of the upper I / O bus 220 is assigned to the bus / memory controller 210.
It is obvious that the arbitration signals 721 to 724 of the upper I / O bus 220 may be connected to the bus / memory controller 210 even when the bus memory controller 210 is not incorporated.

In FIG. 5, when a PIO access is performed on the upper I / O bus 220, which of the plurality of PCI buses 131 to 134 is specified regardless of the physical address. Therefore, upper I / O
The control bus 702 of the bus 220 is changed from 121 to 1
24 are connected to the four BCs via the bus switch circuits 711 to 714, respectively, and from the interface control logic connected to the upper I / O bus 220 of the bus memory controller 210, Node1 and N
PIO access signals 703 and 704 corresponding to the PIO access from mode2 are output. Of the bus switch circuits 711 to 714 corresponding to the four BCs, the bus switch circuits 711 and 71 corresponding to the BCs 121 and 122 belonging to Node 1
2 is a PIO corresponding to PIO access from Node1
Bus switch circuit 71 that is connected and controlled by access signal 703 and corresponds to BCs 123 and 124 belonging to Node 2
3 and the bus switch circuit 714
The connection is controlled by a PIO access signal 704 corresponding to the IO access.

That is, when a PIO access to another group is performed, the control bus 702 is disconnected, and the PIO access is automatically ignored. Thus, when the PIO access is performed on the upper I / O bus 220, the PIO access is specified by irrespective of the physical address to which of the plurality of PCI buses 131 to 134 is performed. To the PCI bus of the group to which it belongs.

As described above, in the present embodiment, a plurality of PCs
One upper I / O bus 2 for I buses 131 to 134
In the case of a PC configured to connect to the bus memory controller 210 via the bus 20, that is, the connection with the I / O of the bus memory controller 210 is performed by the upper I / O bus 22.
Even in the case of a configuration having only one interface control logic connected to 0, the physical division function can be implemented.

Next, a description will be given of a start-up operation procedure when the physical division function is implemented according to the present embodiment.
FIG. 6 is a flowchart showing an example of a start-up operation procedure of the physical division configuration according to the present embodiment.

In FIG. 6, power on (step 80)
1) At times, the physical division mode setting register 502 of FIG.
Has been reset. That is, the physical division function is OFF.
After power-on (step 801), in the PC according to the present embodiment shown in FIG. 1 or FIG. 2, a boot processor is selected by hardware (step 802) in the same manner as in the reference technique, and only one CPU operates in the BIOS. Start-up operation starts.

In the PC according to the present embodiment, the BIO
During the start-up operation in S, the mode defining bit 502a of the physical division mode setting register 502 in FIG. 3 is read to confirm the system operation mode (Step 803), and it is determined whether or not to execute the physical division function (Step 803). Step 80
Perform 4). If the physical partitioning operation is not performed, a single system-compatible startup process (step 811) similar to that of the reference technology is performed, and the OS is booted (step 812).

When implementing the physical division function, the PC according to the present embodiment reads the mode setting notification bit 502b of the physical division mode setting register 502 in FIG. 3 (step 805), and executes the physical division function. It is determined whether or not the internal register setting for performing the operation has been completed (step 806). If the internal register setting has not been completed, the internal register setting (step 807) is automatically performed, or the mode shifts to a general user setting mode in the reference technology of FIGS. Make the user set the internal registers. After the completion of the internal register setting, the mode setting notification bit 5
02b, the system restart processing (step 8
08). At the time of this system restart, the settings of the internal register setting and the mode setting notification bit 502b are not reset. Therefore, after the restart, the setting of the internal registers for performing the physical division function and operating is completed.

When the internal register setting for operating by performing the physical division function has been completed, the PC according to the present embodiment is in a state where a plurality of groups can operate independently of each other. The boot process (step 821) corresponding to the system is performed, and the OS is independently booted (step 822) in each group.

As described above, according to the present embodiment, in a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine, a plurality of processor buses and a plurality of Of the present invention can be divided into a plurality of groups, and a physical division function for operating each group independently of each other is provided, so that a single multiprocessor system can be operated as a plurality of PCs physically independent from each other. it can. Further, it is apparent that a hot standby configuration can be achieved by using a plurality of PCs realized by the physical division function of the present embodiment as an active system and a standby system.

Further, for example, in the case of OS revision,
Using the physical division function of the bus / memory controller 210, 410, the multiprocessor system is started as a plurality of independent plural PCs, and on the one hand, the old version of the OS used so far is started, and on the other hand, the new version is started. There is also an advantage that the operation verification of the new version of the OS can be realized without stopping the entire system by starting up the OS.

As described above, according to the information processing apparatus of the present embodiment, an upper model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server are operated as a plurality of PCs which operate independently of each other. In addition, it is possible to diversify risks for failures.

Further, in a high-order PC model and a PC server machine having a plurality of processor buses and a plurality of PCI buses, the system reliability can be reduced to a level equivalent to that of multiplexing, that is, an active system, while suppressing an increase in cost. The level can be improved to a level at which a standby system of the same scale is switched when a failure occurs.

The features of the present invention other than those described in the claims are listed below.

<1> Bus of personal computer
A memory controller having a function of connecting to a plurality of processor buses and connecting to a main memory and a plurality of PCI buses, wherein the plurality of processor buses and the plurality of PCIs are connected.
A function (physical division function) of dividing the bus into a plurality of groups and operating the groups independently of each other, wherein the group division configuration by the physical division function is set to a register in the bus / memory controller A bus memory controller comprising a register for defining a plurality of compatible PCI bus spaces as a register for setting the division configuration of the group.

<2> The bus / memory controller according to item <1>, wherein the bus / memory controller has a function of connecting the plurality of PCI buses via an upper I / O bus. When a direct memory access (DMA) transfer is performed, the DMA transfer
A bus / memory controller having a function of determining which one of the buses is used.

<3> The bus / memory controller according to item <1>, wherein the bus / memory controller has a function of connecting the plurality of PCI buses via an upper I / O bus. When an access (PIO access) is performed from any processor bus to any PCI bus, the device specifies which of the plurality of PCI buses the PIO access is performed irrespective of the physical address. A bus / memory controller having a function of performing

<4> The bus / memory controller according to item <1>, wherein the bus / memory controller has a plurality of main storage connection ports, and when the group is divided by the physical division function, the plurality of main storage connection ports are set. A bus / memory controller having a function of dividing into a plurality of groups.

<5> The bus / memory controller according to items <1> to <4>, wherein the main memory is divided into a plurality of groups according to a range of physical address values when the group is divided by the physical division function. A bus / memory controller having a function of performing

<6> A personal computer having the bus / memory controller according to item <1>.

The invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is.

[0073]

According to the information processing apparatus of the present invention, an information processing apparatus such as a personal computer having a multiprocessor configuration can be operated as a plurality of information processing apparatuses that operate independently of each other. The effect is obtained.

Further, in an information processing device such as a personal computer having a single multiprocessor configuration, it is possible to realize a fault tolerance equivalent to multiplexing by a plurality of information processing devices while suppressing an increase in cost. The effect is obtained.

Further, it is possible to operate a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine as a plurality of PCs that operate independently of each other, thereby realizing risk distribution for failure. The effect is obtained.

Further, in a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine, the reliability of the system can be reduced to a level equivalent to that of the multiplexing, that is, an active system, while suppressing an increase in cost. An effect is obtained that the level can be improved to a level at which a standby system is switched to an equivalent-scale system when a failure occurs.

[Brief description of the drawings]

FIG. 1 shows an information processing apparatus according to an embodiment of the present invention;
FIG. 2 is a block diagram illustrating a first hardware system configuration example when applied to a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses, and a PC server machine.

FIG. 2 shows an information processing apparatus according to an embodiment of the present invention;
FIG. 11 is a block diagram illustrating a second hardware system configuration example when applied to a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses, and a PC server machine.

FIG. 3 is a register map illustrating an example of an internal register configuration of a bus / memory controller included in the information processing apparatus according to the embodiment of the present invention;

FIG. 4 is a block diagram illustrating an example of an internal hardware configuration of a bus / memory controller included in the information processing apparatus according to the embodiment of the present invention;

FIG. 5 is a block diagram illustrating an example of an internal hardware configuration of a bus / memory controller included in the information processing apparatus according to the embodiment of the present invention;

FIG. 6 is a flowchart showing an example of a start-up operation procedure of a physical division configuration in the information processing apparatus according to one embodiment of the present invention;

FIG. 7 is a block diagram illustrating an example of a first hardware system configuration of an upper model of a PC having a plurality of processor buses and a plurality of PCI buses and a PC server machine according to a reference technique of the present invention.

FIG. 8 is a block diagram illustrating a second example of a hardware system configuration of a higher-level model of a PC having a plurality of processor buses and a plurality of PCI buses, and a PC server machine according to the present invention;

[Explanation of symbols]

101, 111, 301, 311 ... CPU, 102, 1
12, 302, 312: processor bus, 103, 11
3, 321 ... main memory connection port, 104, 114, 32
0, 420 ... main memory, 110, 210, 310, 410
... bus memory controller, 120, 220 ... upper I
/ O bus, 121, 122, 123, 124, 303,
313 bus converter (BC), 131, 132, 1
33,134,331,332,333,334 ... PC
I bus, 130, 231, 232, 330, 431, 4
32 ... Legacy logic (LL), 201, 202, 40
1, 402: groups divided by the physical division function, 304, 314: I / O connection ports, 501: common register group, 502: physical division mode setting register (first register), 502a: mode defining bits, 502
b: Mode setting notification bit, 511: Compatible PC
I bus space setting register, 512... Second compatible PCI bus space setting register (second register), 52
1: Main storage attribute setting register 522: Second main storage attribute setting register (third register), 602, 612
621, 604, 614... Interface control logic, 6
31: Main sequencer; 632: Address / data buffer; 701: Address / data bus of upper I / O bus; 702: Control bus of upper I / O bus;
3,704... PIO access signals, 711, 712, 7
13, 714 bus switch circuits, 721, 722, 7
23,724... Arbitration signals of the upper I / O bus.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yukihiro Seki 1-Horiyamashita, Hadano-shi, Kanagawa F-term in Enterprise Server Division, Hitachi Ltd. 5B014 EA05 GD05 HA11 HB26 HC01 HC15 5B034 BB02 CC01 5B045 BB12 DD01 JJ22 JJ24 JJ44

Claims (3)

[Claims] 1. An information processing apparatus having a configuration in which a main memory, a plurality of processor buses, and a plurality of external input / output buses are connected via a bus memory controller, wherein the bus memory controller comprises a plurality of the processor buses. An information processing apparatus comprising: a plurality of external input / output buses; a plurality of external input / output buses; a plurality of groups; and a physical division function of operating the groups independently of each other. 2. The information processing device according to claim 1, wherein the external input / output bus includes an upper I / O bus connected to the bus memory controller and a plurality of upper I / O buses connected to the upper I / O bus. A first register for designating whether or not to perform division into groups by the physical division function; and a bus register for the external input / output bus. A second register defining a physical address space; and a third register defining a memory address space of the main memory, wherein a direct memory access (D
MA) When a transfer is performed, it is determined from which of the plurality of PCI buses the DMA transfer is performed, and from the processor bus on the upper I / O bus, An information processing apparatus, wherein when an access to a PCI bus (PIO access) is performed, which of the plurality of PCI buses is to be accessed is specified regardless of a physical address. 3. The information processing apparatus according to claim 1, wherein the bus memory controller has a single main storage connection port for the main storage, and is divided into the groups by the physical division function. An information processing apparatus, wherein a storage area of the main storage is sometimes assigned to a plurality of groups according to a range of physical address values.