JP2001028515A - Crystal oscillator - Google Patents

Abstract

(57) [Summary] [Purpose] To suppress self-excited oscillation when the buffer amplifier rises,
Provide a crystal oscillator that obtains a stable oscillation frequency immediately after startup. In a crystal oscillator in which a buffer amplifier is connected to an oscillation circuit and both are driven by the same power supply, the rise of the buffer amplifier is delayed later than the oscillation circuit. Further, the operating voltage at the time of rising of the buffer amplifier is shifted from the reference value, and the output at the time of rising is set to 0 or 1 level. Further, a delay circuit is provided between the buffer amplifier and the power supply.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal oscillator as an industrial technical field, and more particularly to a crystal oscillator which prevents malfunction of a device due to self-excited oscillation (parasitic oscillation) of a buffer amplifier at the time of rising.

[0002]

2. Description of the Related Art Crystal oscillators are widely used as various frequency and time reference sources in various electronic devices including communication devices. For example, in a mobile phone, it is used as a local oscillator for obtaining an intermediate frequency. In recent years, it is used not only to obtain an intermediate frequency but also as a synchronization signal.

FIG. 5 is a circuit diagram of a crystal oscillator for explaining a conventional example. The crystal oscillator includes an oscillation circuit 1 and a buffer amplifier 2. The oscillating circuit 1 is a Colpitts oscillating circuit 1 (not shown) having the quartz oscillator 3 as an L component. The buffer amplifier 2 is a two-stage coupling, both of which are inverter-type complementary-connected MOS-FETs 4 (CMOS
(Ab). Then, a feedback resistor 5 is provided in the first stage to set an operation voltage. In addition, a coupling capacitor 6 is provided between the oscillation circuit 1 and the buffer amplifier 2 so as to be connected at a high frequency. These are the quartz oscillator 3
Integrated on a silicon substrate (not shown) except for
C). Reference numeral 16 denotes a coupling capacitor for coupling to an external circuit.

[0004]

[Problems to be Solved by the Invention]
However, in the crystal oscillator having the above configuration, the oscillation circuit 1
Since the crystal oscillator 3 is used, the rise is relatively slow (about 1.5 to 2.2 msec) until the oscillation frequency (steady output) is reached after the power is turned on. Therefore, there is a problem that the buffer amplifier 2 operates first when the power is turned on, causing self-pulsation. In this case, there is a possibility that other circuits such as a synchronous circuit may be adversely affected.

When the oscillation output exceeds the reference level (about 10% or more of the normal output), the operation of the buffer amplifier 2 is stabilized and self-excited oscillation does not occur.

(Object of the Invention) It is an object of the present invention to provide a crystal oscillator which suppresses self-excited oscillation at the time of rising of a buffer amplifier and obtains a stable oscillation frequency immediately after starting.

[0007]

SUMMARY OF THE INVENTION The present invention provides a buffer amplifier
The basic solution is to make the rise of the delay time longer than that of the oscillation circuit 1 (claim 1).

More specifically, the operating voltage at the time of rising of the buffer amplifier 2 is shifted from the reference value, and the output is set to 0 or 1 level (power supply voltage).
Alternatively, a configuration is provided in which a delay circuit is provided between the buffer amplifier 2 and the power supply.

[0009]

According to the present invention, the operation at the time of rising of the buffer amplifier 2 is delayed. Therefore, during this time, the oscillation output becomes higher than the reference level at which the buffer amplifier 2 operates normally. Therefore, at the time of the delay operation of the buffer amplifier 2, an oscillation output higher than the reference level is input, so that self-excited oscillation at the time of rising and thereafter is suppressed. Hereinafter, an embodiment of the present invention will be described.

[0010]

1 and 2 are views for explaining an embodiment of the present invention. FIG. 1 is a circuit diagram of a crystal oscillator and FIG. 2 is a time chart. The same parts as those in the prior art are denoted by the same reference numerals, and description thereof will be simplified or omitted. As described above, the crystal oscillator is a two-stage coupled CMOS inverter 4 (a) that is connected to the Colpitts oscillation circuit 1 having the crystal oscillator 3 as an L component at a high frequency by a coupling capacitor 6.
b) is provided. In addition,
These are integrated.

In this embodiment, a start delay circuit 7 is provided at the input stage of the buffer amplifier 2. Startup delay circuit 7
Comprises a pulse generation circuit 8 and a voltage drop circuit 9. The pulse generation circuit 8 connects a constant current source 10 and a grounded capacitor 11 connected in series to a power supply Vcc. Constant current source 1
The gate of the first FET 12 whose drain and source are connected between the power supply Vcc and the ground is connected to the midpoint between 0 and the capacitor 11. Then, a load resistor 13 is provided on the drain side.

The voltage drop circuit 9 includes a second FET having a drain and a source connected between the input stage of the buffer amplifier 2 and the ground.
The output (drain) of the pulse generating circuit 8 is connected to the gate 14. Then, a high-frequency blocking resistor 15 is provided on the drain side of the second FET 14.

In such a circuit, when the power supply Vcc is turned on, FIG.
1 is charged first. When the potential of the capacitor 11 exceeds the forward voltage drop (threshold voltage) of the first FET 12, the gate of the first FET 12 opens and a drain current is generated. Therefore, a power supply voltage (suppression pulse P) is generated at the drain output only during the charging time of the capacitor 11 (FIG. 2B).

The second FET 14 of the voltage drop circuit 9
When the suppression pulse P is applied to the gate of the second FET 1
4 operates to generate a drain current from the input stage of the buffer amplifier 2. Therefore, the input stage (FET) of the buffer amplifier 2
, The operating voltage shifts from the reference value (usually 1/2 of the power supply voltage) Vs to Vs ′ below. (FIG. 3) That is, the operating point shifts from the linear region (inclined amplification region) to the non-amplification region (flat portion, one level, HIGH level). FIG. 3 is an input (Vi) -output (Vo) characteristic diagram of the CMOS inverter.

[0015] From this, the suppression pulse P after power-on
(Approximately 1 msec), the buffer amplifier 2 does not operate (has no amplification function). Therefore, self-excited oscillation caused by noise or the like after power-on does not occur. On the other hand, the oscillation circuit 1 operates upon turning on the power, and the oscillation output becomes higher than the reference level during the application of the suppression pulse P to the buffer amplifier 2 (FIG. 2C). The reference level is the buffer amplifier 2
Is set to, for example, 10% or more of the normal time when the device operates normally.

After the suppression pulse P has disappeared, a normal operating voltage is applied to the buffer amplifier 2. Then, the oscillation output (frequency) that has reached the reference level or higher is input to the buffer amplifier 2, and is amplified (FIG. 2 (d)).
Note that the self-excited oscillation does not occur in the buffer amplifier 2 due to the input of the oscillation output that has reached the stable region. In addition, high frequency blocking resistance 1
5, the oscillation circuit 1 and the voltage drop circuit 9 are cut off at a high frequency, so that the level of the oscillation output is prevented from lowering.

From the above, when the power is turned on, there is no high-frequency output from the buffer amplifier 2 due to the start delay circuit 7 (suppression pulse P), and a stable oscillation amplification output can be obtained along with the disappearance of the suppression pulse P. it can. Therefore, during the application of the suppression pulse P, there is no output due to the self-excited oscillation of the buffer amplifier 2, so that the influence on other circuits such as a synchronous circuit is prevented. Then, by delaying the startup, a stable oscillation output can be obtained from the beginning of the delay.

[0018]

[Others] In the above embodiment, the operating voltage of the buffer amplifier 2 (4a) is shifted from the reference value Vs to Vs' below and set to one level (HIGH level) by the suppression pulse P. Conversely, the same applies when the operating voltage is shifted upward to Vs '' and set to the 0 level (LOW level).

In this case, for example, as shown in FIG.
The drive delay circuit 7 includes the above-described pulse generator 8 and the voltage raising circuit 19. The voltage raising circuit 19 is connected to the third FE
A switching operation is performed by the suppression pulse P from the pulse generator 8, and the operating voltage of the buffer amplifier 2 is set to Vs '' (0 level) higher than the reference value Vs. Reference numeral 20 denotes a load resistance.

The drive delay circuit 7 includes a pulse generation circuit 8
And the voltage dropping circuit 9 or the voltage rising circuit 19, but the present invention is not limited to this. In other words, it is sufficient that the operating voltage of the buffer amplifier 2 deviates from the reference value at the time of startup and the output is 1 or 0.

Alternatively, for example, a delay circuit may be provided between the power supply and the buffer amplifier 2 to shift the operation time of the buffer amplifier 2 after the power is turned on. Further, the buffer amplifier 2 is not limited to the CMOS inverter, but may be an amplifier such as a MOSFET or a bipolar transistor.

In short, the purpose of the present invention is to interrupt the operation of the buffer amplifier to prevent self-excited oscillation until the oscillation output after the power is turned on reaches the stable region. Belongs to the technical scope of the present invention, including any appropriate modifications.

[0023]

According to the present invention, since the buffer amplifier is driven with a delay compared to the oscillation circuit, self-sustained pulsation when the power of the buffer amplifier is turned on can be suppressed, and a crystal oscillator which can obtain a stable oscillation frequency immediately after starting can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a crystal oscillator illustrating an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation and effect of one embodiment of the present invention.

FIG. 3 is a CMO illustrating the operation and effect of one embodiment of the present invention.
FIG. 4 is an input-output characteristic diagram of an S inverter.

FIG. 4 is a circuit diagram of a crystal oscillator illustrating another embodiment of the present invention.

FIG. 5 is a circuit diagram of a crystal oscillator illustrating a conventional example.

[Explanation of symbols]

1 oscillation circuit, 2 buffer amplifier, 3 crystal oscillator, 4
CMOS inverter, 5 feedback resistor, 6, 16 coupling capacitor, 7 delay drive circuit, 8 pulse generator, 9
Voltage drop circuit, 10 constant current source, 11 capacitor, 1
2, 14, 17, 18 FET, 13, 20 load resistance, 15 high-frequency blocking resistance, 19 voltage rising circuit.

Claims (3)

[Claims] 1. A crystal oscillator wherein a buffer amplifier is connected to an oscillation circuit and both are driven by the same power supply, wherein the rise of the buffer amplifier is delayed more than the oscillation circuit. 2. The crystal oscillator according to claim 1, wherein an operating voltage at a rise of said buffer amplifier is shifted from a reference value, and an output at a rise is set to 0 or 1 level. 3. The crystal oscillator according to claim 1, wherein a delay circuit is provided between said buffer amplifier and a power supply.