JP2001024563A - Symbol synchronizing device and frequency hopping receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a symbol synchronizing device prevented from being easily influenced by phase variation and capable of executing symbol synchronization even when carrier synchronization is not executed. SOLUTION: Binary phase angle differential signals are successively inputted to a correlation output part 31, which detects correlation with a reference phase bit string. A latch 32 latches a correlation signal at the build up timing of a periodic signal outputted from a VSCO 33. The output from the latch 32 is inputted to an error correction part 34 to control the start phase of one period succeeding the VSCO 33 in accordance with a phaser error between a symbol synchronizing preamble and the periodic signal outputted from the VSCO 33. The error correction part 34 outputs an error state to a synchronization judging part 35. The judging part 35 judges the establishment of synchronization in accordance with the error state and outputs a clock signal on the basis of the periodic signal outputted from the VSCO 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symbol synchronizer for synchronizing symbols when demodulating a digitally modulated signal, and a frequency hopping receiver using the symbol synchronizer. This frequency hopping receiver is suitable for use in, for example, a wireless LAN system.

[0002]

2. Description of the Related Art Spread Spectrum (SS)
m) As one system of communication, frequency hopping system (Frequency Hopping, hereinafter referred to as FH system)
There is. In addition, this FH system and direct diffusion (Direct
Sequence / DS system). FIG.
1 is a block diagram showing an example of a conventional FH system. In the figure, 71 is an encoder, 72 is a digital modulator, 7
3 is a mixer, 74 is a hopping pattern generator, 75 is a frequency synthesizer, 76 is a high-frequency amplifier, 77 is a transmitting antenna, 78 is a receiving antenna, 79 is a high-frequency amplifier, 8
0 is a mixer, 81 is a hopping pattern generator, 82 is a frequency synthesizer, 83 is a digital demodulator, and 84 is a decoder.

On the transmitting side, transmission information is transmitted to an encoder 71.
Is subjected to information source coding and converted into transmission data. At this time, encoding suitable for transmission may be performed as necessary. This transmission data is digitally modulated in the intermediate frequency band by the digital modulator 72, and then frequency-converted by the output signal of the frequency synthesizer 75 in the mixer 73. According to the hopping pattern output from the hopping pattern generator 74, the frequency synthesizer 75 switches the transmission frequency channel by temporally changing the frequency to be frequency-converted. Therefore, the digitally modulated signal is transmitted on a frequency channel corresponding to the hopping pattern. As a result, the signal is spread and becomes a spread spectrum signal having a wide frequency band, amplified by the high frequency amplifier 76 and transmitted from the transmission antenna 77.

On the receiving side, the spread spectrum signal is:
The signal is received by the receiving antenna 78, amplified by the high-frequency amplifier 79, input to the mixer 80, and despread.
The hopping pattern generator 81 generates the same hopping pattern in synchronization with the hopping pattern generator 74 on the transmission side, and the frequency synthesizer 82 outputs a reference oscillation signal having the same frequency as that output from the frequency synthesizer 75 on the transmission side. I do. Then, by selectively receiving a signal of the same frequency channel as the transmitted signal, the transmitted spread spectrum signal is despread to be a signal of an intermediate frequency band. The despread signal is input to the digital demodulator 83 by passing a signal component of a reception frequency band of each frequency channel in an intermediate frequency band by a band-pass filter (not shown). The digital demodulator 83 obtains demodulated data by performing digital demodulation corresponding to the digital modulator 72 on the transmission side. The decoder 84 performs information source decoding on the demodulated data corresponding to the encoder on the transmission side and outputs received information. At this time, decoding for transmission may be performed corresponding to the encoder on the transmission side.

[0005] Currently, the mainstream digital modulation method is Quadrature Phase Shift Keying,
Hereinafter, referred to as QPSK)
ying (hereinafter referred to as PSK) or quadrature amplitude modulation (Quadrtutu)
re Amplitude Modulation (hereinafter, referred to as QAM). In mobile communication, differential detection is the mainstream in QPSK demodulation. However, since synchronous detection has good error rate characteristics, synchronous detection is mainly used for fixed communication. Therefore, when considering an optimal design, it is desired to use delay detection and synchronous detection together so that switching can be performed according to the communication path environment, and to ensure high communication quality in data communication. However, in synchronous detection, symbol synchronization (bit synchronization) is usually performed after carrier recovery is performed and carrier synchronization is established. In the FH system, carrier synchronization, symbol synchronization (bit synchronization) is performed every time a frequency channel is switched. ), Frame synchronization, and data reception, the following problems specific to the FH system occur.

FIG. 14 is an explanatory diagram showing a frequency change of a carrier in the FH system. FIG. 15 is an explanatory diagram of a start portion of a transmission frame transmitted during a frequency hopping period in the FH system. 14, the frequency conversion on the transmission side (diffusion), the carrier of the digital modulated signal, continue to vary continuously from the frequency f ₁ to the current frequency f _2, the purpose of elapsed a certain time It fits in the vicinity of the frequency f _2. However, since a PLL is generally used for frequency conversion, the frequency f
Even in the vicinity of _2, the frequency of the carrier, continue to converge while oscillating in the vicinity of the frequency f ₂ for the purpose. Further, also on the receiving side, since the PLL is used for frequency conversion, the carrier of the signal converted to the intermediate frequency band by the frequency conversion (despreading) similarly converges while oscillating around the intermediate frequency. Will be. This oscillating period is called a settling period. Reception of a transmission frame is started during this settling period. As an example, the frame format starts with a symbol synchronization preamble shown in FIG. 15 and then continues with a frame synchronization signal and information data. In the synchronous detection, during the symbol synchronization preamble period, the carrier synchronization circuit performs a phase lock operation to create a copy of the carrier.

In a circuit using a conventional Costas loop as a carrier synchronization circuit, baseband signals I and Q demodulated based on a symbol synchronization preamble are calculated, and a phase error with respect to a carrier is output from a digitally modulated signal. I do. This phase error is smoothed by a loop filter, and the oscillation frequency of the reference frequency oscillator is controlled so as to follow the frequency of the carrier.

However, since the response of the loop filter is slow, it takes time until the carrier synchronization is completed. Therefore, it is necessary to lengthen the symbol synchronization preamble of the frame. Further, it is necessary to perform a symbol synchronization operation for outputting a clock signal from the completion of the carrier synchronization. As a result, if the time of one frame is short, the preamble length occupies most of the frame length, and the ratio of the time for transmitting data is reduced, resulting in a problem that the throughput is deteriorated. In order to improve the throughput, it is necessary to shorten the symbol synchronization preamble. Therefore, it is desired that symbol synchronization can be performed without performing carrier synchronization (carrier phase tracking).

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and enables symbol synchronization without performing carrier synchronization, and is less susceptible to carrier phase fluctuations. It is an object of the present invention to provide a symbol synchronizer and a frequency hopping receiver using the symbol synchronizer.

[0010]

According to the present invention, a symbol synchronization signal in which the phase rotation direction with respect to a carrier is inverted for each symbol in a symbol synchronization signal of a digitally modulated signal is received, and the symbol of the digitally modulated signal is received. A symbol synchronizer that outputs a clock signal synchronized with a phase angle output unit, a phase angle differentiation unit, a correlation output unit,
A periodic signal generation unit, a phase error determination unit, and an error correction unit, wherein the phase angle output unit outputs a phase angle signal representing an IQ plane phase angle of the digitally modulated signal with respect to a reference frequency signal; The phase angle differentiating means inputs the phase angle signal, outputs a phase angle differentiating signal obtained by time-differentiating the phase angle, and the correlation output means inputs the phase angle differentiating signal, and outputs a reference phase data sequence. The correlation signal is output by taking the correlation of
Generating a periodic signal whose period can be controlled, and outputting the periodic signal or a signal based on the periodic signal as the clock signal, wherein the phase error determining means determines the level of the correlation signal at a predetermined phase timing of the periodic signal. By detecting a phase error between the phase angle signal and the periodic signal when the symbol synchronization signal is received, and the error correction unit determines a period of the periodic signal according to the phase error. To control. Therefore, since the extra phase fluctuation of the carrier is canceled by the phase angle differentiating means, the phase angle differentiating means is less susceptible to, for example, a frequency offset appearing when the carrier is not synchronized. In addition, even when carrier synchronization is performed, it is hardly affected by phase fluctuation. Although the phase angle differentiating means is sensitive to disturbance, the influence of the disturbance is canceled by the integration operation of the correlation output means, so that simple and stable synchronization can be achieved.
As a result, the operation of the symbol synchronizer is stabilized.

In the present invention, the correlation output means may further include:
A signal obtained by binarizing the phase angle differential signal is sequentially input to a shift unit, and it is determined whether each tap output of the shift unit matches the binarized reference phase data sequence. Are sequentially output. Therefore,
The correlation value can be output with a simple configuration.

In the present invention, the phase error determining means may detect the level of the correlation signal at the predetermined phase timing of the periodic signal and at a timing before and after the predetermined phase timing. An error determining unit that includes a synchronization determining unit, which determines that the phase error at the predetermined phase timing is small over one or a plurality of periods of the symbol synchronization signal. The output of the clock signal to the outside is started when it is determined that at least one of the phase error at the predetermined phase timing and the preceding and following timings is small over one or a plurality of periods of the symbol synchronization signal. Therefore, it is possible to make a synchronization determination that is hardly affected by the phase jitter.

According to the present invention, each time a frequency channel is switched, a symbol synchronization signal whose phase rotation direction is inverted with respect to a carrier at a signal point of a digitally modulated signal is received and synchronized with the symbol of the digitally modulated signal. A frequency hopping receiver including a symbol synchronizer that generates a clock signal, wherein the symbol synchronizer having any of the above-described various forms is used as the symbol synchronizer. Therefore, when frequency channels are switched, symbol synchronization acquisition can be performed in a short time. As a result, the preamble for synchronization can be shortened, and the data throughput is improved.

[0014]

FIG. 1 is a block diagram of a digital demodulator for explaining an embodiment of a symbol synchronizer according to the present invention. In the figure, 1 is a reference frequency oscillator, 2
Is a 90 ° phase shifter, 3 and 4 are demodulation multipliers, 5 and 6 are low-pass filters, 7 is an A / D converter, 8 is an IQ phase angle calculation unit, 9 is a symbol synchronization unit, 10 is a differential output unit, 11 is 1
Sampling clock delay unit, 12 is a subtractor, 13 is 2
A value conversion unit 14 is a digital PLL (DPLL) unit, and 15 is a phase angle determination unit. The description will be given on the assumption that QPSK demodulation is performed, but the same applies to carrier synchronization and symbol synchronization even when QAM demodulation is performed. FIG. 2 is an operation explanatory diagram of the block configuration of FIG. 1 at the time of receiving a symbol synchronization preamble. Numerical data is represented as a waveform. FIG. 16 is an explanatory diagram illustrating an example of a symbol synchronization preamble. As an example, four-phase modulation (QPS
The case of K) is shown on the IQ phase plane coordinates. The symbol synchronization preamble is defined as a repetitive signal according to the technical standards for radio equipment. In QPSK, IQ
It is assigned to two states of + 90 ° rotation and -90 ° rotation on the phase plane.

In FIG. 1, a received signal whose frequency has been converted to an intermediate frequency band is balanced-demodulated by demodulation multipliers 3 and 4 by a reference frequency signal output from a reference frequency oscillator 1 and passed through low-pass filters 5 and 6 to a baseband. The signals become I and Q. The A / D converter 7 converts each of the baseband signals I and Q into numerical data at the timing of the sampling signal. The sampling signal is set to be generated a plurality of times, for example, 16 times per unit period of one symbol (one bit when viewed as baseband signals I and Q). In the IQ phase angle calculation unit 8, A /
Numerical data output from the D converter 7 is input, and the phase angle of the digitally modulated signal with respect to the reference frequency signal is discriminated. Specifically, the calculation is performed with reference to a trigonometric function operation or a lookup table.

The symbol synchronization section 9 receives the phase angle, detects a symbol synchronization preamble signal in which the symbol phase rotation direction of the carrier is inverted at the symbol signal point, and detects a symbol synchronization pulse synchronized with the symbol synchronization preamble signal. (Clock signal), and outputs this to the phase angle determination unit 14. The phase angle determination unit 14 outputs demodulated data by determining the phase angle output from the IQ phase angle calculation unit 8 using the symbol synchronization pulse as the determination timing. In the symbol synchronizing unit 9, the output of the differential output unit 10 including the one sampling clock delay unit 11 and the subtractor 12 is binarized by the binarizing unit 13 as a phase angle differential signal, and sent to the digital PLL unit 14. Is entered. Digital PLL unit 14
Outputs a symbol synchronization pulse (clock signal) in synchronization with the binarized phase angle differential signal.

Referring to FIG. 2, the operation of the symbol synchronization section shown in FIG. 1 will be specifically described. FIG. 2A shows, as a waveform amplitude, a phase angle signal output by the IQ phase angle calculation unit 8 when a symbol synchronization preamble is being received. Actually, a sampling value as shown in FIG. 2D is output as digitized data. For the sake of clarity of the drawing, this specification shows that eight sampling clocks are generated per symbol, but the prototype machine uses 16 sampling clocks per symbol. In the phase angle signal, a portion having a positive slope and a portion having a negative slope appear repeatedly for each symbol. The positive and negative peak points are
The symbol signal point, that is, the center point of the symbol section. Each of the baseband signals I and Q is the center point of a bit section. In other words, if the baseband signals I and Q are sampled at the peak timing, symbol (bit) synchronization can be achieved, so that demodulated data can be determined corresponding to the symbol signal point.

However, when symbol synchronization or demodulation data is determined, there is a static frequency shift (frequency offset) between the transmitting side and the receiving side due to the frequency error of the reference frequency oscillator. As shown in FIG. 2A, the phase angle of the carrier is shifted in one direction as a whole due to the frequency offset. In addition, in the communication between the base station and the mobile, the reception frequency is shifted due to the Doppler effect. Furthermore, there is a problem that the frequency fluctuates during the settling period of the frequency hopping. In the differential output section 10, I
The phase angle data output from the Q phase angle calculation unit 8 is input to the one sampling clock delay unit 11 and the one sampling clock delay unit 11.
The phase angle data output from is subtracted. As a result, a signal obtained by subtracting (differentiating) the phase angle is output.

FIG. 2B shows a phase angle differential signal output from the differential output unit 10 as a waveform amplitude during reception of the symbol synchronization preamble. In fact, Figure 2
The sampling value as shown in (e) is output as digitized data. By taking the difference, the phase drift due to the frequency offset is removed. Although the slope of the frequency offset is a DC offset, the DC offset can be easily removed. Not only frequency offset but also gradual fluctuation of frequency can be removed. FIG.
Since the level change timing of the binarized phase angle differential signal shown in (c) corresponds to the switching point of the inclination of the phase angle,
As a result, a symbol signal point can be detected. The interval between the level change timings is the period of the transmitted symbol and is not affected by frequency fluctuations.

The digital PLL section 14 compares the phase of the binarized phase angle differential signal with the internally generated periodic signal, and corrects the period of the periodic signal according to the phase error. The phase is locked to the phase of the binarized phase angle differential signal. When it is locked continuously,
The clock signal is output to the phase angle determination unit 15. The phase angle determination unit 15 determines the phase angle output from the IQ phase angle calculation unit 8 at a predetermined timing of the clock signal,
The digitally demodulated data determined at the symbol signal point timing is output.

FIG. 3 is an explanatory diagram showing the movement of the phase plane coordinate axis with reference to the carrier of the digitally modulated signal. In order to perform digital demodulation, not only symbol synchronization but also carrier synchronization is required in principle. If carrier synchronization (carrier phase tracking) is not performed, the phase plane coordinate axis based on the carrier rotates over time on the phase plane coordinate based on the reference frequency signal. The phase plane coordinate axis of the reference frequency signal is [I ₀ , Q ₀ ]. At first, even if the phase of the reference frequency signal completely matches the phase of the carrier, the phase plane coordinate axis of the carrier is, for example, [I
₁ , Q ₁ ] (offset phase angle Δ ₁ ), [I ₂ , Q ₂ ] (offset phase angle Δ ₂ ),...

Since the symbol signal points of the digitally modulated signal are defined on the phase plane coordinates of the carrier,
Rotate together. For example, the symbol signal point of the symbol synchronization preamble signal indicated by a black circle moves temporally when viewed on the phase plane coordinates of the reference frequency signal.
Since the baseband signals I and Q are I and Q components on the phase plane coordinates [I ₀ , Q ₀ ] based on the reference frequency signal,
If this can be sampled only at the center of the symbol (bit), the phase plane coordinates [I ₁ , Q ₁ ], [I ₂ , Q ₂ ] of the carrier of the digitally modulated signal, I, Q on No components are obtained. However, the phase angle determination unit 15 has a margin of ± 45 ° in the determination. Therefore, unless the offset phase angle rotates beyond the range of ± 45 °, no error substantially occurs. As a result, no determination error occurs unless the phase shift exceeds the allowable range during one synchronization frame period. The differential signal in FIG. 2C is stable in this range, and a symbol synchronization point has been established.

It is also possible to perform demodulation following a change in carrier phase. The present applicant has filed Japanese Patent Application No. 10-288.
No. 316 and Japanese Patent Application No. 10-288317 have applied for an invention relating to a carrier phase tracking device. To explain the outline, the phase angle of the demodulated signal output from the IQ phase angle calculation unit 8, the judgment timing of the clock signal described above, the data determination after performing correction according to the known offset phase angle delta ₁ as well as to update the offset phase angle delta ₁ in accordance with the shift amount of the offset phase angle (Δ ₂ -Δ _1). At this time, the IQ phase angle calculation unit 8 determines that the phase angle is 3
When the phase angle changes (rotates a plurality of times) beyond the range of 60 °, the change of the phase angle is continuously tracked beyond the range of 360 °. As a result, even if carrier synchronization is not performed prior to symbol synchronization, digital demodulation can be performed even if the phase angle rotates beyond the range of ± 45 ° if symbol synchronization is achieved.

Returning to FIG. 1, the symbol synchronization section 9 will be described. By the above-described differentiation operation, it is possible to obtain a clock signal in which a phase change due to a frequency offset or the like has been canceled. However, since the differential operation is included in the extraction of the symbol change point, the disturbance of the phase angle due to noise, multipath fading, delay spread, etc.
Since it reacts sensitively, the operation may be unstable. First, a description will be given of a case where the digital PLL unit 14 pre-processes the binarized phase angle differential output using a histogram circuit.

FIG. 4 is a block diagram of the histogram circuit. In the figure, 21-1 to 21-16 are shift registers, 22-
1 to 22-16 are adders, 23 is a shift register group shift control unit, and 24 is a histogram data selector. FIG.
6 is an explanatory diagram of a sampling signal input to the histogram circuit shown in FIG. The symbol synchronization preamble signal is supplied to the differential output unit 10 and the binarization unit 13 shown in FIG.
, And becomes a binarized phase angle differential signal.

If the binarized phase angle fine signal is represented by a waveform,
One cycle has a length of two symbols. By taking the difference between the binary phase angle differential signals, the symbol change point (symbol signal point)
Is obtained. This change point signal is input to the shift register groups 21-1 to 21-16. The number of sampling clocks is determined to be a predetermined number per symbol length, but is shown as 16 per symbol length. The sampling clock within this one symbol length will be described with circled numbers (1) to (16) according to the sampling point.

In FIG. 4, a symbol change point signal is distributed to shift registers 21-1 to 21-16 of corresponding numbers according to sampling points.
Is entered. The shift register group shift control unit 23
Thus, the inside of each shift register 21-1 to 21-16 is shifted once for one symbol length. In the shift register group, a symbol change point signal has a plurality of cycles,
Accumulates over a period. Each shift register 21-1 to 21
-16, the outputs of the taps are added by the adders 22-1 to 22-16 and output to the histogram data selector 24. The histogram data selector 24 obtains a histogram of symbol change points for each sampling point over a plurality of cycles (a plurality of symbols),
Select the most probable symbol change point statistically. The selected symbol change point is used to control the phase of the internal oscillator.

FIG. 6 is a schematic diagram for explaining a histogram of symbol change points. Sample point
The appearance frequency of the symbol change point is shown for each of (1) to (16). In the illustrated example, it is estimated that the symbol change point of the symbol synchronization preamble is at the sampling point (1). However, due to the above-described disturbance, a false symbol change point appears in the histogram, and simply estimating the sampling point having the highest frequency as the symbol change point results in inaccurate symbol synchronization or, in some cases, synchronization detection. There is a risk of becoming disabled.

FIG. 7 shows the digital PLL unit 1 shown in FIG.
4 is a block diagram showing a first example of FIG. In the figure, 31
Is a correlation output unit, 32 is a latch, 33 is a VSCO (Variab
le Step controlled Oscillator), 34 is an error correction unit, and 35 is a synchronization determination unit. The VSCO 33 is a digital oscillator that can control the phase of the oscillation cycle stepwise according to input information. FIG. 8 is a block diagram showing an example of the correlation output unit shown in FIG. In the figure, 41 is a shift register, 42 is an exclusive OR (EXOR), and 43 is an adder. This digital PLL section includes a correlation output section 3
Since 1 is an integral element, simple and stable symbol synchronization is possible even when a differential output is input.

The binary phase angle differential signal is sequentially input to the correlation output unit 31. As will be described later, the correlation between the binarized phase angle differential signal and the set reference phase bit sequence (reference phase signal) is detected, and a correlation signal is output. VSCO
33 generates at least one periodic signal capable of controlling the start phase of one cycle in a stepwise manner. The above-described correlation signal is latched in the latch 32 at the rising timing of the periodic signal. At the same time, in order to obtain symbol signal point timing for phase angle determination, a signal that is phase-synchronized with this periodic signal is generated and output as a clock signal. Note that the periodic signal itself may be a clock signal. The output of the latch 32 is input to the error correction unit 34. The error correction unit 34 outputs to the VSCO 33 a cycle control signal corresponding to the phase error between the symbol synchronization preamble and the cycle signal of the VSCO 33, and outputs the next cycle signal. The start phase of the cycle (for example, the rising timing) is controlled. At the same time, the error correction unit 34 outputs the error state to the synchronization determination unit 35. The synchronization determination unit 35 determines the establishment of synchronization in accordance with the error state, and starts to output, as a clock signal, a signal output from the VSCO 33 and phase-synchronized with the above-described periodic signal.

The correlation output unit will be described with reference to FIG. 2
The quantified phase angle differential signal is sequentially input to the shift register 41 by a predetermined number per symbol length, in the example shown, eight sampling clocks. In the illustrated example, the shift register 41 is set to the number of taps for accumulating binary data for one cycle and two symbol lengths. Shift register 4
For each tap output of 1, in the exclusive OR 42, the correlation of coincidence or non-coincidence with the bit string indicating the reference phase is determined, and the number of coincidences is added in the adder 43.
The adder 43 outputs a correlation signal indicating the phase relationship between the binarized phase angle differential signal and the reference phase.

FIG. 9 is an explanatory diagram of the operation of the correlation output section shown in FIG. FIG. 10 is an operation explanatory diagram showing a correlation signal output from the correlation output unit shown in FIG. FIG. 9 (a)
The reference phase data {1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0} is represented along the tap of the shift register in FIG. Things. FIGS. 9B to 9F show binary phase angle differential signals along the taps of the shift register in FIG. FIGS. 9B to 9E show states at times t = t _{0 to} t ₄ , respectively. FIG. 9F shows that at the same time t = t ₁ as FIG.
It represents the state where there was disturbance.

In the case of FIG. 9B, since the outputs of the exclusive ORs 42 shown in FIG. 8 are all 0, the correlation signal output from the adder 43 is also 0. In the case of FIG.
Since half of the six exclusive ORs 42 is 1, the output of the adder 43 is 8. In the case of FIG. 9D, since all the exclusive ORs 42 are 1, the output of the adder 43 is 1
It becomes 6. In the case of FIG. 9E, the output of the adder 43 becomes 8 again. As shown in FIG. 10, the correlation signal outputs a triangular correlation signal according to the phase with respect to the reference phase signal in a period of 2 symbols in one cycle. Time t
In = t _1, the correlation values, taking the median 8 of the maximum value 16 and minimum value 0. This central value is a value corresponding to １ ／ of the number of taps of the shift register 41. At this time, the binarized phase angle differential signal is at the boundary of one symbol section after a 周期 period (１ ／ symbol length) has elapsed from the fall. The inside of the shift register 41 shown in FIG. 8 is in the state shown in FIG. 9C. Therefore, if the phase of the first periodic signal output by the VSCO 33 is locked at the time when the correlation value is the median value 8, the periodic signal generated by the VSCO 33 is converted into a symbol input as a binary phase angle differential signal. It can be synchronized with the period of the synchronization preamble. At the time t = t _3, the same correlation value as at the time t = t ₁ is output. However, at time t = t ₁ ,
= T ₃ means the shape of the correlation value output and / or
There is no problem because it can be easily determined from the register value distribution of the shift register 41. For example, by monitoring the time derivative of the correlation value, it can be seen that the time is t = t ₁ in a positive period and the time is t = t _{3 in} a negative period.

The correlation signal output from the correlation output section 31 is latched at the rising timing of the periodic signal output from the VSCO 33. If the period of the periodic signal generated by the VSCO 33 is longer than the period of the binarized phase angle differential signal, the level of the latched correlation signal becomes higher than the above-described predetermined value (median value 8). At this time, the error correction unit 3
4 controls so as to shorten the next cycle of the periodic signal output from the VSCO 33. Conversely, if the cycle of the periodic signal is shorter than the cycle of the binarized phase angle differential signal, the level of the latched correlation signal becomes smaller than the above-described predetermined value (median value 8). At this time, the error correction unit 34 sets the VSCO3
3 is controlled so as to lengthen the next cycle of the output periodic signal. In this way, the period of the periodic signal is feedback-controlled, and the output phase of the periodic signal is synchronized with the phase of the binarized phase angle differential signal. In the phase synchronization state, the symbol signal point at the center of one symbol section is at the level change point of the binarized phase angle differential signal. Therefore, V
If a signal whose phase is shifted by ４ cycle (１ ／ symbol length) from the above-described periodic signal is generated from the SCO 33 and this signal is used as a clock signal, its falling and rising become symbol signal points. In addition, a signal having a half cycle that rises in synchronization with the rise of the above-described periodic signal is generated from the VSCO 33, and if this signal is used as a clock signal, the fall becomes a symbol signal point. Note that a value deviating from the above-described median value 8 may be set as the predetermined value. The phase of the periodic signal output by the VSCO 33 is locked at the phase at which the correlation value becomes the predetermined value. However, it is avoided to lock the phase near the phase where the correlation value indicates the upper and lower peaks. When a value deviating from the median value 8 is set to a predetermined value, it is necessary to determine the output phase of a signal that is output as a clock signal and is phase-synchronized with the above-described periodic signal so that the phase angle can be determined at the timing of a symbol signal point. There is.

In the above description, as the reference phase bit string (reference phase signal), in the waveform representation shown in FIG. 9A, a bit string having a duty ratio of 50%, where the left half is all 1's and the right half is all 0's Is used, but a bit string in which this arrangement is cyclically shifted may be used. Of course, a reference phase bit string having a plurality of cycles may be used. In addition, although the description has been made with the period of the reference phase bit string and the period of the input binary phase angle differential signal being matched, it is not necessary that the two periods match unless the periods are significantly different. Although a slight shift occurs depending on the setting of the cycle of the input signal, the cycle of the reference phase bit string, and the sampling clock cycle, the input signal is shifted symmetrically or almost symmetrically as shown in FIG. , The correlation value becomes the median value or a value near the median value. Therefore, at the time when the correlation value is the median value or a predetermined value near the median value and the correlation value has a positive slope, VSCO
If the phase of the periodic signal output by 33 is locked, the periodic signal is synchronized with the cycle and phase of the input signal regardless of the cycle of the input signal, unless the cycle of the input signal is significantly different from the cycle of the reference phase bit string. be able to.

In the illustrated example, the correlation between bit data is detected by using 0 and 1 as binary values. However, the correlation can be detected by other means. For example, if −1 and 1 are used as binary values, exclusive OR 4
By replacing the operation of 2 with multiplication, a correlation value can be similarly output. Instead of the input binarized phase angle differential signal, a phase angle differential signal before binarization (one sample value having a plurality of bits having a polarity) including the binarized phase angle differential signal may be used. Also, instead of the reference phase bit string, a reference phase data string including this (one data is a plurality of bits having polarity)
May be used. In the above case, if the function of the shift register 41 is executed by controlling the memory, it does not matter whether the input signal is bit data.

Here, description will be made returning to FIG. The error correction unit 34 receives the output of the latch 32 and
The error data is fed back to the VSCO 33 to control the start phase of the next cycle. Thus, the digital PLL unit shown in FIG. 7 is locked in. The synchronization determination unit 35 determines lock-in when the phase of the binarized phase angle differential signal and the phase of the periodic signal output from the VSCO 33 are synchronized, and outputs a signal phase-synchronized with the periodic signal as a clock signal. The phase angle determination unit 15 shown in FIG. 1 determines the phase angle of the central signal point of the symbol based on the clock signal. However, it is also conceivable that a disturbance caused by various causes may cause a condition to be accidentally regarded as lock-in. Therefore, when the periodic signal output from the VSCO 33 is locked while maintaining the same period (state in which error correction is not performed) over a plurality of predetermined symbols, it is determined that synchronization has been achieved.

In FIG. 10, when the periodic signal output from the VSCO 33 rises at or near the time t = t ₃ , it is determined that the slope of the correlation value is opposite as described above. it can. In the reverse state, the loop of the VSCO 33 is forcibly kicked, and the VSCO 33 is started from the next rising sampling timing.
Is controlled so that the output phase of the VSCO becomes a VSCO output waveform as shown or a waveform having a phase close thereto. As a result, high-speed lock-up becomes possible.

The problem here is phase jitter due to disturbance or SSB noise of the local oscillator. If there is phase jitter, the lock-in state may not be established at the next rising timing of the periodic signal output from the VSCO 33 even if it is determined to be locked in at the previous rising timing of the periodic signal output from the VSCO 33. However, if the phase jitter is slight, the lock-in state occurs at the sampling timing before and after this. In this case, if there is no phase jitter, the state is to be determined as a "synchronous state", so it must be allowed.

FIG. 11 is a block diagram showing a second example of the digital PLL section shown in FIG. In the figure, the same parts as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. 51
Is an error determination unit, 52 is a 3-tap shift register, 5
Reference numeral 3 denotes a one-sampling timing delay unit, reference numeral 54 denotes a 3-bit latch, and reference numeral 55 denotes a synchronization determination unit.

In the second example, the output of the correlation output unit 31 is used by an error determination unit 51 to determine whether the absolute value of the error output is small, for example, 2 or less. When the absolute value of the error is 2 or less, “1” is set, and when the absolute value of the error exceeds 2, “0” is set.
(The correlation value changes by ± 2 due to a phase shift of one sampling timing). The 3-tap shift register 52 shifts input bits by a sampling clock. The rising timing of the VSCO 33 is input to the 3-bit latch 54 after being delayed by the one-sample timing delay unit 53, the output of the 3-tap shift register 52 is latched at the input rising timing, and Output in parallel. At this time, the timing of the rising pulse of the VSCO 33 and the determination result of the error determination unit 51 before and after the one sampling clock are input to the 3-tap shift register.
This determination result is latched. Strictly, the one-sample timing delay unit 53 delays slightly longer than the one-sample timing so that the latch is performed after the shift register 52 completes one-tap shift.

The synchronization determining section 55 takes the procedure of establishing symbol synchronization by the following sequence in consideration of the jitter. (1) The lock-in is determined by latching the error output of the correlation output unit 31 at the rising timing of the periodic signal output from the VSCO 33, and when the error determination unit 51 determines that the absolute value of the error is within a predetermined value, for example, , The error output is +
At 2, 0, -2 (phase shift within one sampling timing), lock-in is set to true. When lock-in is true, the central latch of the 3-bit latch 54 is 1. Note that, at this time, the error correction unit 34 sets the VSCO 33
Is zero. (2) It is determined that the lock-in state defined in the above (1) is continued over one or a plurality of predetermined symbol lengths, preferably a plurality of symbol lengths, for example, two symbols. (3) Next, at one of the rising timing of the periodic signal output from the VSCO 33 and the three timings of the error determination output in each sampling clock before and after the rising edge, the lock-in described above is true (a 3-bit latch). If any one of 54 is 1), the symbol synchronization acquisition operation is continued. (4) If the symbol synchronization acquisition operation of (3) continues one or more predetermined times, preferably a plurality of times, for example, four times, the lock-in is finally determined, and the phase angle determination unit 14 in the subsequent stage
In FIG. 1, external output of a clock signal output from the VSCO 33 is started.

In the example shown in the figure, a shift register 52 of 3 taps and a latch 54 of 3 bits are used to determine an error in the rising timing of the VSCO 33, one sampling timing immediately before it, and one sampling timing immediately after it. Synchronization was determined. Alternatively, the synchronization may be determined by determining an error between the rising timing of the VSCO 33 and a plurality of sampling timings before and after the rising timing of the VSCO 33. In this case, a shift register having four or more taps and a latch having the same number of bits may be used. In the shift register having a plurality of taps, the VSCO3 is selected according to the design of the tap position for holding the error at the rising timing of the VSCO33.
3 is delayed by a delay unit similar to the one-sampling-timing delay unit 53, and the output of the shift register having a plurality of taps is taken into a latch of a plurality of bits. Alternatively, the synchronization may be determined by determining an error between the rising timing of the VSCO 33 and the sampling timing separated by a plurality of samples before and after this.

Next, the basic operation of the above-described digital PLL will be described. FIG. 12 is a simplified block diagram of the digital PLL loop shown in FIG.
In the figure, 61 is a correlation output unit, 62 is an error correction unit, and 63 is V
SCO and latch. As shown in FIG. 12, the digital PLL is a first-order IIR filter (Infinite impulse filter).
se Response Filter). The coefficient calculation in the error correction section 62 is performed by β = １ ／
And the fraction is truncated. In addition, VSCO63
When the phase is incremented (or decremented) by one step due to the error correction, the output of the correlation output unit 61 that takes the exclusive OR is incremented (or decremented) by two steps. Is performed. As a result, the magnification becomes 1 in one loop. The transfer function by the Z transformation is as follows. H (Z) = 1 / (1−αβZ ⁻¹ ), where α = 2, β = 1/2

In the stability determination by the characteristic equation, the pole of Z =
Since it becomes 1, this is the boundary where the system becomes unstable. But,
In the error correction unit, the fraction is rounded down by the 演算 operation, so that it can be determined that there is no problem in the stability of the loop.
Let us consider the margin of the system for the differential operation.
The binarized phase angle differential signal is input to the correlation output unit 61. Here, the binarized phase angle differential signal is integrated over a data sequence having a length of two symbols. Furthermore, there is a PLL loop using a first-order IIR filter, and a total of 2
It has two integral elements. That is, although the input signal itself is a signal that has been subjected to a differential operation, the use of the digital PLL 14 described above results in a larger number of integral operations as a whole. As a result, the symbol synchronization section operates stably. This is a great advantage of the symbol synchronization unit 9 described above.

Next, noise and multi-bus fading will be briefly discussed. Since these all cause disturbance in the detection waveform (phase angle), the differentiated binary signal of the symbol synchronization preamble generates a chattering pulse when the H and L levels are switched. However, these signals are canceled to some extent by integration over two symbols in the correlation output unit 61.

Disturbance has a characteristic that the phase change amount is small, symbol interference is apt to occur, and the disturbance easily occurs at the leading edge and the trailing edge of the symbol. Further, since the communication path environment does not change so much in a short time, the state of the disturbance at the leading edge and the trailing edge can be assumed to be similar except for the white noise. This state is applied to the circuit operation. It is assumed that a sequence indicating the transmitted signals for two symbols for each sampling value is x, a sequence indicating the occurrence of disturbance is e (a sampling point at which the disturbance occurs is 1), and a received signal is y. However, for simplicity, it is assumed that the transmission vector is differentiated, and “,” indicates a symbol break. y: {01111110, 10000001} = x:
{11111111,00000000} + e: ¥ 10
Assume that the VSCO 33 operates at the lock-in position where these two symbols are shifted by １ ／ symbol, and the correlation output unit 61
, A correlation of two symbols with the reference phase signal is obtained.

FIG. 9C shows the signal x at this time.
FIG. 9F shows the signal y at this time. The phase comparison is
Since the operation is performed by an exclusive OR (XOR) operation for each sampling value, the result of the XOR is {1111,0001111,0000} when no disturbance occurs, and in the above case where the disturbance occurs, , $ 1110,10
001110, 1000 °, and the number of sampling points where 1 stands, that is, the correlation value has the same value 8 whether or not there is an error. That is, the error correction unit 62
Outputs a lock-in state, and can detect symbol synchronization safely even if there is disturbance.

The digital PLL unit described above can be used not only for a symbol synchronizer in a frequency hopping receiver or the like, but also for inputting a periodic signal by utilizing a structural feature having two integration elements. Thus, it can be used as a versatile digital PLL device that outputs a periodic signal synchronized with this signal.

In the above description, symbol synchronization in the case where carrier synchronization is not performed has been described. However, in the case where carrier synchronization is performed, symbol synchronization can be performed with a similar configuration. When carrier synchronization is performed, the differential operation by the differential output unit 10 in FIG. 1 is not necessarily required. When the differentiation operation is not performed, the phase angle signal output from the phase angle calculation unit 8 is
, And is input to the digital PLL unit 14. In the case where demodulation is performed by delay detection instead of synchronous detection, symbol synchronization can be performed with the same configuration. Also in this case, the differential operation by the differential output unit 10 is not necessarily required.

In the digital PLL section shown in FIG.
The quantified phase angle signal is correlated with a reference phase bit sequence in a correlation output unit 31, and the correlation value is output. As the reference phase bit sequence, those described above can be used as they are. In this case, the input waveform of the “binary phase angle differential signal” shown in FIG.
If the input waveform of the “valued phase angle signal” is used, one symbol section is shifted by １ ／ period and becomes a section illustrating “one symbol length”. Therefore, since the rising and falling points of the periodic signal output from the VSCO 33 are the center points of the symbol section, in other words, the symbol signal points, the periodic signal can be directly output as a clock signal.

[0052]

As is apparent from the above description, the symbol synchronizer of the present invention cancels out phase fluctuations and is therefore less susceptible to frequency offsets and carrier phase fluctuations that occur when carrier synchronization is not performed. This has the effect. The differential operation of the phase angle is sensitive to the disturbance, but is canceled by the integration operation of the phase detection means, so that there is an effect that simple and stable synchronization can be achieved. The frequency hopping receiver of the present invention can perform symbol synchronization even if the symbol synchronization preamble is short.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital demodulator for explaining an embodiment of a symbol synchronizer of the present invention.

FIG. 2 is a diagram illustrating a reception of a symbol synchronization preamble.
FIG. 2 is an operation explanatory diagram of the block configuration of FIG. 1.

FIG. 3 is an explanatory diagram showing movement of a phase plane coordinate axis with reference to a carrier of a digitally modulated signal.

FIG. 4 is a block diagram of a histogram circuit.

FIG. 5 is an explanatory diagram of a sampling signal input to the histogram circuit shown in FIG.

FIG. 6 is a schematic explanatory diagram for explaining a histogram of symbol change points.

FIG. 7 is a block diagram showing a first example of the digital PLL unit shown in FIG. 1;

FIG. 8 is a block diagram showing a correlation output unit shown in FIG. 7;

FIG. 9 is an operation explanatory diagram of the correlation output unit in FIG. 8;

FIG. 10 is an explanatory diagram showing a correlation signal output from a correlation output unit in FIG. 8;

FIG. 11 is a block diagram illustrating a second example of the digital PLL unit illustrated in FIG. 1;

FIG. 12 is a simplified block diagram of the digital PLL shown in FIG. 7;

FIG. 13 is a block diagram showing an example of a conventional frequency hopping system.

FIG. 14 is an explanatory diagram showing a frequency change of a carrier in the frequency hopping system.

FIG. 15 is an explanatory diagram of a start portion of a transmission frame transmitted in one frequency hopping period in the frequency hopping system.

FIG. 16 is an explanatory diagram showing an example of a symbol synchronization preamble.

[Explanation of symbols]

1 reference frequency oscillator, 8 IQ phase angle calculation unit, 9 symbol synchronization unit, 10 differential output unit, 11 1 sampling clock delay unit, 12 subtracter, 13 binarization unit, 14
Digital PLL unit, 31 correlation output unit, 32 latch, 33 VSCO, 34 error correction unit, 35 synchronization determination unit

Continued on the front page F term (reference) 5K004 AA05 AA08 FH08 JH05 5K022 EE04 EE36 5K047 AA15 BB01 EE02 EE04 GG11 HH03 HH15 MM34 MM60 MM63

Claims (4)

[Claims] 1. A symbol synchronizer that receives a synchronization signal whose phase rotation direction with respect to a carrier is inverted at a signal point of a digitally modulated signal, and outputs a clock signal synchronized with a symbol of the digitally modulated signal. A phase angle output unit, a phase angle differentiation unit, a correlation output unit, a periodic signal generation unit, a phase error determination unit, and an error correction unit, wherein the phase angle output unit performs the digital modulation on a reference frequency signal. Outputting a phase angle signal representing a phase angle of the signal; the phase angle differentiating means receiving the phase angle signal and outputting a phase angle differential signal obtained by time-differentiating the phase angle; A phase angle differential signal is input, and a correlation signal is output by correlating with a reference phase data sequence. The periodic signal generating means generates a periodic signal whose period can be controlled. And outputting the periodic signal or a signal based on the periodic signal as the clock signal, wherein the phase error determination means detects the level of the correlation signal at a predetermined phase timing of the periodic signal, thereby obtaining the synchronization signal. Determining a phase error between the phase angle signal and the periodic signal when the signal is received, wherein the error correction unit controls a cycle of the periodic signal according to the phase error. apparatus. 2. The correlation output means sequentially inputs a signal obtained by binarizing the phase angle differential signal to a shift means, and outputs each tap output of the shift means and the binarized reference phase data sequence. 2. The symbol synchronizer according to claim 1, wherein a determination is made as to whether or not the symbols match, and an added value of the determination outputs is sequentially output. 3. The phase error determining means determines the phase error by detecting a level of the correlation signal at the predetermined phase timing of the periodic signal and at timings before and after the predetermined phase timing. Wherein the synchronization determination means determines that the phase error at the predetermined phase timing is small over one or more cycles of the synchronization signal, and then determines one or more of the synchronization signals. The output of the clock signal to the outside is started when it is determined that at least one of the phase error between the predetermined phase timing and the timings before and after the predetermined period is small over a period. Symbol synchronizer. 4. Whenever a frequency channel is switched, a synchronization signal whose phase rotation direction with respect to a carrier is inverted at a signal point of a digitally modulated signal is received, and a clock signal synchronized with a symbol of the digitally modulated signal is received. A frequency hopping receiver comprising a symbol synchronizer that generates a signal, wherein the symbol synchronizer according to any one of claims 1 to 3 is used as the symbol synchronizer.