JP2001022710A - System with multiple bus controllers - Google Patents

Abstract

(57) [Problem] To provide a system capable of efficiently performing data transfer between processors. A bus control device includes a processor bus for connecting a processor, a memory bus for connecting a memory, a common bus for interconnecting a plurality of processors, and a plurality of processors. Each of the processors 1 includes circuits 31 to 40 for sharing the space of the memory 3 connected to the memory bus 12 of each of the bus controllers 30 when the processors 1 are connected via the common bus 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system having a plurality of bus controllers, and more particularly, to an electronic computer which connects a plurality of processors on the same bus and transfers data between the processors with high reliability. And systems related to electronic devices and electric devices.

[0002]

2. Description of the Related Art Conventionally, a system for connecting a plurality of processors to a common bus generally uses a shared memory system as shown in FIG. This is a system in which one memory 5 is shared among a plurality of processors 1. The processor 1 is connected to a bus controller 3 via a processor bus 2, and the bus controller 3 corresponding to each processor 1 4 is connected to a memory 5. Depending on the implementation, a plurality of memories with interleaved addresses may be arranged, but even in this case it is essentially a single memory.

In a system in which a plurality of processors of this type are connected to a common bus, the clocks of the processor bus and the common bus in the system need to be synchronized. Conventionally, as shown in FIG. The clock signal from the circuit 6 is supplied to a multiplication circuit 7 corresponding to each processor 1.
, The plurality of processors 1 are connected by a common bus 4 in a synchronous clock system.

Further, in a system in which a plurality of processors of this kind are connected to a common bus, as shown in FIG.
It is necessary to provide an identification number generation circuit 8 from the outside, and to provide a signal obtained by encoding the identification number to each processor 1 or the bus control device 3.

In this type of system in which a plurality of processors are connected to a common bus, the form of the processor bus is, for example, as shown in FIG. An interface 3A is provided, and a dedicated interface for a specific processor is provided for the B-type processor 1B such that the B control device 3 is provided with the B-dedicated interface 3B, or as shown in FIG. Is connected to a bus control circuit 3 having a general-purpose interface type interface 3C such as a static memory using a connection circuit 9.

Further, as shown in FIG. 16, in a system in which a plurality of processors of this type are connected to a common bus, an error occurs in the bus during data transfer, and a response signal does not return to the processor bus 2 for a predetermined time. In this case, a timer circuit 10 and a reset signal generation circuit 11 which externally monitor a timeout and reset the bus control device 3 are provided.
Was needed.

As shown in FIG. 17, in a conventional system in which a plurality of processors of this kind are connected to a common bus,
Register that specifies the space address of the local memory area accessed by the processor (internal memory address register)
A register (an external memory address register) 15 for designating a memory space address under the bus controller connected to another processor via the bus controller;
A register (external memory address register) 16 that specifies a memory space address accessed from another bus control device to its own memory space exists separately.

Conventionally, in a system in which a plurality of processors of this kind are connected to a common bus, as shown in FIG. 18, in order to transfer a memory between the bus controllers 3 without passing through the processor 1, a common bus is required. For example, DMA in 4
A controller 17 is added, and once the DMA controller 17 reads out the memory 13 under the transfer source bus controller 3,
An operation of writing to the memory 13 under the transfer destination bus control device 3 was required.

[0009]

However, the conventional methods shown in FIGS. 11 to 18 have the following problems. In other words, in the case of the method shown in FIG. In this case, data transfer from a certain processor 1 is performed once via a shared memory 5 on a common bus 4. Data is written from the transfer source processor 1 to the memory 5 on the common bus 4, and thereafter, the transfer destination processor 1 reads out the data from the memory 5 on the common bus 4, thereby performing one-unit transfer. In this case, access to the common bus 4 is performed twice for one unit transfer, and there is a problem that much time is required for data transfer.

In the method shown in FIG. 11, since one memory 5 is owned by the system, if a fatal defect occurs in this memory 5, data transfer between all processors 1 becomes impossible, and There is a problem that communication is interrupted. .

In the case of the system shown in FIG. 12, the clock of the common bus 4 and the processor bus 2 are synchronized, the processor bus 2 and the common bus 4 are set with the same frequency clock, and the frequency of the processor bus 2 is set to an integer. In some cases, the clock of the common bus 4 is set at the frequency divided by (1). In any of these cases, the clock phase must be synchronized. When a plurality of processors 1 are connected via the common bus 4, the clocks of all the processor buses 2 have no error and have a uniform phase. Must be implemented at different frequencies.

In order to realize such a circuit, it is necessary to externally mount a multiplying circuit 7 based on the clock of the common bus 4 and create a clock for the processor bus 2. The problem arose.

In the case of the system shown in FIG.
In order to recognize the in-system identification number, it is necessary to provide an identification number generation circuit 8 and provide a signal obtained by encoding the identification number from the outside to each processor 1 or the bus control device 3. In addition to the related signals, a signal line for an identification number is required for each processor 1 or the bus control device 3 connected to each processor 1, resulting in mounting or cost problems.

In the case of the system shown in FIGS. 14 and 15, the processor bus 2 of the bus controller 3
In the case of A, a bus controller 3 having a different interface of the processor bus 2 must be prepared in order to mount a plurality of types of processors 1, resulting in a cost problem. Further, when the processor bus of the bus control device is the general-purpose interface 3C, a connection circuit 9 for connecting the processor bus 2 and the general-purpose interface 3C is required, which causes problems in mounting and cost.

In the case of the method shown in FIG. 16, an external circuit such as a timer circuit 10 and a reset signal generating circuit 11 is required to detect an abnormality in access to the common bus, and there is a restriction on circuit mounting. was there. Further, since resetting after the detection of the timeout resets all functions of the bus control device 3, there is a possibility that a portion that does not need to be reset due to a timeout may be reset.

In the case of the system shown in FIG. 17, a register 14 for specifying a space address of its own memory area accessed from the processor 1 and a bus control device 3 connected to another processor 1 via the bus control device 3 Register 15 for designating a memory space address of the memory device and a register 16 for designating a memory space address accessed from another bus control device 3 to its own memory space exist separately. There was something. Also, if there is a discrepancy in the address setting of these registers,
There was a possibility that memory reference between processors could not be performed.

In the case shown in FIG. 18, a DMA controller 17 for controlling data transfer on the common bus 4 is required.
This has to be realized by an external circuit, which causes mounting and cost problems. In addition, in the case of realization by this method, access to the common bus in one unit transfer requires a total of two times of writing from the transfer source to the DMA controller 17 and writing from the DMA controller 17 to the transfer destination. There was a problem that efficient data transfer was not performed.

A first object of the present invention is to provide a processor bus.
Utilizing that the transfer speed between the memory buses is higher than the transfer speed between the common bus and the memory bus, the memory is distributed and arranged on the memory buses of the bus control device connected to each processor, so that the It is an object of the present invention to provide a system capable of increasing a required data transfer speed.

Further, since the memories are distributed to the respective bus controllers, even if a fatal defect occurs in one memory, communication between processors irrespective of the memory can be continued. Accordingly, it is an object of the present invention to provide a system for realizing communication between processors having high fault tolerance.

A second object of the present invention is to provide a system capable of normally transferring data even if there is a difference between clocks of respective processors on a common bus and realizing inter-processor communication without a multiplication circuit. Is to provide.

A third object of the present invention is to provide a system capable of acquiring an in-system identification number of each processor without requiring an additional signal such as an identification number.

A fourth object of the present invention is to prepare a separate bus control device having a dedicated interface,
It is another object of the present invention to provide a system which can be connected to a plurality of types of processors without external connection circuits.

A fifth object of the present invention is to reset a minimum necessary internal circuit without requiring an external circuit even if an abnormality occurs in access to a common bus, and to quickly reset the bus control device. It is an object of the present invention to provide a system capable of recovering the operation as the above.

A sixth object of the present invention is to provide a system capable of improving the circuit mountability by unifying a plurality of registers, and reducing the occurrence of a failure in memory reference due to a mismatch of addresses. Is to provide.

A seventh object of the present invention is to eliminate the need for an external circuit when performing transfer between memories of a bus control device without using a processor, and to complete transfer of a common bus only once, thereby improving efficiency. An object of the present invention is to provide a system capable of performing data transfer well.

[0026]

According to a first aspect of the present invention, in a system having a plurality of bus controllers, the bus controller connects a processor bus for connecting a processor to a memory. A memory bus for connecting a plurality of processors to each other, and the memory wherein each of the processors is connected to a memory bus of the bus control device when the plurality of processors are connected via the common bus. And means for sharing the space.

According to a second aspect of the present invention, there is provided a first-in-first-out memory according to the first aspect, wherein the bus control device makes an access request to the memory from the processor and an asynchronous master access request to the common bus. A circuit can be further provided.

According to a third aspect of the present invention, in the first aspect of the present invention, the bus control device executes an external access through the common bus from the processor and an internal access without the common bus through the common bus. The system of claim 1, further comprising means for performing:

A fourth aspect of the present invention is the system according to the first aspect, wherein the bus control device according to the first aspect of the present invention further comprises a plurality of processor interfaces and a multiplexer.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the bus control device includes an internal timer, an internal state transition circuit, and a response circuit to the processor, wherein the response circuit includes the internal timer and the processor. The system of claim 1, further comprising means for resetting an internal state transition circuit.

According to a sixth aspect of the present invention, in the first aspect of the present invention, the bus control device is provided with a register function for designating a space address of a local memory area accessed by the processor and a local bus control device. One register having a register function of designating a memory space address under another bus control device and a register function of designating a memory space address accessed from another bus control device to its own memory space The system of claim 1, wherein:

[0032] The invention according to claim 7 is the system according to claim 1, wherein the bus control device according to the invention according to claim 1 further comprises a data transfer unit.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A system according to a first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the bus control device 30 according to the first embodiment includes three ports of a processor bus 2, a memory bus 12, and a common bus 4. As shown in FIG. Bus control devices 30 (30-1 and 30-2) are distributed and connected.

The memory bus 1 of each bus control device 30
A memory 13 is connected to 2. Processor bus 2
Can access the own memory 13 and perform master access to the memory 13 under the other bus control device 30.

Further, one bus control device 30 can respond to a master access from another bus control device 30 as an access to its own memory 13 as a slave access.

The basic functions of the bus control device 30 are shown in FIG. That is, there are three types of basic access as follows. First, the access from the processor 1 to the memory 3 is its own memory access. An access from the processor 1 to the common bus 4 is a master access. In addition,
Master access to the common bus 4 is generally much slower than its own memory access because it requires processing to acquire ownership of the common bus 4 and the like. An access accessed from another bus control device 30 to the own memory 3 is a slave memory access.

Here, a detailed configuration of the bus control device will be described with reference to FIG. That is, access from a processor (not shown) is processed by the processor interface 31 via the processor bus 2. The memory address register 38 of the access from this processor
With respect to the address indicated by, a memory (not shown) connected to the memory bus 12 is accessed. The second address decode circuit 32-2 determines whether the access from the processor is the address specified by the memory address register 38.

Of the accesses from the processor, for the address indicated by the master address register 34,
Access to the common bus 4 occurs. The first address decode circuit 32-1 determines whether the access from the processor is the address specified by the master address register 34. An address conversion circuit 33 is provided as a circuit for performing address conversion when an address from the processor is output to the common bus 4. The access converted by the address conversion circuit 33 is output to the common bus 4 by the common bus master interface 35.

The common bus slave interface 36 responds to an access (slave access) from another bus control device 30 on the common bus 4. The common bus slave interface 36 regards the address specified by the slave address register 37 in the slave access as an access to its own memory, and does not respond to other accesses. The third address decode circuit 32-3 determines whether the access address from the common bus 4 is an address specified by the slave address register 37.

Memory access from the processor 1;
Since there is a possibility that the slave access from the common bus 4 may occur at the same time, the arbitration circuit 39 performs arbitration. The arbitration circuit 39 determines an access with a high priority, and accesses the memory on the memory bus 12 via the memory bus interface 40.

FIG. 3 shows the data transfer operation of the processor 1 and the two bus controllers 30-1 and 30-2 arranged on the common bus 4. First, the first processor 1
-1 generates a master access and writes data to the common bus 4. If the access address at this time matches the slave address register of the second bus control device 30-2, the second bus control device 30-2 performs a slave access operation and stores the data from the processor 1 in the second memory 13-2. Is written. After that, the second processor 11-4 accesses its own memory and
Transfer is performed by reading the data from -2.

As described above, in the data transfer between the processors (1-1, 1-2) in the present embodiment, the data is written in its own memory at the transfer source, and the processor at the transfer destination passes through the common bus 4 by master access. Or by reading the memory of the transfer source, or the transfer source writes data to the transfer destination memory via the common bus 4 by the master access, and the transfer destination processor 1 writes the data by the own memory access. This is performed by reading data.

The memory access without passing through the common bus 4 has no overhead for acquiring the right to use the common bus, and therefore can operate at a higher speed than the master access and the slave access via the common bus 4.

(Second Embodiment) A bus control apparatus according to a second embodiment will be described with reference to FIG. 4 in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the second embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and the differences will be described here. For master access from a processor (not shown), address conversion is performed by the address conversion circuit 33, and thereafter, the master access is stored in the first first-in first-out memory 41-1. The common bus master interface 35 checks the inside of the first first-in first-out memory 41-1 and performs a master access if the access is stored. Similarly, the own memory access from the processor is stored in the second first-in first-out memory 41-2 after the address decoding is performed by the second address decode circuit 32-2. The arbitration circuit 39 for the memory access includes the second first-in first-out memory 4
It examines 1-2, and if access is stored, performs arbitration processing.

As described above, the access from the processor to its own memory is temporarily made on a first-in first-out memory
-2. In writing to the own memory, write request data is sequentially written to the second first-in first-out memory 41-2. Upon detecting that the data has been written to the second first-in first-out memory 41-2, the arbitration circuit 39 arbitrates between the write request from the processor and the data access request from the common bus slave interface 36, and has a high priority. Side performs memory access. The arbitration and the memory bus access are performed in synchronization with the clock of the common bus 4. Since the second first-in first-out memory 41-2 operates asynchronously, the input side of the second first-in-first-out memory 41-2 does not need to operate in synchronization with the clock of the common bus.

Similarly, the master access from the processor to the common bus 4 is once performed by the first first-in first-out memory 41.
Via -1.

The above two first-in first-out memories 41-
According to 1, 41-2, the clock on the processor bus side and the clock on the common bus side can be supplied completely independently, and there is no need to be synchronized.

(Third Embodiment) A bus control device according to a third embodiment will be described with reference to FIG. 5 in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the second embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and different portions will be described here. That is, in the present embodiment, the internal register 43 is provided in the bus control device 30-2. The internal register 43 is accessed from the common bus 4 and
Access is possible only when the register selection signal becomes true. Via the simultaneous access comparison circuit 42,
It is determined whether a master access from a processor (not shown) is performed and a slave access from the common bus 4 to an internal register is performed simultaneously. If both accesses are made at the same time, the processor interface 31 is notified.

In this embodiment, a structure is provided in which a specific internal register in the bus control device 30-2 can be accessed once via a common bus. That is, FIG. 6 shows the connection relationship between the address input from the common bus 4 and the selection signal. Reserve a specific memory range for accessing internal registers. The address line is 32 bits (A31
~ A0) and the address FFFF0000
Assume that (H) to FFFFFFFF (H) are reserved for internal registers. At this time, the upper 16 bits (A31 to A
16) is necessary for addressing, but the lower 16
The bits (A15 to A0) can be used arbitrarily.

Here, 16 freely usable address lines are connected one by one to the selection signal input of each device. In FIG. 6, A15 is connected to the selection signal input of device 0, A14 is connected to device 1, and so on. Each processor and bus control device 30-2 is assigned any device number. Each processor:
In order to access the internal register, addresses are sequentially scanned so that the connected address line becomes 1.

Next, consider the case where the processor of the device 1 accesses the internal register at the address where A15 becomes 1 = FFFF8000 (H). In the bus control device of the device 1, the register selection signal = A15 = 0
(False) and the internal registers cannot be accessed. Although a master access occurs inside the bus control device 30-2, a slave access to the internal register 43 does not occur. At this time, the simultaneous access comparison circuit 42
Deems that only the master access has become true, and recognizes that the device number (device 1) is not the own device number.

Next, consider the case where the processor of the device 1 accesses the internal register at the address where A14 becomes 1 = FFFF4000 (H). In the bus controller of the device 1, the register selection signal = A14 = 1 (true)
And the internal registers can be accessed. Inside the bus controller, a master access and a slave access to an internal register occur simultaneously. At this time, the simultaneous access comparison circuit 42 considers that both the master access and the slave access have become true, and recognizes that the device number (device 1) is the number of the own device.

As described above, the register is sequentially accessed by the address in which each of the bits A15 to A0 is set to 1, and the result of the simultaneous access comparison circuit 42 is scanned, whereby
It is possible to recognize the identification number (device number) of the own device.

A bus control device according to the fourth embodiment will be described with reference to FIG. 7, in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the fourth embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and different portions will be described here.
That is, in the present embodiment, a plurality of processor interfaces connected to the processor bus 2 are prepared according to the type of the processor. An interface 44 for processor A is provided as a processor interface corresponding to an A-type processor (not shown), and an interface 45 for processor B is provided as a processor interface corresponding to a B-type processor (not shown). The type of processor actually connected to the processor bus is externally input through a processor type selection signal. Based on this selection signal, the multiplexer 46 switches the bus control device 3
The processor interface (44 or 45) connected to the internal circuit 0-3 is selected.

This embodiment is based on the premise that the types of processors connected to the bus control device 30-3 are various. Processor interfaces 44 and 45 corresponding to various different processors are prepared inside the bus control device 30-3. In this case, the pins connected to the processor bus 2 are shared between the processor interfaces. In order to specify the type of the processor connected to the processor bus 2, an external processor type selection signal is provided. By this processor type selection signal, the processor bus 2 of the bus controller 30-3 is actually
The processor 46 selects one of the processor interfaces 44 and 45 corresponding to the processor connected to the bus controller 30-3, and supplies it to the internal circuit of the bus controller 30-3.

(Fifth Embodiment) A bus control device according to a fifth embodiment will be described with reference to FIG. 8 in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the fifth embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and different portions will be described here.

In the present embodiment, the access time timer 47
When the master access from the processor 1 to the common bus 4 starts, the access time timer 47 starts counting time. When a signal indicating that the master access has been completed is received from the common bus master interface 35, the access time timer 47 stops counting time.

However, this access time timer 47
If the timer does not end within a certain period of time after the start of the timer, a reset request is issued to the reset circuit 48. The reset circuit 48 issues a reset request to a circuit related to master access.

More specifically, a reset is issued to the processor interface 31 and the common bus master interface 35 to interrupt the master access and return the state of the bus control device 30-4 to the state before the start of the master access.

In the configuration of the present embodiment, a bus error occurs when a master access from the processor 1 to the common bus 4 occurs. When the master access is performed, the master access start signal to the common master interface 35 by the processor interface 31 becomes true. The access time timer 47 starts counting time in response to the master access start signal. Normally, when the access to the common bus 4 ends normally, a master access end signal becomes true from the common bus master interface 35 to respond. The access time timer 47 stops when this signal becomes true.

However, if the access to the common bus does not end normally, the master access end signal does not become true. If the timer 47 does not stop for a certain period of time when the access time timer is started, it is considered that there is an abnormality in the access to the common bus 4 and a reset request is made to the reset circuit 48.

The reset circuit 48 resets access only to circuits related to master access to the common bus 4. In the configuration shown in FIG. 8, the processor interface 31 and the common bus master interface 35 are reset.

(Sixth Embodiment) A bus control device according to a sixth embodiment will be described with reference to FIG. 9, in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the sixth embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and different portions will be described here.

FIG. 9 shows the processor bus 2 in FIG.
The memory address register 38 specifies an access address to the own memory at the address of the master, the master access register 34 specifies the access address to the common bus at the address of the processor bus 2, and the slave specifies the access address to the own memory at the address of the common bus 4. The three registers of the address register 37 are configured such that slave memories are integrated into an address register 49.

In the bus control device shown in FIG. 9, the following rules are applied.

First, no address conversion is performed (the address on the common bus at the time of master access is left as the processor address).

Second, the values of the slave address register 37 and the memory address register 38 in FIG.

Third, as the value of the master access register 34, a value obtained by masking a part of the address register 49 is used (when the address space for performing the master access to the common bus is 16 MB).
The value obtained by masking 16 MB is used.

This will be described with reference to an example. Bus control device 30-
The address width of the memory bus 12 is 1 MB and the space for the common bus is 16 MB.

Address register is 12400000
In the case of (H), the original value of the memory address register 38 is 12400000 (H) from the above three rules. 12400000 (H) to 1 in processor address
24FFFFFF (H) is an address for the own memory.

Similarly, the original value of the slave address register 37 becomes 12400000 (H), and the address from the common bus 4 to the memory from the address 12400000 (H) to
1 MB up to 124FFFFF (H) is an address for the own memory.

The original value of the master address register 34 is set to the value of the address register by 16 MB (00FFFFFF).
(H)), so that it becomes 12000000 (H). The 16 MB from 12000000 (H) in the processor address becomes a master access to the common bus 4. However, of these addresses, 1 MB from 12400000 (H) is excluded because it is an access address to the own memory, and no bus access actually occurs on the common bus.

As described above, the register addresses 34, 3
By integrating 7, 38 into one access register 49, the bus control device 30-5 can be realized with a clear and simple circuit.

(Seventh Embodiment) A bus control device according to a seventh embodiment will be described with reference to FIG. 10 in which the same parts as those in FIG. The basic configuration and operation of the bus control device according to the seventh embodiment are the same as those of the bus control device according to the first embodiment shown in FIG. 1, and different portions will be described here.

In this embodiment, the memory access to the common bus 4 can be generated from the bus access generation circuit 52 in addition to the master access from the processor (not shown). The bus access generation circuit 52 can access data at an address previously indicated by the transfer counter 18-1. Bus access generation circuit 5
When the access by 2 is completed, the transfer counter 51 is incremented by one. The data read and written by the bus access generation circuit 52 are stored in the buffer memory 5.
0 is stored.

The data in the buffer memory 50 can access the memory bus 12 through the first arbitration circuit 39-1. Since the access to the memory bus 12 may occur at the same time as three types of access: the own memory access from the processor, the slave access from the common bus 4 and the access from the bus access generation circuit 52 via the buffer memory 50, One arbitration circuit 39-1 has three inputs. The master access to the common bus 4 is performed by a bus access generation circuit 52 in addition to the master access from the processor.
Therefore, the priority determination is performed using the second arbitration circuit 39-2 because there is a possibility that the master access by the arbitration will occur at the same time.

In the bus control device 30-6 of this embodiment,
In addition to the master access from the normal processor, a bus access generation circuit 52 built in the bus control device 30-6
And the like, the transfer between the common bus 4 and the memory can be automatically performed independently of the processor.

An example of the operation when the transfer function is enabled will be described. The bus access generation circuit 52 accesses the address indicated by the transfer counter 51 to the common bus 4.
In the case of transfer from the common bus 4 to the memory, the common bus 4
Is read. The access to the common bus 4 is arbitrated by the second arbitration circuit 39-2 because the access from the bus access circuit 52 and the access from the processor may occur simultaneously.

Access from the bus access circuit 52 is made to the common bus 4, and when data is read via the common bus 4, the data is stored in the buffer memory 50. Once the data stored in the buffer memory 50 is
Although it is possible to write to its own memory, buffer memory 5
In addition to the access from 0, the memory access may be performed via the first arbitration circuit 39-1 because the own memory access from the processor and the slave access from the common bus 4 may occur simultaneously. .

Since the transfer counter 51 is incremented by one at the time when the data is stored in the buffer memory 50, the access to the next common bus 4 can be started. Can be performed simultaneously, and high-performance data transfer can be realized.

[0082]

According to the first aspect of the present invention, a memory connected to a common bus by a plurality of bus control devices is provided.
Data transfer between processors can be realized by performing only one data transfer on the common bus. In addition, since concentrated memory resources are not arranged unlike the shared memory system, even if one memory fails, all data transfer is not disabled, and data transfer with high fault tolerance can be realized. In addition, by distributing the memory, the contrast and independence between the plurality of processors connected by the bus control device can be improved.

According to the second aspect of the present invention, by using a first-in first-out memory internally, the bus controller may operate even if the clock of the processor bus and the clock of the common bus are independent (asynchronously). As a result, there is no need for an external circuit for multiplying the clock from the processor bus, and advantages in cost and mounting are obtained. Further, since the clock of the processor bus can be freely selected, the selection range of the processors that can be connected to the bus control device is widened, and the system can have flexibility.

According to the third aspect of the present invention, the device number of the processor can be recognized without requiring a dedicated identification number input circuit from the outside, so that there are advantages in cost and mounting. In addition, since the bus controller can be connected to the common bus without increasing the number of terminals, the bus controller can be downsized.

According to the fourth aspect of the present invention, the processor can be connected to the processor bus without using a dedicated bus control device for the processor and without requiring an external circuit for connecting the processor. Cost and mounting benefits are improved.

According to the fifth aspect of the present invention, since the detection of an abnormality in access to the common bus can be realized without requiring an external circuit, the cost and mounting advantages are improved.
Further, since only the circuits that need to be reset when an error occurs are performed, it is not necessary to initialize the bus control device from the beginning, and simplification of software for processing when an error occurs can be realized.

According to the sixth aspect of the present invention, since the access register is integrated into one, the circuit of the bus control device is simplified, and the cost and mounting advantages are improved. In addition, since a malfunction due to an address setting error hardly occurs, simplification of software for setting an address register and improvement in system reliability can be realized.

According to the seventh aspect of the present invention, the DMA
The cost and the merit in mounting which can realize the data transfer of the memory between the bus control devices without mounting the circuit are improved. In addition, since one-unit transfer is completed by one common bus transfer as compared with the mounting of the external DMA circuit, high-efficiency and high-speed data transfer can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of a bus control device according to a first embodiment of the present invention.

FIG. 2 is an exemplary diagram showing an example of a basic operation of the bus control device according to the first embodiment;

FIG. 3 is an exemplary diagram showing a system operation example of the bus control device according to the embodiment;

FIG. 4 is a diagram showing an internal configuration of a bus control device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an internal configuration of a bus control device according to a third embodiment of the present invention.

FIG. 6 is an exemplary view showing an address input method and a selection signal input method for identification number recognition in the embodiment.

FIG. 7 is a diagram showing an internal configuration of a bus control device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing an internal configuration of a bus control device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram illustrating an internal configuration of a bus control device according to a sixth embodiment of the present invention.

FIG. 10 is a diagram showing an internal configuration of a bus control device according to a seventh embodiment of the present invention.

FIG. 11 is a diagram showing a configuration example of a connection between a plurality of processors according to a conventional shared memory system.

FIG. 12 is a diagram showing a configuration example according to a conventional clock synchronization method.

FIG. 13 is a diagram showing a conventional identification number generation method.

FIG. 14 is a diagram showing a configuration example of a processor interface using a dedicated interface in the related art.

FIG. 15 is a diagram showing a configuration example of a processor interface using a conventional general-purpose interface.

FIG. 16 is a diagram showing an example of a conventional timeout detection circuit.

FIG. 17 is a diagram showing an example of a conventional configuration for address register separation.

FIG. 18 is a diagram showing an example of a conventional external DMA system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Processor bus 4 ... Common bus 30, 30-1, 30-2, 30-3, 30-4, 30
-5, 30-6-Bus control device 31-Processor interface 32-1, 32-1-Address decode circuit 33-Address conversion circuit 34-Master address register 35-Common bus master interface 36-Common bus slave interface 37-Slave address Register 38: Memory address register 39: Arbitration circuit 40: Memory bus interface.

Claims (7)

[Claims] 1. A system having a plurality of bus controllers, the bus controller comprising: a processor bus for connecting a processor; a memory bus for connecting a memory;
A common bus connecting the plurality of processors to each other, and when the plurality of processors are connected via the common bus, each of the processors shares a space of the memory connected to a memory bus of the bus control device. And a means for: 2. The bus controller according to claim 1, further comprising a first-in first-out memory circuit for executing an access request to the memory from the processor and an asynchronous master access request to the common bus. The system of claim 1. 3. The bus control device further comprises means for executing external access from the processor via the common bus and internal access from the processor via no common bus. The system of claim 1, wherein the system comprises: 4. The system of claim 1, wherein said bus controller further comprises a plurality of processor interfaces and a multiplexer. 5. The bus control device includes an internal timer, an internal state transition circuit, and a response circuit to a processor.
The system of claim 1, wherein said response circuit comprises means for resetting said internal timer and said internal state transition circuit. 6. The bus control device has a register function of designating a space address of its own memory area accessed by the processor, and designates a memory space address under another bus control device via its own bus control device. 2. The system according to claim 1, further comprising one register having a register function and a register function of designating a memory space address accessed from another bus control device to its own memory space. 7. The system according to claim 1, wherein said bus control device further comprises a data transfer unit.