JP2001015584A - High breakdown voltage semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a high breakdown voltage semiconductor device in which a breakdown voltage holding structure occupies a small area and reliability can be improved. SOLUTION: This semiconductor device is provided with a semiconductor substrate 302 of which one surface is used as a first main surface of the semiconductor substrate, and a semiconductor substrate 304 formed under the semiconductor substrate 302, of which one surface is used as a second main surface of the semiconductor substrate. An active region is formed on the first main surface 301 side. A V-groove 309 coated by an oxide film 307 and a polycrystal silicon film 308 is formed outside the active region so as to reach from the first main surface 301 to the semiconductor substrate 304.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high breakdown voltage semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art Hitherto, as a breakdown voltage holding structure of a high breakdown voltage semiconductor device, there are a guard ring structure shown in FIG. 7 and a mesa structure shown in FIG. In the case of the guard ring structure shown in FIG. 7, the surface of the PN junction is covered with a thermal oxide film 701, which is excellent in reliability and the manufacturing process is simple. Ring 70
It is necessary to increase the number of the two, and as a result, there is a disadvantage that the area occupied by the guard ring 702 as the breakdown voltage holding structure in the semiconductor element increases, and the semiconductor element increases.

Further, since the PN junction of the guard ring structure is formed by an impurity diffusion process from the surface of the semiconductor substrate, the diffusion layer partially has an interface having a small curvature, and the electric field concentration is increased in that region. This causes a problem that the breakdown voltage is lower than that of a flat PN junction. Further, it is necessary to form the N-type semiconductor region 3 around the semiconductor element so that the depletion layer does not extend to the end face of the semiconductor element.

On the other hand, in the case of the mesa structure shown in FIG. 8, the PN junction surface on the side surface of the semiconductor element is flattened by a chemical or mechanical flattening process (etching or polishing), so that a higher breakdown voltage is realized. it can. In addition, there is an advantage that the area occupied by the breakdown voltage holding structure can be smaller than that of the guard ring structure. However, in this mesa structure,
There is a problem that the side surface of the semiconductor element cannot be covered with the thermal oxide film, and the reliability is reduced.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a high withstand voltage structure in which the occupied area of a withstand voltage holding structure is small and reliability can be improved. An object of the present invention is to provide a structure of a semiconductor device and a manufacturing method thereof.

[0006]

According to a first aspect of the present invention, there is provided a high withstand voltage semiconductor device, wherein a first surface of a relatively low concentration first first conductivity type semiconductor substrate has one surface serving as a first main surface of the semiconductor substrate; A relatively high concentration second layer formed under the first conductivity type semiconductor substrate and having one surface serving as a second main surface of the semiconductor substrate.
A high withstand voltage semiconductor device comprising: a first conductivity type semiconductor substrate; and an active region formed on the first main surface side.
A V-groove covered with an oxide film and a polycrystalline silicon film outside the active region is formed from the first main surface to the second groove.
Is formed so as to reach the region of the first conductivity type semiconductor substrate. The high breakdown voltage semiconductor device according to claim 2 is the high breakdown voltage semiconductor device according to claim 1, wherein a second conductivity type semiconductor region is formed inside the V groove formed outside the active region. It is characterized in that it is formed so as to contact.

A high breakdown voltage semiconductor device according to a third aspect of the present invention is the high breakdown voltage semiconductor device according to the second aspect, wherein the polycrystalline silicon film covering the V groove and the semiconductor region of the second conductivity type are electrically connected. It is characterized by having.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a high withstand voltage semiconductor device, comprising the steps of: forming a V-groove in a semiconductor substrate; forming a thermal oxide film on the surface of the V-groove; A step of depositing crystalline silicon, a step of polishing the V groove, and a step of diffusing impurities for forming a second conductivity type semiconductor region in contact with the V groove and an active region in the semiconductor substrate. It is characterized by the following.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the high breakdown voltage semiconductor device according to the present invention will be described below with reference to the sectional view of FIG. A semiconductor substrate 302 having one surface serving as a first main surface 301 of the semiconductor substrate is a relatively low-concentration N-type semiconductor region, and one surface thereof serves as a second main surface 303 of the semiconductor substrate.
A semiconductor substrate 304, which is a relatively high-concentration N-type semiconductor region, is formed below the semiconductor substrate 302.

N-type semiconductor substrate 30 on first main surface 301 side
In the region 2, a P-type semiconductor region 305 and an N-type semiconductor region 306 are formed to constitute an NPN transistor. Outside the region where the NPN transistor is formed, the V-groove 3 covered with an oxide film 307 and filled with a polycrystalline silicon film 308 is formed.
09 is formed so as to reach the semiconductor substrate 304 which is an N-type semiconductor region from the first main surface 301.

In the conventional guard ring structure shown in FIG. 7, since the depletion layer extends in the horizontal direction with respect to the surface of the semiconductor substrate, the width of the guard ring region is required to be about 300 μm in a high breakdown voltage semiconductor device of about 500 V. In addition, it was necessary to form an N-type semiconductor region around the semiconductor element so that the depletion layer did not extend to the end face of the semiconductor element.
In the high breakdown voltage semiconductor device shown in FIG. 1, when the depletion layer extending from the P-type semiconductor region 305 reaches the V-shaped groove 309, the depletion layer thereafter extends in a direction perpendicular to the surface of the semiconductor substrate. By providing the V-shaped groove 309 having a width, a high withstand voltage semiconductor device can be realized.

A V-groove 309 is formed so as to reach the semiconductor substrate 304 which is a high-concentration N-type semiconductor region, and a depletion layer extending from the P-type semiconductor region 305 extends outward from an end face of the semiconductor element. Figure 7
It is not necessary to form an N-type semiconductor region around a semiconductor element as in the case of the conventional guard ring structure shown in FIG.

Next, another embodiment of the high breakdown voltage semiconductor device according to the present invention will be described with reference to the sectional view of FIG.
A semiconductor substrate 402 having one surface serving as a first main surface 401 of the semiconductor substrate is a relatively low-concentration N-type semiconductor region, and one surface thereof serves as a second main surface 403 of the semiconductor substrate. Semiconductor substrate 4 which is a high-concentration N-type semiconductor region
04 is formed below the semiconductor substrate 402.

N-type semiconductor region 40 on first main surface 401 side
2 includes a P-type semiconductor region 405 and an N-type semiconductor region 40.
6 to form an NPN transistor. Outside the region where the NPN transistor is formed, a V-groove 409 whose surface is covered with an oxide film 407 and filled with a polycrystalline silicon film 408 extends from the first main surface 401 to the N-type semiconductor region 404. Is formed to reach.

In the high-breakdown-voltage semiconductor device shown in FIG. 2, the P-type semiconductor region 405 is configured so as to be in contact with the side wall of the V-shaped groove 409, so that an interface having a small curvature is not formed. As a result, electric field concentration is less likely to occur in this region, and a higher breakdown voltage can be achieved.

In the embodiment shown in FIG.
The P-type semiconductor region 405 in contact with the side wall of the transistor 09 is a P-type base region of an NPN transistor which is an active region. As shown in FIG.
10 may be configured to be in contact with the side wall of the V groove 409.

Next, a further different high withstand voltage semiconductor device of the present invention will be described with reference to FIG. A semiconductor substrate 602 having one surface serving as a first main surface 601 of the semiconductor substrate
Is a relatively low-concentration N-type semiconductor region, one surface of which is a second main surface 603 of the semiconductor substrate. Is formed.

N-type semiconductor substrate 60 on first main surface 601 side
In the region 2, a P-type semiconductor region 605 and an N-type semiconductor region 606 are formed, and constitute an NPN transistor. Outside the NPN transistor, a V groove 609 whose surface is covered with an oxide film 607 and filled with a polycrystalline silicon film 608 has a first main surface 6.
It is formed so as to reach the semiconductor substrate 604 which is an N-type semiconductor region from 01. Further, the P-type semiconductor region 605
Are configured to be in contact with the side walls of the V-groove 609, so that a portion having a small curvature is not formed in the P-type diffusion region.

Further, the polycrystalline silicon film 608 covering the V-groove 609 and the P-type semiconductor region 605 are
0 is electrically connected. As a result, in the region of the P-type semiconductor region 605 that is in contact with the side wall of the V-groove 609, the depletion layer is easily extended, and the electric field concentration in this region is further reduced. In the embodiment shown in FIG. 4, the P-type semiconductor region 6 in contact with the side wall of the V-groove 609 is formed.
Reference numeral 05 denotes a P-type base region of the NPN transistor which is an active region. As shown in FIG.
The polycrystalline silicon film 608 filling the V-groove 609 and the P-type diffusion layer
May be configured to be electrically connected.

Further, a method of manufacturing an NPN transistor will be described as a method of manufacturing a high breakdown voltage semiconductor device according to the present invention with reference to FIG. A semiconductor substrate having a relatively low-concentration N-type semiconductor region 802 on the first main surface 801 side and a relatively high-concentration N-type semiconductor region 804 on the second main surface side, as shown in FIG. The first main surface 8
01 is patterned, and a V groove 809 is formed by chemical etching using KOH or the like.

Next, as shown in FIG. 2B, an oxide film 807 is formed on the surface of the semiconductor substrate including the region where the V-groove 809 is formed.
Is formed, and a layer of a polycrystalline silicon film 808 is formed to fill the V groove 809 as shown in FIG. afterwards,
As shown in (d), the semiconductor substrate surface 801 is polished using a mechanical method so as to be flat.

Thereafter, as shown in FIG.
A P-type diffusion layer 805 serving as an active region is formed in the N-type semiconductor region 802 between the grooves 809 so as to be in contact with the side wall of the V-groove 609. Further, as shown in FIG.
An N-type diffusion layer 806 is formed in the region of No. 5. Finally,
As shown in (g), contact holes for connecting electrodes to the respective diffusion regions and the polycrystalline silicon film 808 were opened, and as shown in (h), they were formed so as to be in contact with the V-grooves 809. P-type diffusion layer 805 and polycrystalline silicon film 80
8 are connected by an electrode 810.

In the manufacturing method shown in FIG. 6, a V-groove is formed, the V-groove is covered with an oxide film and a polycrystalline silicon film, and the semiconductor surface is planarized. By performing fine processing using a semiconductor device manufacturing apparatus to be manufactured, a high-performance semiconductor element can be manufactured.

In each embodiment of the present invention, the high withstand voltage N
Although the description has been given of the case of the PN transistor, the present invention is not limited to this. In a MOSFET, an IGBT, a thyristor, a diode, or the like, a current flows in the vertical direction (vertical direction) with respect to the surface of the semiconductor substrate, and high withstand voltage performance is required. Applicable to semiconductor devices.

[0025]

According to the high breakdown voltage semiconductor device of the first aspect, the V-groove is formed outside the active region of the semiconductor element and in contact with the diffusion layer holding the breakdown voltage, so that the reliability is reduced in a small area. A high high withstand voltage structure can be realized.

According to the high withstand voltage semiconductor device of the second or third aspect, the polycrystalline silicon film covering the V-groove is electrically connected to the diffusion layer for maintaining the withstand voltage. Electric field concentration on the side wall of the V-groove can be reduced, and a higher breakdown voltage can be achieved.

According to the method of manufacturing a high withstand voltage semiconductor device according to the fourth aspect of the present invention, the active region can be formed after the V-groove is formed. Can be processed. As a result, a high-performance semiconductor can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of an embodiment of a high breakdown voltage semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing the structure of another embodiment of the high breakdown voltage semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing the structure of still another embodiment of the high breakdown voltage semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing the structure of still another embodiment of the high breakdown voltage semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a structure of still another embodiment of the high breakdown voltage semiconductor device of the present invention.

FIG. 6 is a sectional view showing one embodiment of a method for manufacturing a high breakdown voltage semiconductor device of the present invention.

FIG. 7 is a sectional view showing an example of a conventional high breakdown voltage semiconductor device.

FIG. 8 is a sectional view showing a different example of the conventional high breakdown voltage semiconductor device.

[Explanation of symbols]

301 first main surface 302 semiconductor substrate (first low concentration first
Semiconductor substrate (conductivity type) 303 Second main surface 304 Semiconductor substrate (Second first substrate having relatively high concentration)
(Conductive semiconductor substrate) 307 oxide film 308 polycrystalline silicon film 309 V groove

Continuing on the front page (72) Inventor Noriyuki Furumoto 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. ) 5F032 AA40 AA45 AA47 CA24

Claims (4)

[Claims] A first semiconductor substrate having a relatively low concentration, one surface of which is a first main surface of the semiconductor substrate; and a first conductive semiconductor substrate formed under the first conductive semiconductor substrate. Surface becomes the second main surface of the semiconductor substrate.
A high withstand voltage semiconductor device comprising: a first conductivity type semiconductor substrate; and an active region formed on the first main surface side.
A V-groove covered with an oxide film and a polycrystalline silicon film outside the active region is formed from the first main surface to the second groove.
A high-breakdown-voltage semiconductor device formed so as to reach a region of the first conductivity type semiconductor substrate. 2. The semiconductor device according to claim 1, wherein said V is formed outside said active region.
2. The high breakdown voltage semiconductor device according to claim 1, wherein a semiconductor region of the second conductivity type is formed inside the groove so as to contact the V groove. 3. The high breakdown voltage semiconductor device according to claim 2, wherein a polycrystalline silicon film covering said V-groove and said second conductivity type semiconductor region are electrically connected. 4. A step of forming a V-groove in a semiconductor substrate, a step of forming a thermal oxide film on a surface of the V-groove, a step of depositing polycrystalline silicon on the thermal oxide film, A method for manufacturing a high breakdown voltage semiconductor device, comprising: a polishing step for planarizing; and an impurity diffusion step for forming a second conductivity type semiconductor region in contact with the V groove and an active region in the semiconductor substrate. .