JP2001014810A - Magnetic reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a PLL(Phase Locked Loop) circuit from being inconvenienced due to instability of operation caused by variation in a relative speed between a rotary head and a magnetic tape in search modes like a normal reproducing mode and a 12 times or 18 times speed mode. SOLUTION: This magnetic reproducing device alters an offset voltage for altering a center level of a lock range of a PLL circuit 6, and also alters an error voltage value for altering a clock frequency of the PLL circuit 6 according to the running direction of the reproducing head of a rotary head for reproducing the information and the magnetic tape. Thus, even though there is variation in the relative speed between the rotary head 1 and the magnetic tape, it is possible to operate the PLL circuit 6 according to this variation, and accurately reproduce the information signals recorded on the magnetic tape based on the clock stably formed by the PLL circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to, for example, D-VHS
A magnetic recording / reproducing apparatus suitable for use in a magnetic recording / reproducing apparatus for recording / reproducing information signals based on the (registered trademark) system
In particular, the present invention relates to a magnetic reproducing apparatus capable of reproducing information in an information search at an accurate timing.

[0002]

2. Description of the Related Art A D-VHS magnetic recording / reproducing apparatus for digitally recording an information signal on a magnetic tape based on a D-VHS recording format has been known. When recording an information signal, the magnetic recording / reproducing apparatus performs A / D conversion processing on the information signal to be recorded, digitizes the information signal, and performs predetermined information processing such as data compression processing and addition of an error correction code. After the processing, the recording and reproducing heads are provided to two recording and reproducing heads A and B provided opposite to each other as shown in FIG.

[Recording operation] At the time of this recording, the rotation of the rotary drum 100 is controlled to a rotation speed of, for example, 30 Hz, and the running speed of the magnetic tape is a standard speed defined as a standard mode, for example, 16.67 mm / sec.
The traveling speed is controlled to the traveling speed of c. Then, as shown in FIG. 3, the recording track A is formed by the recording / reproducing head A by alternately tracing the magnetic tape 101 by the recording / reproducing heads A and B provided on the rotating drum 100. Recording / reproducing head B adjacent to track A
, The operation of forming the recording track B is repeated, and the information signal is recorded on the magnetic tape 101.

[Reproduction Operation] Next, the information signal recorded on the magnetic tape 101 as described above is reproduced by a reproduction system as shown in FIG. That is, each time the rotary drum 100 rotates 180 degrees, a drum flip-flop signal, which is a high-level and low-level repetition signal as shown in FIG. 5A, is formed. The reproducing heads A and B rotate the rotating drum 100 based on the drum flip-flop signal.
Is turned on / off each time the .phi. Rotates 180 degrees, and traces on the magnetic tape 101 alternately. As a result, FIG.
As shown in (b) and (c), each of the recording tracks A and B
Are alternately reproduced by the recording / reproducing heads A and B, respectively, and supplied to the A / D converter 103 via the preamplifier 102 as a reproduced output as shown in FIG.

The A / D converter 103 operates based on the clock from the variable voltage oscillator 107 (VCO), thereby digitizing the information signals analog-reproduced by the recording / reproducing heads A and B, This is a 1 + D circuit 10
4 The 1 + D circuit 104 performs, for example, a delay of one clock on the information signal from the A / D converter 103 based on the clock from the VCO 107, and adds the current information signal to the delayed information signal. After the noise of the information signal is reduced, the high frequency band is demodulated and supplied to an error correction circuit 105 (ECC circuit).

The ECC circuit 105 performs an error correction process on the information signal from the 1 + D circuit 104 based on the clock from the VCO 107, and supplies the information signal to a television receiver or the like. Thereby, a video output and an audio output corresponding to the information signal reproduced from the magnetic tape 101 can be obtained via the television receiver or the like.

[Clock forming operation] Here, the VCO
107 is a so-called PLL (Phase Lockcd).
Based on the Loop control technique, a clock is formed and the A / D converter 103 and the ECC circuit 10 are formed as described below.
5 and so on.

That is, the information signal digitized by the A / D converter 103 is supplied to a 1 + D circuit 104 and a phase detection circuit 106 (Phase DET)
Are also supplied. Phase detection circuit 106
Is supplied with a clock currently formed by the VCO 107, and the phase detection circuit 106 compares the phase of the information signal from the A / D converter 103 with the phase of the current clock from the VCO 107. To detect the phase error between the two, and outputs this phase error detection output to the adder 112.
To supply.

The adder 112 has an offset voltage source 14
, An offset output indicating a predetermined DC voltage value is supplied. This offset output prevents an inconvenience that the center level of the lock range of the PLL control fluctuates due to variations in characteristics (variations in gain and offset) of each analog component such as the amplifier 110, the low-pass filter 111 (LPF), and the VCO 107. It is for. The voltage value of the offset output is adjusted at the time of reproducing the information signal so that the center level becomes a predetermined optimum value.

The adder 112 adds the offset output to the phase error detection output from the phase detection circuit 106 to correct the center level fluctuation of the lock range, and corrects the change by the amplifier 110, LPF 111 and The signal is supplied to the VCO 107 via the adder 113.

The VCO 107 forms a clock having a phase corresponding to the phase error detection output, and outputs the clock to the A / D converter 1.
03, to the error correction circuit 105 and the like. Thereby, the A / D converter 103, the error correction circuit 105, etc.
The information signals reproduced by the recording / reproducing heads A and B can be driven at timings corresponding to the phases of the information signals, and the information processing can be performed on the information signals at optimal timing.

[Operation of Discriminator] In the conventional magnetic recording / reproducing apparatus, each recording / reproducing head A is controlled by PLL control in which the VCO 107 is driven to oscillate based on the phase error detected by the phase detecting circuit 106. , B
A clock having a timing according to the phase of the information signal reproduced by the VCO 107 is formed. If the phase of the clock formed by the VCO 107 deviates from the lock range of the PLL circuit for some reason, Phase needs to be redrawn. Discriminator 108 (disc
A riminator (frequency discriminator) is provided in order to shorten the phase pull-in time.

Specifically, the discriminator 108
Is configured as shown in FIG. 6, the clock from the VCO 107 is frequency-divided by the frequency divider 125 to, for example, a 1/100 clock, and the frequency-divided clock is supplied to the counter 117 as a reset pulse. The oscillator 109 (crystal oscillator: XO) oscillates a reference clock having a frequency inherent in the information signal recorded on the magnetic tape 101, and outputs the reference clock to a counter 117.
To supply.

The counter 117 divides the clock by the frequency divider 12
The count value is reset at the timing when the frequency-divided clock from 5 is supplied, the counting of the reference clock from the oscillator 109 is started, and the count value of the reference clock counted before the next reset is applied to the comparator. 11
5

Here, in this case, the frequency divider 125
Since the clock from O107 is divided by 100, if the clock formed by this VCO 107 has the correct frequency, the counter 117 should count the clock from the oscillator 109 by 100 before the reset is applied. It is. However, when the frequency of the clock formed by the VCO 107 is high, the count value of the counter 117 is reset earlier than usual, and the count value output from the counter 117 is smaller than 100. . Conversely, VCO10
When the frequency of the clock formed by 7 is low, the count value of the counter 117 is reset later than usual, and the count value output from the counter 117 becomes a value larger than 100.

The comparison count value from comparison count value generating section 126 is a value indicating what percentage of the frequency error of the clock formed by VCO 107 is to be an error, for example, an error is caused by a frequency error of -1%. In the case, "10
The comparison count value of “1” is supplied from the comparison count value generator 126 to the comparator 115.

The comparator 115 compares the count value from the counter 117 with the comparison count value from the comparison count value generator 126, and outputs an error (error voltage) corresponding to the comparison result. To supply. In this case, the comparator 115 includes the comparison count value generator 12
Since the comparison count value of “101” is supplied from the counter 6, when the count value from the counter 117 becomes 101 or more, the comparator 115 forms an error output corresponding to the difference between the two and outputs the error output. To the vessel 113.

The adder 113 shown in FIG.
2. A phase error detection output from the phase comparator 106 supplied via the amplifier 110 and the LPF 111 is added to an error output from the comparator 115, and the VCO 107 is oscillated based on the added output. This allows
A clock having an accurate phase and a frequency corresponding to the information signal reproduced by the recording / reproducing heads A and B can be formed by the VCO 107.
Accurate information processing can be performed by the / D converter 103, the 1 + D circuit 104, and the like.

[0019]

Here, conventionally, a desired information signal recorded on a magnetic tape is searched by performing reproduction while running the magnetic tape at a high speed.
Although a so-called search is known, in the above-described D-VHS magnetic recording / reproducing apparatus, even when this search is performed, the rotation speed of the rotating drum 100 is reduced to a normal rotation speed of, for example, 30 Hz. Fixed. That is, the rotating drum 10 corresponds to the running speed of the magnetic tape.
No relative speed correction such as changing the rotation speed of 0 is performed. Therefore, the relative speed between the rotating drum 100 and the magnetic tape 101 differs depending on the search speed.
Further, when the traveling of the magnetic tape 101 is controlled in the forward direction and when the traveling of the magnetic tape 101 is controlled in the reverse direction, the difference is also caused by the difference in the azimuth angle of the recording / reproducing heads A and B provided on the rotating drum 100. Occurs.

However, the conventional magnetic recording / reproducing apparatus uses PL
Since the lock range of the L circuit, the voltage value of the offset voltage source 14 and the error detection range of the discriminator 8 are set to a predetermined predetermined fixed range or fixed value, such a difference in relative speed may be reduced. If this occurs, the operation of the PLL circuit becomes unstable.

For example, when a search is performed by controlling the running of the magnetic tape 101 in the reverse direction at 12 × speed, the frequency of the information signal to be reproduced increases by nearly + 5%, so that the PLL circuit may follow this frequency fluctuation. As a result, phase lock is lost, and there is a problem that all reproduced information signals become errors.

In consideration of such a frequency variation,
It is conceivable that the lock range of the PLL circuit, the error detection range of the discriminator 8 and the like are set to a wider range in advance, but this results in mislocking and unstable operation of the PLL circuit, which is preferable. is not.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to operate a PLL circuit stably to accurately reproduce an information signal even when the relative speed of a rotating drum and a magnetic tape fluctuates. It is an object of the present invention to provide a magnetic reproducing apparatus capable of performing the above.

[0024]

According to a first aspect of the present invention, there is provided a magnetic reproducing apparatus, comprising: a rotating head for reproducing information obliquely recorded on a tape-shaped magnetic recording medium; Information processing means for performing predetermined information processing on information reproduced from a tape-shaped magnetic recording medium by the rotary head and restoring the information; clock forming means for forming an operation clock of the information processing means; Speed control means for controlling the running speed of the tape-shaped magnetic recording medium, and the relative speed between the rotary head and the tape-shaped magnetic recording medium, which is changed by controlling the running speed of the tape-shaped magnetic recording medium by the running speed control means. Clock forming operation control means for controlling the clock forming operation of the clock forming means in accordance with the speed.

In the magnetic reproducing apparatus according to the first aspect of the present invention, the clock forming operation control means changes the rotation speed by controlling the traveling speed of the tape-shaped magnetic recording medium by the traveling speed control means. The clock forming operation of the clock forming means is controlled in accordance with the relative speed between the head and the tape-shaped magnetic recording medium. Thereby, the clock forming means can be operated stably in accordance with the relative speed between the rotary head and the tape-shaped magnetic recording medium. Then, based on the clock formed by the clock forming means, the information processing means can perform information processing on information reproduced by the rotary head at accurate and optimal timing.

According to a second aspect of the present invention, there is provided a magnetic reproducing apparatus including, as means for solving the above-described problems, the rotating head having first and second reproducing heads arranged opposite to each other; And the clock forming operation control means for controlling the clock forming operation of the clock forming means corresponding to the first and second reproducing heads which have reproduced the information.

In the magnetic reproducing apparatus according to the present invention, the clock forming operation control means controls the clock forming operation of the clock forming means in accordance with the relative speed between the rotary head and the tape-shaped magnetic recording medium. In addition to controlling, the clock forming operation of the clock forming means is controlled corresponding to the first and second reproducing heads that have reproduced the information. Thereby, the clock forming operation of the clock forming means can be controlled for each reproducing head for reproducing information, and the clock forming means can be operated more stably, and the information processing can be performed at accurate and optimal timing. Can be applied.

According to a third aspect of the present invention, there is provided a magnetic reproducing apparatus according to the present invention, wherein the traveling speed of the tape-shaped magnetic recording medium is controlled by the traveling speed control means. And a clock forming operation control unit that controls a clock forming operation of the clock forming unit.

In the magnetic reproducing apparatus according to the third aspect of the present invention, the clock forming operation control means controls the clock forming operation of the clock forming means according to the relative speed between the rotary head and the tape-shaped magnetic recording medium. In addition to controlling, the clock forming operation of the clock forming means is controlled in accordance with the running direction of the tape-shaped magnetic recording medium. This makes it possible to control the clock forming operation of the clock forming unit even in accordance with the running direction of the tape-shaped magnetic recording medium, to operate the clock forming unit more stably, and to obtain information at accurate and optimal timing. Processing can be performed.

Alternatively, in the magnetic reproducing apparatus according to the third aspect of the present invention, the clock forming operation control means may include:
The clock forming operation of the clock forming means is controlled in accordance with the relative speed between the rotating head and the tape-shaped magnetic recording medium, and the clock forming operation is performed in correspondence with the first and second reproducing heads which have reproduced the information. In addition to controlling the clock forming operation of the means, further controlling the clock forming operation of the clock forming means according to the running direction of the tape-shaped magnetic recording medium.

Thus, the relative speed between the rotating head and the tape-shaped magnetic recording medium, and the first speed at which the information was reproduced.
In addition, it is possible to control the clock forming operation of the clock forming means even in accordance with the running direction of the second reproducing head and the tape-shaped magnetic recording medium, and to operate the clock forming means more stably, accurately and accurately. It is possible to perform information processing at optimal timing.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Structure of Embodiment] [Overall Structure] A magnetic reproducing apparatus according to the present invention employs a D-VHS
Information signal (video signal, audio signal, etc.)
The present invention can be applied to a magnetic reproducing apparatus that reproduces the data. FIG. 1 is a block diagram of a main part of a magnetic reproducing apparatus according to an embodiment of the present invention. As can be seen from FIG.
In the magnetic reproducing apparatus of the present embodiment, two reproducing heads A and B having different azimuth angles are respectively arranged to face each other, and the recording tracks of the information signal formed on the magnetic tape by these reproducing heads are traced. And a preamplifier 2 for amplifying the information signal reproduced by the rotary head 1 with a predetermined gain and outputting the amplified information signal.

Further, the magnetic reproducing apparatus has a preamplifier 2
An A / D converter 3 for digitizing and outputting an information signal supplied through the A / D converter, a 1 + D circuit 4 for subjecting the information signal digitized by the A / D converter 3 to high-frequency demodulation processing and the like,
An error correction circuit 5 that performs error correction processing on the information signal from the 1 + D circuit 4 and supplies the information signal to, for example, a television receiver.
(ECC circuit) and a P which forms a clock serving as an operation reference of the A / D converter 3, the 1 + D circuit 4, the ECC circuit 5, and the like.
And an LL circuit 6.

[Configuration of PLL circuit 6]
A voltage variable oscillator 7 for forming a clock which is used as an operation reference for the A / D converter 3, the 1 + D circuit 4, the ECC circuit 5, etc.
(VCO), an information signal from the A / D converter 3, and V
A phase detection circuit 8 for detecting a phase error of a clock formed by CO7, an amplifier 10, and a low-pass filter 11 (L
PF), the PLL due to variations in characteristics (variations in gain and offset) of analog components such as VCO 7
Center level of lock range of circuit 6 (DC level)
And an offset voltage generator 9 for generating an offset voltage for correcting the fluctuation of the offset voltage.

The PLL circuit 6 adds the offset voltage from the offset voltage generator 9 to the phase error detection output from the phase detection circuit 8 to adjust the DC level of the phase error detection output. 12, an amplifier 10 for amplifying the phase error detection output from the adder 12 with a predetermined gain and outputting the same, and a low-pass filter 11 (LPF) for performing a predetermined filtering process on the phase error detection output from the amplifier 10 and outputting the result. And

The PLL circuit 6 has a discriminator 14 (frequency discriminator) for forming an error signal for correcting the frequency of a clock formed by the VCO 7.
And by adding an error signal from the discriminator 14 to the phase error detection output from the LPF 11,
And an adder 13 for forming an addition output for correcting the phase and frequency of the clock formed by the CO 7 and supplying the added output to the VCO 7.

[Structure of Offset Voltage Generating Unit 9] The offset voltage generating unit 9 provided in the PLL circuit 6 of the magnetic reproducing apparatus includes a plurality of offset voltage sources 3 having different values.
0 to 33 and a changeover switch 29 for switching between these and supplying the same to the adder 12.

In the magnetic reproducing apparatus, for example, in addition to the normal reproduction mode, search modes of a 12 × speed forward search, a 12 × speed reverse search, an 18 × speed forward search, and an 18 × speed reverse search are provided. Although provided, the fluctuation of the center level of the lock range of the PLL circuit 6 differs in the normal reproduction mode, the 12 × speed search mode, and the 18 × speed search mode.

The fluctuation of the center level differs between the same 12-times speed search mode and the forward 12-times speed search mode and the reverse 12-times speed search mode. Further, even in the same forward 12 × speed search mode, each of the reproducing heads A and B is different, and even in the same reverse 12 × speed search mode, each of the reproducing heads A and B is different.
B differs for each.

Similarly, the fluctuation of the center level is different between the same 18 × speed search mode, the 18 × speed search mode in the forward direction and the 18 × speed search mode in the reverse direction, and the same 12 × speed in the forward direction. Each of the reproducing heads A and B is different even in the search mode of FIG.
Each is different.

For this reason, the PLL circuit 6 is provided with an offset voltage source for each mode, for each of the forward and reverse running directions, and for each reproducing head. Each offset voltage is switched and supplied to the adder 12 every time, every running direction and each reproducing head.

FIG. 1 shows offset voltage sources 30 to
Although it is illustrated as if a total of 33 types of offset voltage sources are provided, this corresponds to the normal reproduction mode and search mode described above, and a plurality of offset voltages corresponding to each of the reproduction heads A and B. It should be understood that an offset voltage source is provided.

[Configuration of Discriminator 14] The discriminator 14 changes the clock from the VCO 7 by 1 / n.
, And a frequency divider 16 that outputs the frequency-divided clock as a reset pulse, and an oscillator 27 (XO: for example, a crystal oscillator) that oscillates a reference clock having a frequency originally possessed by the information signal reproduced by the rotary head 1. ), A counter 17 for counting the reference clock from the oscillator 27 between the time when the reset pulse is supplied from the frequency divider 16 and the time when the next reset pulse is supplied, and the counter 17
An error signal (error voltage) for correcting the frequency of the clock formed by the VCO 7 by comparing the count value of the VCO with a selected comparison value described below.
And supplies the same to the adder 13
And

The discriminator 14 includes a plurality of frequency division ratio generating circuits 18 to 20 for outputting frequency division ratio signals for changing the frequency division ratio of the frequency divider 16, and each frequency division ratio generating circuit 1.
A changeover switch 25 for switching the frequency division ratio signal from 8 to 20 to supply the frequency divider 16 to the frequency divider 16, a comparison value forming circuit 21 to 23 for forming a plurality of comparison values to be supplied to the comparator 15,
And a changeover switch 24 for switching the comparison value from each of the comparison value forming circuits 21 to 23 and supplying the comparison value to the comparator 15.

As described above, the magnetic reproducing apparatus has 12 × and 18 × search modes in addition to the normal reproduction mode. The frequency of the clock formed by the PLL circuit 6 is It fluctuates in the normal playback mode, the 12 × speed search mode, and the 18 × speed search mode, respectively.

The fluctuation of the clock frequency is different between the same 12 × speed search mode, the forward 12 × speed search mode and the backward 12 × speed search mode, and the same 18 × speed search mode. Even at the time, it differs in the 18 × speed search mode in the forward direction and in the 18 × speed search mode in the reverse direction.

For this purpose, the discriminator 14 is provided with frequency division ratio generating circuits 18 to 20 and comparative value forming circuits 21 to 23 for each mode, and for each of the forward and reverse running directions. The changeover switch 25 switches each frequency division ratio signal for each mode and for each traveling direction, and
The changeover switch 24 switches each comparison value for each mode and for each traveling direction and supplies the comparison value to the comparator 15.

FIG. 1 shows frequency dividing ratio generating circuits 18-2.
0 is provided as a total of three types of frequency division ratio generating circuits, and it is illustrated as if a total of three types of comparative value forming circuits of comparative value forming circuits 21 to 23 are provided. It should be understood that a plurality of frequency division ratio generating circuits or comparison value forming circuits respectively corresponding to the above-described normal reproduction mode and search mode are provided.

[Operation of Embodiment] Next, the operation of the magnetic reproducing apparatus of the embodiment having the above-described configuration will be described.

[Operation in Normal Reproduction Mode] First, the operation in the normal reproduction mode will be described. In the normal reproduction mode, the running of the magnetic tape is controlled at the normal running speed, and the rotating head 1 rotates in the normal rotation mode. The rotation is controlled by the speed. As a result, each of the reproducing heads A,
In B, the recording tracks formed on the magnetic tape are sequentially traced, and the information signal is transmitted to A / A via the preamplifier 2.
It is supplied to the D converter 3. The A / D converter 3 operates based on a clock formed by a PLL circuit 6 described later to digitize an information signal which is an analog signal, and supplies the digitalized information signal to the 1 + D circuit 4 and the phase detector 8. .

The 1 + D circuit 4 converts the information signal from the A / D converter 103 based on the clock from the PLL circuit 6 into
For example, a delay process for one clock is performed, and the current information signal is added to the delayed information signal to reduce the noise of the information signal and demodulate the high frequency band. Supply. The ECC circuit 5 performs an error correction process on the information signal from the 1 + D circuit 104 based on the clock from the PLL circuit 6, and supplies the information signal to a television receiver or the like. Thereby, a video output and an audio output corresponding to the information signal reproduced from the magnetic tape can be obtained via the television receiver or the like.

[Clock forming operation] "Correction operation of lock range center level"
The clock currently formed by the VCO 7 is supplied to the phase detection circuit 8, and the phase detection circuit 8
By comparing the phase of the information signal from the D converter 3 with the phase of the current clock from the VCO 7, the phase error between the two is detected, and this phase error detection output is supplied to the adder 12.

The adder 12 includes an offset voltage generator 9
Is supplied from the offset voltage source 30 to 33 of the offset voltage generator 9 in the normal reproduction mode. ,
The offset voltage for the reproducing head A for the normal reproducing mode and the offset voltage for the reproducing head B for the normal reproducing mode are changed by a drum drum flip-flop signal formed according to the rotation of the rotating drum 1 (see FIG. 5A). ), And these are supplied to the adder 12. The adder 12 controls the offset voltage for the normal reproduction mode supplied through the changeover switch 29 and the phase detection circuit 8.
Is added to the phase error detection output from.

The PLL circuit 6 is provided for each reproduction head A and B for each mode such as a normal reproduction mode and a search mode due to variations in characteristics (variations in gain and offset) of analog components such as the amplifier 10, the LPF 11 and the VCO 7. The center level of the lock range fluctuates,
In this manner, the adder 12 adds the offset voltage for the normal reproduction mode to the phase error detection output to thereby correct the fluctuation of the center level of the lock range of the PLL circuit 6 in the normal reproduction mode. The output can be shaped. The adder 12 supplies the phase error detection output to the adder 13 via the amplifier 10 and the LPF 11.

[Clock Frequency Correction Operation] Next, the adder 13 adds an error voltage for correcting the frequency error of the clock output from the VCO 7 formed by the discriminator 14 to the phase error detection output. Is added to the VCO 7 and supplied to the VCO 7. In the normal reproduction mode, the discriminator 14 detects a frequency error of the clock output from the VCO 7 and forms an error voltage as described below. .

That is, in the case of the normal reproduction mode, the changeover switch 25 sets the frequency division ratio for the normal reproduction mode selected from the frequency division ratio signals output from the frequency division ratio generation circuits 18 to 20. Select the signal and divide it by the divider 16
To supply. The frequency division ratio signal for the normal reproduction mode is, for example, a signal for dividing the clock from the VCO 7 by 100. The frequency divider 16 converts the clock from the VCO 7 based on the frequency division ratio signal for the normal reproduction mode. The frequency is divided by 100, and this frequency-divided clock is supplied to the counter 17 as a reset pulse.

The counter 17 is supplied with the reference clock from an oscillator 27 that oscillates a reference clock having a frequency inherent in the information signal reproduced by the rotary head 1. The reference clock from the oscillator 27 is counted from when the reset pulse is supplied until the next reset pulse is supplied, and this count value is supplied to the comparator 15.

The comparator 15 is supplied with a comparison value selected from the comparison values formed by the plurality of comparison value forming circuits 21 to 23 in addition to the count value. In the case of the normal playback mode, the changeover switch 2
Numeral 4 selects comparison values, for example, "97" and "103", which are comparison values for the normal reproduction mode, from among the comparison values formed by the respective comparison value forming circuits 21 to 23. 15 The comparator 15 monitors the frequency of the clock formed by the VCO 7 by comparing the count value from the counter 17 with each comparison value selected by the changeover switch 24.

Specifically, in the case of the normal reproduction mode,
Since the frequency divider 16 divides the frequency of the clock from the VCO 7 by 100, if the clock generated by the VCO 7 has the correct frequency, the counter 17 outputs the clock from the oscillator 27 until the reset is applied. Clock of 1
It should count 00.

However, when the frequency of the clock generated by the VCO 7 is high, the count value of the counter 17 is reset earlier than usual.
The count value output from the counter 17 is smaller than 100. Conversely, when the frequency of the clock formed by the VCO 7 is low, the count value of the counter 17 is reset later than usual, so that
The count value output from the counter 17 is a value larger than 100.

The comparison value selected by the changeover switch 24 is a value indicating what percentage of the frequency error of the clock formed by the VCO 7 is set as an error. in this case,
The comparison values selected by the changeover switch 24 are “97” and “103”. This “97” and “1”
The comparison value of “03” indicates that the clock frequency error in the normal reproduction mode is, for example, “± 3%” from the center frequency.
This is a value that allows a frequency error other than that.

The comparator 15 compares the count value from the counter 17 with the comparison value selected by the changeover switch 24. If the count value becomes smaller than "97", and "103" When the value becomes larger than the above value, an error signal (error voltage) corresponding to the difference between the two is formed, and this is supplied to the adder 13. When the count value from the counter 17 is in the range of "97 to 103", the output from the comparator 15 is open (the error voltage supplied from the comparator 15 to the adder 13 is 0 level). .)

The adder 13 includes an adder 12, an amplifier 10,
The phase error detection output supplied via the LPF 11 and the error signal supplied from the comparator 15 are added, and the VCO 7 is driven to oscillate based on the added output.
As a result, the clock of the correct phase and frequency corresponding to the information signal reproduced in the normal reproduction mode is output to the VCO 7
And based on this clock, A
It is possible to perform information processing at accurate timing in the / D converter 3, the 1 + D circuit 4, the ECC circuit 5, and the like.

[Operation in Search Mode] Next, the operation in the search mode will be described.
Two search modes of double speed are provided. Even in the same 12 × or 18 × search mode, there is a search in the reverse direction and in the reverse direction. Hereinafter, in the description of the operation in the search mode, the operation in the 12 × speed search mode will be described as a representative. For the operation in the 18 × speed search mode, see the description of the operation in the 12 × speed search mode below.

[Forward Search Operation in 12x Speed Search Mode] First, when the forward search is performed in the 12x speed search mode, the magnetic tape is controlled to run in the forward direction at 12 times the normal running speed. Is controlled at a normal rotation speed. Then, the recording tracks formed on the magnetic tape are traced by the reproducing heads A and B opposed to the rotary head 1, and the information signals are transmitted to the preamplifier 2, the A / D converter 3, and 1 + D as described above. The signal is reproduced by the circuit 4 and the ECC circuit 5 and supplied to a television receiver or the like.
As a result, a video output (and an audio output) corresponding to the information signal reproduced from the magnetic tape can be obtained via a television receiver or the like in a so-called fast-forward state of the magnetic tape.

[Clock Forming Operation During Forward Search in 12x Search Mode] "Correcting operation of center level of lock range"
At the time of the forward search in the 12 × speed search mode, the changeover switch 29 sets one of the offset voltages from the offset voltage sources 30 to 33 of the offset voltage generator 9.
Playback head A for forward search in 2x search mode
And an offset voltage for the reproducing head B for forward search in a 12 × speed search mode are alternately selected based on a drum drum flip-flop signal formed according to the rotation of the rotating drum 1. Is supplied to the adder 12.

More specifically, the reproduction frequency of the information signal reproduced by the reproduction head A in the forward search in the 12 × speed search mode is the reproduction frequency of the information signal reproduced by the reproduction head A in the normal reproduction mode. 3.3% (-3.3%), and the reproduction frequency of the information signal reproduced by the reproduction head B in the normal reproduction mode is 2% smaller than the reproduction frequency of the information signal reproduced by the reproduction head B. -9% (-2.9%).

Therefore, in the forward search in the 12 × speed search mode, the changeover switch 29
An offset voltage 3.3% lower than the offset voltage for the information signal reproduced by the reproducing head A in the normal reproducing mode is applied to the information signal reproduced by the reproducing head A in the forward search in the 12 × speed search mode. And supplies the same to the adder 12. Similarly,
In the forward search in the 12 × speed search mode, the changeover switch 29 sets the offset voltage which is 2.9% lower than the offset voltage for the information signal reproduced by the reproducing head B in the normal reproduction mode to 12 The offset voltage is selected as the offset voltage for the information signal reproduced by the reproducing head B at the time of the forward search in the double speed search mode, and is supplied to the adder 12.

The adder 12 adds the offset voltages for the reproducing heads A and B to the phase error detection output from the phase detection circuit 8, respectively. Thus, in the forward search in the 12 × speed search mode, the phase error in which the center level of the lock range of the PLL circuit 6 is set to the level in the forward search in the 12 × speed search mode for each of the reproducing heads A and B. A detection output can be formed.
The adder 12 supplies the phase error detection output to the adder 13 via the amplifier 10 and the LPF 11.

(Offset voltage in forward search in 18 × speed search mode) The reproduction frequency of the information signal reproduced by the reproducing head A in the forward search in the 18 × speed search mode is the same as that in the normal reproduction mode. The reproducing frequency of the information signal reproduced by the reproducing head B is reduced by 5.1% (-5.1%) from the reproducing frequency of the information signal reproduced by the head A, and reproduced by the reproducing head B in the normal reproducing mode. 4.6% lower than the reproduction frequency of the information signal to be reproduced (-4.6%).

Therefore, in the forward search in the 18 × speed search mode, the changeover switch 29 is
An offset voltage 5.1% lower than the offset voltage for the information signal reproduced by the reproducing head A in the normal reproducing mode is applied to the information signal reproduced by the reproducing head A during the forward search in the 18 × speed search mode. And supplies the same to the adder 12. Similarly,
At the time of the forward search in the 18 × speed search mode, the changeover switch 29 sets the offset voltage which is 4.6% lower than the offset voltage for the information signal reproduced by the reproduction head B in the normal reproduction mode to 18. The offset voltage is selected as the offset voltage for the information signal reproduced by the reproducing head B at the time of the forward search in the double speed search mode, and is supplied to the adder 12.

Thus, at the time of the forward search in the 18 × speed search mode, the PLL is provided for each of the reproducing heads A and B.
A phase error detection output can be formed in which the center level of the lock range of the circuit 6 is set to the level at the time of the forward search in the 18 × speed search mode.

[Clock Frequency Correction Operation] Next, at the time of forward search in the 12 × speed search mode, the changeover switch 25 of the discriminator 14 is output from each of the frequency division ratio generating circuits 18 to 20. From the frequency division ratio signals, a frequency division ratio signal for forward search in a 12 × speed search mode is selected and supplied to the frequency divider 16. Also,
The changeover switch 24 is connected to each of the comparison value forming circuits 21 to 23
The comparison value for forward search in the 12 × speed search mode is selected from the comparison values formed by
To supply.

As described above, in the normal reproduction mode, the frequency error of the clock monitored by the discriminator 14 is set to, for example, “± 3%” from the center frequency of the clock. At the time of the direction search, for example, “−6% to 0” from the center frequency of the clock
% ". For this reason, the changeover switches 25 and 24 change the monitoring range of the clock frequency error from the center frequency of the clock by “−”.
A frequency division ratio signal and a comparison value of “6% to 0%” are selected and supplied to the frequency divider 16 and the comparator 15, respectively.

The frequency divider 16 outputs V in accordance with the frequency division ratio signal.
The clock from the CO 7 is frequency-divided, and the frequency-divided clock is supplied to the counter 17 as a reset pulse. The counter 17 counts the reference clock supplied from the oscillator 27 between the time when the reset pulse is supplied and the time when the next reset pulse is supplied.
To supply. The comparator 15 compares the count value from the counter 17 with the comparison value selected by the changeover switch 24, so that the frequency of the clock formed by the VCO 7 is "-6% to 0%" from the center frequency. It is monitored whether it is within the range. Then, the frequency of the clock formed by the VCO 7 is “-6%
If it is out of the range of ".about.0%", an error signal corresponding to the difference between the count value and the comparison value is formed and supplied to the adder 13.

The adder 13 includes an adder 12, an amplifier 10,
The phase error detection output supplied via the LPF 11 and the error signal supplied from the comparator 15 are added, and the VCO 7 is driven to oscillate based on the added output.
This allows the VCO 7 to form a clock having an accurate phase and frequency corresponding to the information signal reproduced at the time of the forward search in the 12 × speed search mode, and based on the clock, the A / D converter It is possible to perform information processing at accurate timing in the 3, 1 + D circuit 4, the ECC circuit 5, and the like.

(Frequency Error Range in Forward Search in 18 × Speed Search Mode) In the forward search in the 18 × search mode, the monitoring range of the clock frequency error is set to “−” from the center frequency of the clock. 8% ~
-2%. " For this reason, the changeover switches 25 and 24 change the monitoring range of the clock frequency error from the center frequency of the clock by “−”.
8% to -2% "and a comparison value,
These are supplied to the frequency divider 16 and the comparator 15, respectively. This allows the VCO 7 to form a clock with an accurate phase and frequency corresponding to the information signal reproduced during the forward search in the 18 × speed search mode.

[Reverse Search Operation in 12x Speed Search Mode] Next, when the reverse search is performed in the 12x speed search mode, the magnetic tape is controlled to run in the reverse direction at 12 times the normal running speed, and the rotating head is rotated. 1 is rotationally controlled at a normal rotational speed. Then, the recording tracks formed on the magnetic tape are traced by the reproducing heads A and B opposed to the rotary head 1, and the information signals are transmitted to the preamplifier 2, the A / D converter 3, and 1 + D as described above. The signal is reproduced by the circuit 4 and the ECC circuit 5 and supplied to a television receiver or the like.
As a result, a video output (and an audio output) corresponding to the information signal reproduced from the magnetic tape can be obtained via a television receiver or the like in a state in which the magnetic tape is quickly returned.

[Clock Forming Operation in Reverse Search in 12x Speed Search Mode] "Correction operation of center level of lock range"
At the time of the reverse search in the 12 × speed search mode, the changeover switch 29 sets one of the offset voltages from the offset voltage sources 30 to 33 of the offset voltage generator 9.
Playback head A for reverse search in 2x speed search mode
And an offset voltage for the reproducing head B for reverse search in a 12 × speed search mode are alternately selected based on a drum drum flip-flop signal formed in accordance with the rotation of the rotary drum 1. Is supplied to the adder 12.

More specifically, the reproduction frequency of the information signal reproduced by the reproducing head A in the reverse search in the 12 × speed search mode is the reproduction frequency of the information signal reproduced by the reproducing head A in the normal reproducing mode. 3.9% (+ 3.9%) from the reproduction frequency of the information signal reproduced by the reproduction head B in the normal reproduction mode. Up 5% (+ 3.5%).

Therefore, in the reverse search in the 12 × speed search mode, the changeover switch 29
An offset voltage 3.9% higher than the offset voltage for the information signal reproduced by the reproducing head A in the normal reproducing mode is applied to the information signal reproduced by the reproducing head A during the reverse search in the 12 × speed search mode. And supplies the same to the adder 12. Similarly,
At the time of the reverse search in the 12 × speed search mode, the changeover switch 29 sets the offset voltage higher by 3.5% than the offset voltage for the information signal reproduced by the reproducing head B in the normal reproduction mode to 12 The offset voltage is selected as the offset voltage for the information signal reproduced by the reproducing head B at the time of the reverse search in the double speed search mode, and supplied to the adder 12.

The adder 12 adds the offset voltage for each of the reproducing heads A and B to the phase error detection output from the phase detection circuit 8, respectively. Thus, during the backward search in the 12 × speed search mode, the phase error in which the center level of the lock range of the PLL circuit 6 is set to the level in the backward search in the 12 × speed search mode for each of the reproducing heads A and B. A detection output can be formed.
The adder 12 supplies the phase error detection output to the adder 13 via the amplifier 10 and the LPF 11.

(Offset Voltage in Reverse Search in 18 × Speed Search Mode) The reproduction frequency of the information signal reproduced by the reproducing head A in the reverse search in the 18 × speed search mode is the same as that in the normal reproduction mode. The reproduction frequency of the information signal reproduced by the reproduction head B is increased by 5.7% (+ 5.7%) with respect to the reproduction frequency of the information signal reproduced by the head A, and reproduced by the reproduction head B in the normal reproduction mode. 5.1% (+ 5.1%) with respect to the reproduction frequency of the information signal.

Therefore, in the reverse search in the 18 × speed search mode, the changeover switch 29
An offset voltage having a voltage 5.7% higher than the offset voltage for the information signal reproduced by the reproducing head A in the normal reproducing mode is applied to the information signal reproduced by the reproducing head A in the reverse search in the 18 × speed search mode. And supplies the same to the adder 12. Similarly,
In the reverse search of the 18 × speed search mode, the changeover switch 29 sets the offset voltage which is higher by 5.1% than the offset voltage for the information signal reproduced by the reproducing head B in the normal reproduction mode to 18. The offset voltage is selected as the offset voltage for the information signal reproduced by the reproducing head B at the time of the reverse search in the double speed search mode, and supplied to the adder 12.

As a result, during the reverse search in the 18 × speed search mode, the PLL is provided for each of the reproducing heads A and B.
A phase error detection output can be formed in which the center level of the lock range of the circuit 6 is set to the level at the time of reverse search in the 18 × speed search mode.

[Clock Frequency Correction Operation] Next, at the time of reverse search in the 12 × speed search mode, the changeover switch 25 of the discriminator 14 is output from each of the frequency division ratio generation circuits 18 to 20. From among the frequency division ratio signals, a frequency division ratio signal for reverse search in a 12 × speed search mode is selected and supplied to the frequency divider 16. Also,
The changeover switch 24 is connected to each of the comparison value forming circuits 21 to 23
A comparison value for the backward search in the 12 × speed search mode is selected from the comparison values formed by
To supply.

As described above, in the normal reproduction mode, the frequency error of the clock monitored by the discriminator 14 is set to, for example, “± 3%” from the center frequency of the clock. At the time of the direction search, for example, “+ 1% to +
7% ". For this reason, the changeover switch 25 and the changeover switch 24 select a frequency division ratio signal and a comparison value that set the monitoring range of the clock frequency error to “+ 1% to + 7%” from the center frequency of the clock, and divide them. To the comparator 16 and the comparator 15, respectively.

The frequency divider 16 outputs V in accordance with the frequency division ratio signal.
The clock from the CO 7 is frequency-divided, and the frequency-divided clock is supplied to the counter 17 as a reset pulse. The counter 17 counts the reference clock supplied from the oscillator 27 between the time when the reset pulse is supplied and the time when the next reset pulse is supplied.
To supply. The comparator 15 compares the count value from the counter 17 with the comparison value selected by the changeover switch 24, so that the frequency of the clock formed by the VCO 7 is "+ 1% to + 7%" from the center frequency. Monitor whether it is within the range. Then, the frequency of the clock formed by the VCO 7 is shifted by “+1” from the center frequency.
If it is out of the range of "% to + 7%", an error signal corresponding to the difference between the count value and the comparison value is formed and supplied to the adder 13.

The adder 13 includes an adder 12, an amplifier 10,
The phase error detection output supplied via the LPF 11 and the error signal supplied from the comparator 15 are added, and the VCO 7 is driven to oscillate based on the added output.
As a result, a clock having an accurate phase and frequency corresponding to the information signal reproduced at the time of the reverse search in the 12 × speed search mode can be formed by the VCO 7, and based on the clock, the A / D converter is used. It is possible to perform information processing at accurate timing in the 3, 1 + D circuit 4, the ECC circuit 5, and the like.

(Frequency Error Range During Reverse Search in 18 × Speed Search Mode) In the reverse search in the 18 × search mode, the monitoring range of the clock frequency error is set to “+2” from the center frequency of the clock. % ~
+ 8%. " For this reason, the changeover switches 25 and 24 change the monitoring range of the frequency error of the clock from the center frequency of the clock by “+”.
2% to + 8% "and the comparison value,
These are supplied to the frequency divider 16 and the comparator 15, respectively. This allows the VCO 7 to form a clock with an accurate phase and frequency corresponding to the information signal reproduced at the time of the reverse search in the 18 × speed search mode.

[Effects of the Embodiment] As is clear from the above description, the magnetic reproducing apparatus of the present embodiment operates in the normal reproduction mode and the search mode, and in the running direction (forward or backward) of the magnetic tape in the search mode. PLL circuit 6 for each reproducing head for tracing the magnetic tape.
, And an error voltage for correcting the frequency of the clock formed by the VCO 7 can be varied. For this reason, even when the relative speed of the rotating drum and the magnetic tape fluctuates, the VCO 7 can form a clock having an optimum phase and frequency for each mode, the running direction of the magnetic tape, and each reproducing head. Therefore, it is possible to operate the PLL circuit 6 stably and accurately reproduce the information signal.

[Modification of the Present Invention] Finally, the above-described embodiment is an example of the present invention. For example, in the description of the above-described embodiment, the monitoring range of the frequency error of the clock of the discriminator 14 in the normal playback mode is ± 3% from the center frequency, or the forward search in the 12 × speed search mode. At this time, the reproduction frequency of the information signal reproduced by the reproduction head A is a specific numerical value such as 3.3% lower than the reproduction frequency of the information signal reproduced by the reproduction head A in the normal reproduction mode. Although described above, such numerical values are examples for facilitating understanding of the present invention. Therefore, the present invention is not limited to such numerical values, and is not limited to the above-described embodiment. It goes without saying that various changes can be made in accordance with the design and the like within a range not departing from the spiritual idea.

[0093]

According to the magnetic reproducing apparatus of the present invention, the clock forming means can be operated stably according to the relative speed between the rotary head and the tape-shaped magnetic recording medium. Then, based on the clock formed by the clock forming means, the information processing means can perform information processing on information reproduced by the rotary head at accurate and optimal timing.

In the magnetic reproducing apparatus according to the present invention, the clock forming operation of the clock forming means is performed for each reproducing head for reproducing the information together with the relative speed between the rotary head and the tape-shaped magnetic recording medium. This makes it possible to control the clock forming means more stably and to perform information processing at accurate and optimal timing.

According to a third aspect of the present invention, there is provided a magnetic reproducing apparatus, comprising: a relative speed between a rotary head and a tape-shaped magnetic recording medium;
Also, the clock forming operation of the clock forming means can be controlled according to the running direction of the tape-shaped magnetic recording medium, so that the clock forming means can be operated more stably and the information processing can be performed with accurate and optimal timing. Can be performed.

Alternatively, in the magnetic reproducing apparatus according to the third aspect of the present invention, the relative speed between the rotary head and the tape-shaped magnetic recording medium, and the first and second information reproducing the information thereof.
The clock forming operation of the clock forming means can be controlled even in accordance with the reproducing head of the present invention and the running direction of the tape-shaped magnetic recording medium. It is possible to perform information processing at a timing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a magnetic reproducing apparatus of a D-VHS system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a rotary head provided in a conventional D-VHS type magnetic reproducing apparatus.

FIG. 3 is a schematic diagram of a recording track obliquely recorded on a magnetic tape by a conventional D-VHS magnetic reproducing apparatus.

FIG. 4 is a block diagram of a conventional D-VHS magnetic reproducing apparatus.

FIG. 5 is a diagram showing signal waveforms at various parts of a conventional D-VHS magnetic reproducing apparatus.

FIG. 6 is a block diagram of a discriminator provided in a conventional D-VHS type magnetic reproducing device.

[Explanation of symbols]

1 rotary drum, 2 preamplifier, 3 A / D converter,
4 ... 1 + D circuit, 5 ... Error correction circuit (ECC circuit), 6
... PLL circuit, 7 ... Variable voltage oscillator (VCO), 8 ...
Phase comparator, 9 offset voltage generator, 10 amplifier, 11 low-pass filter (LPF), 12, 13 ...
Adder, 14: discriminator, 15: comparator, 1
Reference numeral 6: frequency divider, 17: counter, 18 to 20: frequency dividing ratio generating circuit, 21 to 23: comparison value forming circuit, 24, 25: changeover switch, 27: crystal oscillator (XO), 30 to 33
… Offset voltage source

Continued on front page F term (reference) 5D044 BC01 CC03 FG23 GM14 GM18 5J106 AA04 BB04 CC01 CC15 CC21 CC38 CC41 CC53 DD05 DD06 DD13 DD17 DD36 EE18 FF02 KK12

Claims (3)

[Claims] 1. A rotary head for reproducing information obliquely recorded on a tape-shaped magnetic recording medium, and information for performing predetermined information processing and restoring information reproduced from the tape-shaped magnetic recording medium by the rotary head. Processing means; clock forming means for forming an operation clock of the information processing means; running speed control means for controlling the running speed of the tape-shaped magnetic recording medium; and running of the tape-shaped magnetic recording medium by the running speed control means. A magnetic head comprising: a clock forming operation control unit configured to control a clock forming operation of the clock forming unit in accordance with a relative speed between the rotary head and the tape-shaped magnetic recording medium, the speed being changed by controlling the speed. Playback device. 2. The rotating head according to claim 1, further comprising:
And a second reproducing head, wherein the clock forming operation control means controls the clock forming operation of the clock forming means in accordance with the first and second reproducing heads that have reproduced the information. The magnetic reproducing apparatus according to claim 1, wherein: 3. The clock forming operation control means controls a clock forming operation of the clock forming means in accordance with a running direction of the tape-shaped magnetic recording medium, the running of which is controlled by the running speed control means. Claim 1
Alternatively, the magnetic reproducing apparatus according to claim 2.