JP2001014161A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time needed for processing in a pipeline cycle and to shorten the total instruction execution time by dividing a 1st instruction read-in stage of conventional 5-stage pipeline constitution into two parts for the update of a program counter and the reading of an instruction memory. SOLUTION: The 1st stage which requires the longest time for processing in 5-stage pipeline constitution is divided into two stages for updating the program counter PC and accessing an instruction memory IMEM. At a 3rd stage, a register fetch processing for fetching values from an instruction decoder DC and a general register is performed and at a 4th stage, arithmetic logical operation, data address calculation, or branch calculation of the effective address of a branch destination is performed. At a 5th stage, a memory access processing to a data memory DMEM or branching processing is performed at a 6th stage, an arithmetic processing or a writing processing to the general register is performed. Then 6-stage pipeline constitution is obtained as the whole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a programmable controller having dedicated hardware (processor) capable of processing both basic bit operation instruction processing and multi-bit application instruction processing.

[0002]

2. Description of the Related Art Programmable controllers are widely used for controlling industrial equipment, machines and factory automation equipment, and process a greater number of input / output signals at high speed in accordance with the complexity and speed of the target equipment. Is required. For this reason, a basic instruction mainly for bit processing is combined with a general-purpose microprocessor that performs high-speed processing using dedicated hardware (processor) capable of processing multi-bit applied instructions and performs communication processing and peripheral processing. To form a programmable controller. Conventionally, as the structure of the dedicated hardware (processor), the following 3 is used.
Instructions were executed in a staged pipeline structure.

First stage: instruction fetch Second stage: instruction decode, register fetch, arithmetic logic operation, data address calculation, branch destination calculation Third stage: memory access (read / write), branch, bit operation, register write

In the above three-stage pipeline structure, the overall instruction execution speed is determined by the processing speed of the slowest execution stage among the stages. In order to speed up such pipeline processing, it is necessary to equalize the processing speed of each stage. In this example, if memories having the same access time are used for the instruction memory and the data memory, the first processing is performed.
There is an imbalance that the processing time is required as much as the third stage performs the bit operation on the stage.
In order to improve the execution speed, the pipeline stage may be further divided into multiple stages.

Therefore, the present inventors have developed a programmable controller having a five-stage pipeline structure in which an instruction execution cycle of dedicated hardware (processor) is divided into the following five stages. 1st stage: instruction fetch 2nd stage: instruction decode, register fetch 3rd stage: arithmetic logic operation, data address calculation, branch destination calculation 4th stage: memory access (read / write) 5th stage: branch, bit operation, Write register

When this five-stage pipeline structure is adopted,
Compared to a conventional programmable controller having a three-stage pipeline structure, the imbalance between pipeline stages is improved, and the time required for one stage of the pipeline stage is reduced, so that the overall instruction execution speed can be improved. . FIG. 30 shows a schematic configuration diagram of the programmable controller having the five-stage pipeline structure.

In the figure, an IF (Instruction F)
The first stage, denoted by (etch), is the instruction memory IM
At the stage of performing an instruction fetch process of reading the next instruction to be executed from the EM to the instruction register IR, receiving the signals from the instruction memory IMEM for storing the instruction and the address calculation circuit ADDRCALC for controlling the program counter, and executing the next instruction Instruction memory IMEM in which instructions to be stored are stored
And a program counter PC for counting the address of the program. An instruction register IR in which an instruction read from the instruction memory IMEM is stored in accordance with the address designation of the program counter PC stores an execution result of the first stage IF and transmits the result to the next second stage ID. , Pipeline register IF / ID.

[0008] ID (Instruction Deco)
The second stage indicated by de) is a stage for performing instruction decoding by the instruction decoder DC and register fetch processing for extracting a value from one of a plurality of general-purpose registers constituting the register file RF. It comprises a decoder DC for decoding and a general-purpose register file RF composed of a plurality of general-purpose registers. The general register file RF is provided with two outputs, one output is connected to S1 of the pipeline register ID / EX, and the other output is connected to S2 of the pipeline register ID / EX.
The value decoded by the instruction decoder DC is also stored in a predetermined location of the pipeline register ID / EX.

Next, a third stage indicated by EX (Execute) is a stage in which the arithmetic and logic operation unit ALU performs an arithmetic and logic operation or a data address calculation or a branch destination calculation for calculating an effective address of a branch destination. One input of the logical operation unit ALU is connected to the output of S1 of the pipeline register ID / EX,
The other input is S2 of the pipeline register ID / EX.
Connected to the output. The arithmetic and logic unit ALU is controlled by the value of the decoded instruction stored at a predetermined location of the pipeline register ID / EX, and the output of the arithmetic and logic unit ALU is output from the pipeline register EX / MEM. D is stored.

Next, MEM (MEMory acces)
The fourth stage indicated by s) is a data memory DMEM
In the stage where the memory access process is performed, the value stored in the location D of the pipeline register EX / MEM is stored in the memory at the predetermined address of the data memory DMEM, and the value stored in the pipeline register MEM / WB is stored in the predetermined address. Is output to the location. Or data memory DMEM
Is stored in a predetermined location of the pipeline register MEM / WB.

Finally, a fifth stage represented by WB (Write Back) is a stage for performing a bit operation, a write process to a general-purpose register, or a branch process.
In the case of a write process to a general-purpose register, a value stored in a predetermined location of the pipeline register MEM / WB is stored in a predetermined general-purpose register of the register file RF. However, FIG. 30 shows only a portion related to the present invention, and other components are not shown.

The functions required for the programmable controller include one of the data memories DMEM.
There is a bit processing instruction for referring to and updating a certain 1-bit value in a word, and for referring to and updating a multiple-word data memory DMEM during execution of an instruction. Since the execution of the bit processing instruction requires a plurality of memory access cycles, the bit processing instruction cannot be executed if the above-described five-stage pipeline structure is used as it is. Therefore, in this conventional example, a BPU (Bit Processing Un
It) block and a register updated by the bit processing operation: BITACC (Bit Accumulate)
or).

In a programmable controller having this five-stage pipeline structure, for example, as shown in FIG. 31, IF: instruction fetch, ID: instruction decode, register fetch, EX: arithmetic logic operation, data address calculation, branch destination calculation , MEM: memory access (read / write), WB: branch, register write, and executes one instruction in five pipeline stages. In addition to such an instruction, there is an instruction required by the programmable controller called a “bit processing instruction” for referring to or updating a certain 1-bit value in one word of the data memory. There are various types of instructions called bit processing instructions, and a register: BITACC (bit accumulator) inside the programmable controller is updated according to the state of a certain bit of one word of the read data memory.
There is an instruction to update a certain 1-bit value in the data memory in addition to updating the ACC. In this bit processing instruction, an instruction other than the bit processing instruction writes a BITAC in a portion corresponding to the WB stage in which a register write or the like was performed by using the value of the data memory read in the MEM stage.
Update of C, update of a 1-bit value in data memory,
There is a BPU stage that performs operations such as data memory writing. There are many types of bit processing instructions, and the number of BPU stages required according to the instruction also changes as shown in FIGS. 15B and 15C described later.

[0014]

The conventional example having the five-stage pipeline configuration has an improved instruction execution speed as compared with the conventional example having the three-stage pipeline configuration. However, the demand for higher speed is increasing, and the miniaturization of the semiconductor process for realizing a processor which is dedicated hardware is progressing, and the speed of each circuit block constituting the dedicated hardware (processor) is progressing. In some cases, the five-stage pipeline configuration is not an optimal configuration for achieving high speed. For example, due to the improvement of the operation speed of the dedicated hardware (processor) of the circuit itself, the memory access executed in the first stage or the fourth stage is more effective than the various arithmetic processes which are the third stage of the five-stage pipeline configuration. Although it may take time, the fourth stage only accesses the data memory DMEM, whereas the first stage determines the value of the program counter PC which is the address of the instruction memory IMEM. , Instruction memory IM
Since the EM must be accessed, the instruction memory I
When memories having the same access time are used for the MEM and the data memory DMEM, an unbalance occurs in that the first stage needs more processing time by the amount of the update processing of the program counter PC.

The present invention has been made in view of such a point, and an object of the present invention is to shorten the time required for one processing of a pipeline cycle and to shorten the entire instruction execution time. It is to provide a programmable controller.

[0016]

As described above, in order to maximize the performance of dedicated hardware (processor) having a pipeline configuration, it is necessary to equalize the execution time of each stage of pipeline processing. is there. Therefore, the first stage, which spends the most time in processing in the five-stage pipeline configuration, is divided into two stages, one for updating the program counter PC and the other for accessing the instruction memory IMEM. A pipeline configuration is used (claims 1 and 2). In the conventional example, the dedicated hardware (processor) employs a configuration in which a plurality of clock signals are used to control internal operations. However, discrimination of clock signals may cause an unbalance in processing time. Therefore, the present invention employs a configuration in which the dedicated hardware (processor) operates with a single clock signal (claim 3).

[0017]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of a programmable controller having a six-stage pipeline according to the present invention. FIG. 2 shows an operation timing chart thereof. In this embodiment, of the five-stage pipeline configuration of the conventional example, the first instruction reading stage is divided into two, that is, the updating of the program counter PC and the reading of the instruction memory IMEM. Only the necessary time can be set as the pipeline cycle, the time required for the pipeline cycle can be shortened, and the processing speed can be increased. Comparing FIG. 31 of the conventional example with FIG. 2 of the first embodiment, it seems that the first embodiment spends more time, but the time shown here is the pipeline cycle represented by time 1. Actually, the pipeline cycle time of FIG. 2 is shorter than that of FIG. 31, and the processing speed of the first embodiment is faster.

Further, as in the second embodiment shown in FIG. 4, a single-phase clock signal is used as a clock signal for driving a sequential circuit such as a flip-flop, a general-purpose register, or a pipeline register in dedicated hardware (processor). In addition, the processing speed can be increased (claim 3). Conventionally, as shown in FIG. 3, an additional clock signal serving an auxiliary role is used in addition to the clock signal Φ1 for driving the pipeline register. In FIG. 3, four-phase clocks Φ1, Φ2, Φ obtained by dividing the pipeline cycle into four equal parts
3 and Φ4 are shown as an example. And
A sequential circuit (for example, a program counter PC) other than the pipeline register is driven by a clock signal other than Φ1, that is, Φ2 in FIG. With such a configuration, the design flexibility is improved, but the operation must be completed between adjacent clock signal edges, for example, from Φ1 to Φ2, instead of the period of Φ1 of the pipeline cycle inside the circuit. Some parts may have to be created. That is, in the example of FIG. 3, there is also a path in which the operation must be completed in one-fourth of the pipeline cycle, which hinders the speeding up of the dedicated hardware. Further, as the operating frequency increases, it has become difficult to guarantee the relative relationship between the timings of the edges of different clock systems of the LSI. Therefore, by determining the clock signal for driving the internal sequential circuit to be a single-phase clock as shown in FIG. 4, the operation time of the circuit which must be considered can be simplified to only the pipeline cycle.
Further, in the case of clock signals of the same system, it is easy to reduce the clock skew on the LSI real device.

As described above, the circuit configuration of the dedicated hardware (processor) that operates with a single-phase clock is, for example, as shown in FIG.
become that way. Conventionally, the register file is driven by a clock signal different from the pipeline register. However, since the second embodiment operates with a single-phase clock, the output of the register file RF in the third stage is output as shown in FIG. It is used as it is in the fourth stage.

Next, FIG. 6 shows a main part circuit configuration of the third embodiment. In the second embodiment, the input to the arithmetic and logic unit ALU for performing the actual operation uses the output of the register file in the second embodiment, but in the third embodiment, it is additionally transferred to the pipeline register EX / MEM or MEM / WB. AL done
The output of U can be selected (claim 4). FIG. 6 illustrates only the relevant portions of the dedicated hardware, and here shows only one of the two inputs of the ALU. It goes without saying that the other input of the ALU may have the same configuration. In the figure, ALU
RSLT calculates the operation result in ALU (ALU Resul
t), the pipeline registers EX / MEM and ME
The data is transferred on the M / WB and finally stored in the register file. SRCFB is a selection means. As an input of the ALU, data SRCFB is stored in the register file.
1 or the data ALURSLT on the pipeline register EX / MEM which is the operation result of the ALU, or the pipeline register ME which is the operation result of the ALU.
This is a means for selecting whether to use the data ALURSLT on the M / WB. When the pipeline operation is executed, a delay occurs between the completion of the operation and the time when the value is stored in the register. In the third embodiment, a problem due to the delay is avoided. FIG. 7 shows the operation timing of the third embodiment.

The instruction 1 shown in FIG. 7 corresponds to the AN of the registers R1 and R2.
The result of the D operation is stored in the register R3. The result of the AND operation completed at time 4 is stored in the register R3 for the first time at time 6. Here, in the instruction following the instruction 1, the register R3 updated by the instruction 1
In FIG. 7, the instruction 3 immediately after the instruction 1 in FIG. 7 requires the value of the register R3 as an operation argument. However, the instruction 3 reads the argument at the time 5; The value of the register R3 updated by the instruction 1 has not yet been reflected in the register file, and if the operation is executed as it is, the operation with an incorrect argument will be executed.
Therefore, as shown in FIG. 6, in the third embodiment, the values which have not yet been written to the register file, but are transferred on the pipeline register for writing to the register file, are used as the arguments of the operation. It is possible to execute an operation without any change.

By using the data on the pipeline structure in this way, the operation using the correct argument can be performed even if the value is not written in the register file, but the LOAD instruction for reading the value from the data memory DMEM is used. In the case, the situation changes. As shown in FIG.
When a value is read from the data memory DMEM by the OAD instruction, the value appears in the dedicated hardware (processor) at time 5 and the value is written in the register file RF at time 6. . Therefore, if the subsequent instruction is executed as it is, an operation based on a correct argument cannot be executed, and it is necessary to stop the pipeline operation and wait for a value to be read from the data memory DMEM for several cycles.

In FIG. 8, it is apparent from a comparison between the normal operation example of the instruction 2 and the failure occurrence example that the data memory D
L to read data from MEM to register file RF
When the instruction 2 having the data stored in the register file RF as the argument is executed after the execution of the OAD instruction 1, the unit time of the pipeline between the IF unit and the ID unit in the pipeline operation of the instruction 2 is 2 units. Normal operation can be achieved by inserting a pause (stall) for a number of times, but a malfunction occurs if a stall is not provided.

FIG. 9 shows a fourth embodiment for coping with the execution inconsistency relating to the instruction following the LOAD instruction. An instruction is decoded in an instruction decoding stage which is a third stage of a six-stage pipeline configuration, and control information indicating that the instruction is a LOAD instruction and which general-purpose register in the register file RF stores a value by the LOAD instruction is transmitted. , Sequentially on the pipeline register. The control information is transferred to the hatched portion in the figure, and is analyzed by the hazard detection unit HDU. When it is detected that the instruction uses the value of the general-purpose register as an argument when the instruction is decoded by the decoder DC, this is notified to the hazard detection unit HDU. The hazard detection unit HDU checks whether the general-purpose register serving as an argument is updated by the preceding LOAD instruction, stops the pipeline operation as necessary, and waits until the register value is updated to a correct value.

When the hazard detection unit HDU stops the pipeline operation, PC_HZD (hazard of the program counter) is set to "1". When a normal pipeline operation is being executed, PC_HZD is “0”.
It is. At this time, the program counter PC of the pipeline register PC / IF has an address calculation unit ADDRC.
The output of the ALC is stored in the pipeline register PC /
The contents of the IF program counter PC are stored in the instruction memory IM.
Used for reading the EM, transferred to the program counter PC of the pipeline register IF / ID,
The instruction read from the instruction memory IMEM operates so as to be stored in the instruction register IR of the pipeline register IF / ID. On the other hand, the hazard detection unit HDU requires the PC to stop the pipeline operation.
_HZD is set to “1”, the pipeline register PC
The output of the pipeline counter IF / ID program counter PC is stored in the / IF program counter PC, and the contents of the pipeline register PC / IF program counter PC are transferred to the pipeline register IF / ID program counter PC. At the same time, the instruction memory IR is used for reading the instruction memory IMEM. The instruction register IR of the pipeline register IF / ID does not store the instruction read from the instruction memory IMEM, but retains the previous contents.

FIG. 10 shows an operation timing chart of the fourth embodiment. In FIG. 10, LOAD is at address 1 of the instruction memory IMEM.
As instructions, instructions using a register R1 updated by a LOAD instruction as an argument are arranged at the following address 2, and those instructions are sequentially executed. PC_IF_PC in the figure is a PC on pipeline register PC / IF,
ID_PC is PC on pipeline register IF / ID
Indicates that the IF_ID_IR is an IR on the pipeline register IF / ID. FIG.
As shown in the timing chart, after the time 6 when the LOAD instruction of the instruction 1 updates the register R1, the operation of the instruction 2 of the succeeding instruction reads the argument.

By the way, as shown in Embodiment 4, the LO
When an instruction following the AD instruction refers to a register updated by the LOAD instruction, the pipeline operation stops.
It is desirable to avoid such a behavior that reduces the operation speed as much as possible. For example, if the instruction following the LOAD instruction is a STORE instruction that writes a value to the data memory DMEM, it is not necessary to stop the pipeline operation as in the fourth embodiment. This is because the STORE instruction does not need to calculate a value in the ALU, unlike other inter-register operation instructions.

FIG. 11 shows an operation timing chart of the fifth embodiment for realizing the exception processing in this case. When the LOAD instruction of instruction 1 reads a value from the data memory DMEM, the value appears in the dedicated hardware (processor) at time 5 and is stored in the register R1 at time 6 is there. Then, the instruction 2 immediately after the STOR writes the value of the register R1 into the data memory DMEM.
In the case of the E instruction, the value of the register R1 must be updated to a correct value before the execution of the EX stage, but the STORE instruction writes the value of the general-purpose register as it is without processing the value with the ALU. Since the instruction is an instruction, the value before being written to the general-purpose register can be directly used for the STORE instruction. FIG.
In the case of the instruction 2 of the instruction 1, the MEM stage starting from the time 5 is used. In the case of the instruction 3, the instruction is also the EX stage. Instructions can be executed.

FIG. 12 is a block diagram showing the circuit configuration of the fifth embodiment. MEMFB2 in FIG. 12 is data selection means for the STORE instruction of instruction 2 in FIG. 11, and MEMFB1 in FIG. 12 is data selection means for the STORE instruction of instruction 3 in FIG. That is, when the LOAD instruction of instruction 1 reads a value from the data memory DMEM, the value appears in the dedicated hardware (processor) at time 5 and the value is stored in the pipeline register MEM /
Appears in the SRCMEM part of WB. This value is
MUX and MEM stage selection means MEM for use in the MEM stage
The data is written to the data memory DMEM via the FB2. In order to use the same value in the EX stage of the instruction 3, the value read by the instruction 1 is stored in the SRCMEM portion of the pipeline register EX / MEM via the multiplexer MUX of the WB stage and the selecting means MEMFB1 of the EX stage. Keep it. In the MEM stage of the instruction 3, the SRCMEM of the pipeline register EX / MEM is used.
Will be written to the data memory DMEM via the selection means MEMFB2.

As a case where the pipeline operation is disturbed, there is a branch instruction in addition to the LOAD instruction described above. FIG. 13 shows how the branch instruction is being executed. It is assumed that the instruction 1 stored at the address 1 of the instruction memory IMEM is a branch instruction, the branch condition of this instruction is satisfied, and the instruction 1 branches to the instruction stored at the address 100 of the instruction memory IMEM. . The instruction 1 determines a branch condition in the EX stage, and based on the result, at time 5, sets the branch destination address to the program counter PC.
The instruction 100 at the branch destination is read from the instruction memory IMEM based on the value of the program counter PC and is executed. However, before the execution of the instruction 100 at the branch destination starts, Instructions 2, 3, which are instructions
4 is input into the pipeline, and instructions 2, 3, and 4, which must not be executed when the branch condition is satisfied, are executed.

Therefore, as shown in FIG. 14, four selection means MUX (multiplexer) are provided,
Selection signals PC_SEL, IF_HZD, ID_HZ output from hazard detection unit HDU of M stage
D, EX_HZD. In the control information of the pipeline registers EX / MEM, JP is a flag indicating that the instruction decoded by the decoder DC in the ID stage is a jump instruction, PC is the branch destination address of the jump instruction, and D is the operation result of the ALU. Data, EQ (Equa
l) is a flag indicating that the condition of the conditional jump instruction that branches to the branch destination address when the two values are compared and matched in the ALU is satisfied, GT (Greater that)
n) is a flag indicating that the condition of the conditional jump instruction that branches to the branch destination address when one value is larger than the other by comparing two values in the ALU is satisfied, LT (Less)
(tan) is a flag indicating that the condition of the conditional jump instruction that branches to the branch destination address when one is smaller than the other in the ALU is satisfied.

Hazard detection unit H for MEM stage
When the flag indicating the satisfaction of the condition of the jump instruction JP or the conditional jump instructions EQ, GT, and LT is set in the control information of the pipeline register EX / MEM, as shown in FIG. 13, the DU selects the selection signal PC_SEL ( I
F_HZD, ID_HZD, and EX_HZD are the same). In FIG. 13, PC_IF_PC indicates a program counter PC on the pipeline register PC_IF, and IF_ID_IR indicates an instruction register IR on the pipeline register IF_ID.

Hereinafter, selection signals PC_SEL, IF output from the hazard detection unit HDU of the MEM stage
_HZD, ID_HZD and EX_HZD will be described. The ID section and the EX section of the pipeline structure are provided with selection means MUX (multiplexer) for overwriting the control signal as a result of decoding the instruction with "0".
When _HZD and EX_HZD are “1”, a function of invalidating a control signal for leaving a result such as register update or data memory update among control signals is realized. Also,
When IF_HZD is “1”, the instruction memory I
NO to execute nothing instead of the value read from MEM
A selection means MUX for writing data corresponding to the P instruction into the instruction register IR is provided. These IF_HZD, ID
_HZD and EX_HZD change at the same timing as the control signal PC_SEL for writing the branch destination address to the program counter PC of the pipeline register PC / IF, so that the subsequent instructions 2, 3, at time 5 in FIG. 4 can be invalidated collectively (claim 7). To calculate the branch destination address, the relative address value transferred from the instruction register IR of the pipeline register IF / ID to the register I of the pipeline register ID / EX is used as the value of the program counter PC of the pipeline register ID / EX. The addition is stored in the program counter PC on the pipeline register EX / MEM, and when the control signal PC_SEL becomes “1”, the program counter P on the pipeline register PC / IF is
C.

By the way, all the instructions described so far are shown in FIG.
Although instructions are only executed in six pipeline cycles as in (a) and (b) of FIG. 5, some of the bit processing instructions unique to the programmable controller are as shown in FIG. Some execute instructions in six or more pipeline cycles. How many pipeline cycles are required varies depending on the instruction, but these instructions are different from the usual case in which memory access occurs only once as shown in FIG. b)
As shown in (1), a plurality of memory accesses occur. LO
For the AD and STORE instructions, the address calculation for memory access is a simple addition of the register value and the immediate data in the instruction word, so the address calculation is performed by the ALU, but the bit processing instruction is more complicated. As shown in the seventh embodiment in FIG.
A dedicated address calculation block BPUADR is provided instead of U.

In FIG. 17, of the six-stage pipeline structure,
Of the three stages of EX, MEM, and WB (BPU), a portion particularly relating to data memory access is shown. In the EX stage of FIG. 17, a LOAD instruction or S
ALU for which memory address was calculated by TORE instruction
Separately, an address calculation block BPUADR dedicated to a bit processing instruction is provided.
, But the output of BPUADR is used for the address for memory access. Therefore, the multiplexer M
A UX is provided to select the output of the ALU and the output of the BPUADR, and write it to the address portion AD of the pipeline register EX / MEM. In the bit processing instruction, an address for memory access is calculated by an address calculation block BPUADR dedicated to the bit processing instruction, and is written to the address portion AD of the pipeline register EX / MEM via the multiplexer MUX. When the memory access is a read, the memory read control signal RD of the pipeline register EX / MEM is set to “1”. When the memory access is a write, the memory of the pipeline register EX / MEM is set. The write control signal WT is set to “1”. As described above, in the bit processing instruction, the address calculation block BPUADR dedicated to the bit processing instruction stores the address AD of the data memory DMEM.
DR is calculated, and a read control signal RD or a write control signal WT is issued. In addition, LOAD instruction and STORE instruction
In the instruction, the memory address is calculated by the ALU, and the pipeline register EX is output via the multiplexer MUX.
Write to the address portion AD of / MEM. In the case of the LOAD instruction, the memory read control signal RD of the pipeline register EX / MEM becomes "1", and in the case of the STORE instruction, the memory write control signal WT of the pipeline register EX / MEM becomes "1". .

In addition to the value calculated in the EX pipeline cycle, a block B for executing a bit processing instruction
The PU issues the address ADDR and write value WTDT of the data memory DMEM and the control signals RD and WT of the memory, and the MEM stage is provided with a data path through which the memory access can be executed based on the data. FIG.
7, the control signals RD and WT of the memory mean “execute when“ 1 ””, and the pipeline register EX
The value of the memory control signal WT or RD on / MEM is "0"
However, the memory access can be executed by issuing a memory access request from the bit processing instruction execution circuit block BPU. That is, the bit processing instruction execution circuit block BPU is
Is read, the multiplexer MUX is switched so that the bit processing instruction execution circuit block BPU is replaced with the address part AD of the pipeline register EX / MEM.
, A memory address ADDR to the data memory DM, and a memory read control signal RD from the bit processing instruction execution circuit block BPU to the data memory DM via an OR gate. Thereby, the data memory DM
The data RDDT read from the EM is input to the bit processing instruction execution circuit block BPU via the pipeline register MEM / WB. When writing data from the bit processing instruction execution circuit block BPU to the data memory DMEM, the multiplexer MUX is switched to replace the address part AD of the pipeline register EX / MEM with the data from the bit processing instruction execution circuit block BPU to the data memory DMEM. The address ADDR is given, and the multiplexer MUX is switched to replace the data part DT of the pipeline register EX / MEM,
The write data WTDT is given from the bit processing instruction execution circuit block BPU to the data memory DMEM.
A memory write control signal WT is applied from the bit processing instruction execution circuit block BPU to the data memory DMEM via the OR gate. This makes it possible to write data from the bit processing instruction execution circuit block BPU to the data memory DMEM.

The above time chart is shown in FIG. FIG. 16A shows a LOAD / STORE instruction, and FIG. 16B shows a bit processing instruction for reading three words from the data memory DMEM and writing three words when the instruction is executed. In FIG. 16A, address calculation is performed by the ALU in the EX stage, and Read / W of the memory is performed in the MEM stage.
writing. On the other hand, in FIG. 16B, the address is calculated in the BPUADR of the EX stage, and the memory read is performed in the MEM stage based on the value. Further, the BPUADR stores therein a part of the instruction word of the bit processing instruction necessary for the address calculation, and stores the MEM in the MEM.
Memory Re even in the pipeline cycle immediately after the stage
The address calculation is performed in the MEM stage following the EX stage and a memory read request is also issued so that the memory read request can be performed in the BPU1 stage.
running ad. One more word of memory Re
However, at the BPU1 stage, since the instruction word of the bit processing instruction moves on the pipeline register and reaches the BPU, the memory read of the BPU2 cycle issues all necessary signals from the BPU, Has been realized. In the subsequent three-word memory write, all necessary values are issued from the BPU, and the memory write over three cycles is executed.

As described above, in this embodiment, the address calculation block BPUADR dedicated to the bit processing instruction has a function of generating an address over a plurality of cycles and issuing a memory access request together. After the instruction is transferred on the pipeline register and reaches the WB stage, if a memory access is required, an address and write data for the memory access, and a Read request and a Write request are transmitted from the circuit block BPU executing the bit processing instruction. publish. Therefore, as in the memory access of the instruction execution operation described above, the memory can be accessed not only by the value of the pipeline register EX / MEM but also by the signal from the BPU.
9).

Such an instruction: For example, when executing a bit processing instruction that causes a large number of memory accesses as shown in FIG. 16B, the subsequent instruction does not access the data memory DMEM until the memory access itself is completed. Thus, it is necessary to suspend the execution of the subsequent instruction. FIG. 18 shows an operation timing chart of the eighth embodiment which realizes this function. Since instruction 1 in FIG. 18 performs memory access over six cycles from time 4 to time 10, execution of subsequent instruction 2 must be stopped so that memory access is performed after time 10. This execution control can be realized by utilizing the same configuration as in the fourth embodiment (FIG. 9). FIG. 19 shows a circuit configuration of the eighth embodiment. The difference from the fourth embodiment (FIG. 9) is that the input of the hazard detection unit HDU is control information relating to a bit processing instruction. As described above, the control signal indicating that the bit processing instruction requires a large number of memory accesses and must stop the execution of the subsequent instruction is transmitted to the pipeline register ID /
A control signal for transferring the data to EX, EX / MEM, and MEM / WB, and issuing a similar control signal from a circuit block BPU that executes a bit processing instruction as necessary, thereby stopping the update of the program counter PC. Signal PC_H
Control signal ID_HZ for stopping ZD and instruction decoding
D is issued to halt the execution of the instruction following the bit processing instruction for a required period (claims 10 and 11).

Incidentally, some instructions of the programmable controller do not always execute the instruction, but execute the instruction only when an instruction execution condition including a plurality of flags is satisfied. In the ninth embodiment, it is assumed that a certain instruction is executed when the following condition is satisfied.

[0041]

(Equation 1) Here, EXEFLG is a forced execution flag, ERRCNT
RL is an error flag, and these flags are present together with other flags in the flag register FR of FIG. BITACC is a flag updated by a bit processing instruction. This BITACC is updated at the end of the sixth stage of the pipeline operation or at a later timing as shown in FIG. 20 (b) or (c). . In the ninth embodiment, in order to control the execution of the instruction whose execution / non-execution depends on the instruction execution condition, the control signals ID_HZD, EX_HZ are determined based on the flags constituting the execution condition.
D is generated, and the result of decoding the instruction with the values of these signals is overwritten with “0” to realize the function of making the instruction non-executable. Also, among the flags constituting the execution condition, BIT
Since the ACC is updated later than the others, if there is a bit processing instruction that updates BITACC before an instruction whose execution / non-execution depends on the instruction execution condition, BITACC is updated. The pipeline operation is suspended so that the execution of the EX stage is not performed until that time. This is realized by a circuit configuration similar to that of the eighth embodiment (FIG. 19).

Although the description so far has focused only on the case where the dedicated hardware (processor) is executing the instruction, the instruction execution is started by the start request from the state where the dedicated hardware is stopped. Also, a circuit structure for stopping the operation when the stop condition is satisfied during execution of the instruction is required. FIG. 22 is a block diagram showing a configuration for performing control relating to the start / stop shown in FIG.
Shown in In this embodiment, the processor is activated by an externally supplied activation request signal, and the processor is stopped when a stop instruction is executed or when an external interrupt request is input. When a stop instruction is executed, it stops immediately, does not always stop when an interrupt request is input, executes the instruction until a stop mark appears in the instruction word, and the stop mark is attached After executing the instruction, it shall stop. When the stop instruction is executed, the value of the program counter PC after the stop is assumed to be the address of the stop instruction itself, and when stopping by an interrupt request, the value is the address of the instruction next to the instruction with the stop mark. And

Such a start / stop operation is realized by a state machine denoted by STM in FIG. FIG. 23 shows the state transition of the state machine. At power-on or reset, the state of the state machine is ID
When set to LE and a start request is given, the state becomes S0
To execute the instruction. While the state is S0, the dedicated hardware (processor) continues to execute the instruction, but when the stop instruction is executed, the state changes to S11, and S12,
The procedure necessary for the stop is executed during the state change from S13, and further the state changes to IDLE, and the processor stops. If an interrupt request is input while the state is S0 and an instruction is being executed, the state changes to S21, and the execution of the instruction with the stop mark is waited while the instruction is continuously executed. When the instruction with the stop mark is executed, the state of the state machine is changed to S22, S2.
After performing the necessary stop operation, the processor stops.

FIG. 24 shows a case in which a stop command is executed among these stop operations, and FIG. 25 shows a case in which a stop is caused by an interrupt request (claims 14, 15, and 16). In each figure, STATE indicates the state of the state machine STM. PC_HZD, IF_HZD, I
D_HZD and EX_HZD are hazard detection units HD
U is PC stage, IF stage, ID stage, EX
3 shows a hazard signal output for a stage.
PC_IF_PC indicates a PC on the pipeline register PC / IF, and IF_ID_IR indicates an IR on the pipeline register IF / ID.
PCWTRQ is a write request signal of the program counter PC, and PCKEEP is a program counter PC after stopping.
Are shown. In FIG. 24, ID_ST
OP is a signal indicating that it is determined that the instruction is a stop instruction as a result of decoding the instruction by the decoder DC in the ID stage. In FIG. 25, INTRQ is an interrupt request signal, and ID_END is a signal indicating that it is determined that the instruction has a stop mark as a result of instruction decoding by the decoder DC in the ID stage.

By the way, some instructions executed by the dedicated hardware (processor) cannot complete the operation within the time of the pipeline cycle and execute the operation using a plurality of pipeline cycles. is there. For example, an arithmetic operation such as multiplication or division, which requires a larger amount of operation than addition and subtraction, corresponds to such an instruction. FIG. 26 shows a circuit configuration of the eleventh embodiment for executing this type of instruction. FIG. 27 shows an operation timing chart thereof. In each figure, PC / IF is a pipeline register between the PC stage and the IF stage, IF / ID is a pipeline register between the IF stage and the ID stage, ID / EX is a pipeline register between the ID stage and the EX stage, EX / MEM means a pipeline register between the EX stage and the MEM stage, and MEM / WB means a pipeline register between the MEM stage and the WB stage.
Also, IMEM is an instruction memory, DMEM is a data memory, and REG. FILE is a register file, SUBAL
U is a sub-ALU, and EXALU is an A for executing an arithmetic operation instruction such as multiplication or division, which requires a larger amount of operation than addition and subtraction.
LU, EXALU REG. Is the EXALU argument S1,
This is a register for storing S2. Also, FS
M is a state machine for executing an arithmetic operation instruction such as multiplication or division, which requires a larger amount of operation than addition and subtraction.

The dedicated hardware (processor) shown in FIG.
In the above, when the instruction read out in the IF stage is decoded by the decoder DC in the ID stage and it is determined that the instruction is of a type that cannot execute the operation within the time of one stage of the pipeline, the decoder DC sets the state machine FS
The MULT_RQ_ID signal ("1" for one clock) is output to M, the hazard detection unit HDU, and the MULT_RQ section (control information of the multiplication request) of the pipeline register ID / EX. The state machine FSM that has received the MULT_RQ_ID signal starts operating from the immediately following clock, and outputs a MULT signal (“1”) indicating a multiplication instruction or the like to the hazard detection unit HDU during the M2 stage to the M7 stage. . It should be noted that the state machine FSM uses MULT_RQ_ID = "1" and M1
Moves to the stage, and indicates DONE = instruction execution completion
The state transits to the M5 stage with “1”. On the other hand, the MULT_RQ part of the pipeline register ID / EX provides the hazard detection unit HDU and the EXALU register with the MULT_RQ.
_RQ_EX signal. EXALU register is M
Data only when ULT_RQ_EX = "1" (argument S
1, S2). That is, while the state machine FSM operates and the operation is performed in the EXALU, arguments required for the operation are held in the EXALU register.

At this point, the hazard detection unit HDU receives the MULT_RQ_ID signal from the ID stage, the MULT signal from the state machine FSM, and the MULT_RQ_EX signal from the EX stage. The hazard detection unit HDU uses these signals, and according to the following relationship, the hazard signals HZD_PC, HZD_ID
Generate

HZD_PC = (MULT_RQ_ID)
or (MULT) or (MULT_RQ_EX) HZD_ID = (MULT) or (MULT_RQ_E)
X)

The HZD_PC signal is output from the hazard detection unit HDU to the PC stage. In the PC stage, the value of the program counter PC at the time of the rise of HZD_PC is continuously output while HZD_PC = “1”. As a result, the program counter PC immediately after the instruction that cannot execute the operation within the time of one stage of the pipeline is extended by a necessary cycle. However, in this state, the operation is executed for the instruction immediately after the instruction that cannot execute the operation within the time of one stage of the pipeline. Therefore, the hazard detection unit HDU outputs the HZD_ID signal to the multiplexer MUX of the ID stage. HZD
The multiplexer MUX receiving the _ID signal outputs “0” to the pipeline register ID / EX. E
ALU, SUB receiving this signal at X stage
The ALU does not execute the subsequent operation (EX = "0"). As described above, the arguments S1 and S2 are not updated while the operation is performed in the EXALU, and the subsequent instruction waits in the ID stage until the operation of the previous instruction is completed. become.

Dedicated hardware (processor) shown in FIG.
To process a preceding instruction (normal instruction), an instruction 1 that cannot execute an operation within one pipeline stage, a subsequent instruction 1 (an instruction that cannot execute an operation within one pipeline stage), and a subsequent instruction 2. FIG. 27 shows an operation timing chart in the case where the operation is performed.

As described above, among the instructions of the programmable controller, there are instructions that are not always executed but are executed only when an instruction execution condition is satisfied. FIG. 28 shows a twelfth embodiment in which the instruction for executing an operation using a plurality of pipeline cycles described in the eleventh embodiment is an instruction whose execution / non-execution depends on the instruction execution condition. FIG. 29 shows an operation timing chart thereof. In each figure, PC / IF is a pipeline register between the PC stage and the IF stage, and IF / ID.
Is a pipeline register between the IF stage and the ID stage, ID / EX is a pipeline register between the ID stage and the EX stage, and EX / MEM is an EX stage and the ME stage.
A pipeline register between M stages, MEM / WB, is a pipeline register between MEM stage and WB stage. Also, IMEM is an instruction memory, DMEM is a data memory, and REG. FILE is a register file, F
LAGREG is a flag register, SUBALU is sub-A
LU and EXALU are ALUs and EXs for executing arithmetic operation instructions, such as multiplication and division, which require more operation than addition and subtraction.
ALU REG. Is a register for storing arguments S1 and S2 of EXALU. The FSM is a state machine for executing an arithmetic operation instruction such as multiplication or division, which requires a larger amount of operation than addition and subtraction.

The dedicated hardware (processor) shown in FIG.
In the case where the non-execution condition is satisfied in the flag register FLAGREG, the output signal MULT_RQ_ID1 from the decoder DC in the ID stage becomes FLAGREG =
AND signal MULT_RQ_ID2 with “0” = “0”
Is transmitted to each part. As a result, the state machine FSM continues the IDLE state regardless of the decoded instruction. Also, a series of signals generated when processing an instruction that cannot execute an operation within the time of one stage of the pipeline is not generated. Therefore, the flag register FLAGRE
When the non-execution condition is satisfied in G, as shown in FIG. 29, an instruction (MULT instruction in the figure) that cannot execute an operation within the time of one stage of the pipeline is not executed, and the instruction is not executed on the pipeline like a normal instruction. (Claim 1
8). FIG. 29 is a diagram showing a case where the dedicated hardware (processor) of FIG.
FIG. 9 is an operation timing diagram when processing an instruction (MULT instruction), a subsequent instruction 1, and a subsequent instruction 2 that cannot execute an operation within the time of a stage;

[0053]

According to the configurations of claims 1 and 2, the time required for processing one pipeline cycle can be shortened, and the instruction execution time can be shortened. According to the configuration of claim 3,
A circuit that requires an operation to be completed in a shorter time than a pipeline cycle is required, and it is possible to prevent a situation in which the speed of the entire pipeline structure is hindered by the restriction of this circuit portion, and shorten the instruction execution time. be able to. According to the configuration of the fourth aspect, it becomes unnecessary to insert a NOP instruction for solving a hazard at the time of reading a general-purpose register, and the program size can be reduced. Further, the instruction execution time can be reduced as compared with the case where the NOP instruction is inserted.

According to the fifth aspect of the present invention, there is no need to insert a NOP instruction for solving a hazard when the LOAD instruction and the following instruction refer to a general-purpose register updated by the LOAD instruction, thereby reducing the program size. be able to. According to the configuration of claim 6, when the LOAD instruction and the subsequent instruction referring to the general-purpose register updated by the LOAD instruction are STORE instructions, it is not necessary to stop the STORE instruction, and the instruction execution time can be shortened. it can. According to the configuration of claim 7, NO for preventing execution of an illegal instruction when a branch condition is satisfied is established.
This eliminates the need for inserting a P instruction, thereby reducing the program size.

According to the eighth and ninth aspects, it is possible to efficiently execute an instruction without wasting a pipeline cycle. According to the tenth and eleventh aspects, it is possible to execute a subsequent instruction of the bit processing instruction without inconsistency without inserting a NOP instruction when the bit processing instruction performs memory access, and to reduce the program size. Can be smaller. Claim 12, 1
According to the configuration 3, an instruction execution condition composed of a plurality of flag values is determined, and a specific instruction is executed / non-executed such that the instruction is executed only when the instruction execution condition is satisfied in the instruction execution stage. Can be controlled without contradiction.

According to the configuration of claim 14, various stop conditions and specifications after stop can be satisfied. According to the configuration of claim 15, the specifications of the program counter at the time of stop can be easily satisfied. Claim 16
With the configuration described above, it is possible to prevent execution of an illegal instruction after the start of the stop operation. According to the configuration of claim 17, it is possible to easily implement an instruction that is difficult to complete the operation within the time of one pipeline stage. According to the configuration of the eighteenth aspect, it is possible to prevent unnecessary stoppage of the pipeline operation when an instruction execution condition of an instruction that is difficult to complete the operation within one pipeline stage is not satisfied. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a programmable controller having a six-stage pipeline configuration according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart according to the first embodiment of the present invention.

FIG. 3 is an operation timing chart when a plurality of clocks of a conventional example are used.

FIG. 4 is an operation timing chart according to the second embodiment of the present invention.

FIG. 5 is a block diagram illustrating an overall circuit configuration according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a main circuit configuration according to a third embodiment of the present invention.

FIG. 7 is an operation timing chart according to a third embodiment of the present invention.

FIG. 8 is an operation timing chart for explaining a problem to be solved in a fourth embodiment of the present invention.

FIG. 9 is a block diagram illustrating an overall circuit configuration according to a fourth embodiment of the present invention.

FIG. 10 is an operation timing chart according to the fourth embodiment of the present invention.

FIG. 11 is an operation timing chart according to the fifth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a main circuit configuration according to a fifth embodiment of the present invention.

FIG. 13 is an operation timing chart according to the sixth embodiment of the present invention.

FIG. 14 is a block diagram illustrating an overall circuit configuration according to a sixth embodiment of the present invention.

FIG. 15 is a first operation timing chart according to the seventh embodiment of the present invention.

FIG. 16 is a second operation timing chart according to the seventh embodiment of the present invention.

FIG. 17 is a block diagram illustrating a main circuit configuration according to a seventh embodiment of the present invention.

FIG. 18 is an operation timing chart according to the eighth embodiment of the present invention.

FIG. 19 is a block diagram illustrating a main circuit configuration according to an eighth embodiment of the present invention.

FIG. 20 is an operation timing chart according to the ninth embodiment of the present invention.

FIG. 21 is a block diagram illustrating a main circuit configuration according to a ninth embodiment of the present invention.

FIG. 22 is a block diagram illustrating an overall circuit configuration according to a tenth embodiment of the present invention.

FIG. 23 is a state transition diagram of the tenth embodiment of the present invention.

FIG. 24 is an operation timing chart when a stop instruction is executed according to the tenth embodiment of the present invention.

FIG. 25 is an operation timing chart when the operation is stopped by an interrupt request according to the tenth embodiment of the present invention.

FIG. 26 is a block diagram illustrating an overall circuit configuration according to an eleventh embodiment of the present invention.

FIG. 27 is an operation timing chart of the eleventh embodiment of the present invention.

FIG. 28 is a block diagram illustrating an overall circuit configuration according to a twelfth embodiment of the present invention.

FIG. 29 is an operation timing chart of the twelfth embodiment of the present invention.

FIG. 30 is a block diagram showing a schematic configuration of a conventional programmable controller having a five-stage pipeline configuration.

FIG. 31 is an operation timing chart of the conventional example.

[Explanation of symbols]

IMEM instruction memory DMEM data memory PC program counter ALU arithmetic logic unit DC instruction decoder RF register file BPU bit processing instruction execution circuit block BITACC bit accumulator BPUADR Address calculation block dedicated to bit processing instruction

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B013 AA00 BB18 DD00 5B033 AA03 AA13 CA22 CA25 5H220 BB03 CC03 CC05 CX01 EE04 EE07 EE14 FF07 JJ16 JJ34

Claims (18)

[Claims] 1. A programmable controller that performs basic bit processing operation and multi-bit application processing, performs an instruction execution stage, a first stage that updates a program counter, and an instruction fetch process that fetches an instruction from an instruction memory. A second stage, a third stage for performing instruction decoding and register fetch processing for extracting a value from a general-purpose register, a fourth stage for performing an arithmetic logic operation or data address calculation, or a branch calculation for calculating an effective address of a branch destination, A fifth stage for performing a memory access process or a branch process for a memory, and a sixth stage for performing a bit operation process or a write process to the general-purpose register, wherein the six stages are operated in a pipeline. Programmable controller. 2. A hardware corresponding to each instruction execution stage of the pipeline processing includes a PC having a program counter, an IF having an instruction memory, an ID having an instruction decoder and a general-purpose register, and An EX unit having an arithmetic and logic unit ALU, a MEM unit having a data memory and a memory access interface for controlling access to the data memory, and a WB unit having a bit processing unit BPU for performing bit processing operation; In order to control the pipeline processing, a plurality of pipeline registers are provided between hardware corresponding to the instruction execution stages, and the execution results of the instruction execution stages and instruction execution specification information are stored in the pipeline registers. A programmable controller, characterized in that: 3. The programmable controller according to claim 2, wherein a single-phase clock signal is used as a clock signal for driving a sequential circuit inside the programmable controller such as a pipeline register, a general-purpose register, and a program counter. controller. 4. The programmable controller according to claim 2, wherein an output of said general-purpose register of said third stage as an input of said arithmetic and logic unit ALU of said fourth stage, and said A taken into said fifth stage.
LU output, the AL captured in the sixth stage
A programmable controller comprising selection means for selecting one of the outputs of U. 5. The programmable controller according to claim 1, wherein when data taken in by a LOAD instruction is required in an instruction subsequent to the LOAD instruction, the data fetched by the LOAD instruction is written in the general-purpose register. , LOA after the LOAD instruction
A programmable controller having a function of stopping execution of an instruction that refers to a value of a general-purpose register updated by a D instruction. 6. An instruction subsequent to the LOAD instruction is STORE.
If the general-purpose register required by the STORE instruction is updated by a LOAD instruction, the data stored in the general-purpose register in the sixth stage of the LOAD instruction is replaced by the fifth or fourth stage of the STORE instruction. By taking in the stage and writing to the data memory, S
6. The programmable controller according to claim 5, having a function of not stopping execution of the TORE instruction. 7. The programmable controller according to claim 1, further comprising a function of suppressing execution of an invalid instruction already entered in a pipeline when a branch condition is satisfied during execution of a branch instruction. A programmable controller. 8. The programmable controller according to claim 1, wherein the LOAD instruction or the STOR
In addition to an arithmetic and logic operation block ALU for performing an address calculation when a memory access instruction such as an E instruction is executed, an address calculation block dedicated to a bit processing instruction for executing a bit processing instruction is provided. A programmable controller having a function of performing a memory access in a plurality of continuous pipeline stages by causing an address of a data memory to be calculated over a pipeline cycle and issuing a memory access request. 9. A dedicated circuit block for executing a bit processing instruction, and issues a memory address and a memory read request or a memory address and a memory write data and a memory write request from the circuit block. 9. The programmable controller according to claim 8, wherein the programmable controller has a function of executing reading / writing from / to the memory. 10. A program signal is provided on a pipeline register to indicate that the instruction is a bit processing instruction, and when it is necessary to stop execution of an instruction following the bit processing instruction, the program counter is incremented. 9. The programmable controller according to claim 8, further comprising a function of stopping the execution of an instruction subsequent to the bit processing instruction by stopping the execution of the instruction and, if necessary, rewriting the instruction execution specification information as a result of decoding the instruction. . 11. A program counter which is provided with a dedicated circuit block for executing a bit processing instruction and which issues a control signal from the circuit block to stop execution of an instruction following the bit processing instruction. 9. The function according to claim 8, further comprising the step of stopping the execution of the instruction following the bit processing instruction by stopping the increment of the bit processing instruction and rewriting the instruction execution specification information as a result of decoding the instruction as necessary. Programmable controller. 12. The programmable controller according to claim 1, wherein an instruction execution condition composed of a plurality of flag values is determined, and a specific instruction is executed in the fourth stage which is an instruction execution stage. A programmable controller characterized by executing an instruction only when it is satisfied. 13. A bit which is updated by a bit processing instruction for performing bit operation processing in the sixth stage and constitutes an instruction execution condition, and the corresponding instruction updates a flag relating to the instruction execution condition on the pipeline register. A control signal indicating a processing instruction is provided, and execution of the instruction is stopped while the instruction execution condition is not determined based on the control signal. 13. The programmable controller according to claim 12, having a structure for executing. 14. The programmable controller according to claim 1, further comprising a state machine for performing start / stop control for executing a stop operation based on various stop conditions as required by specifications. Features a programmable controller. 15. A state machine for controlling start / stop for transferring the value of a program counter at the time of instruction fetch to a pipeline register and calculating the value of the program counter at the time of stop is transferred to the pipeline. 15. The program counter according to claim 14, wherein the value of the program counter is read, the value of the program counter at the time of stop is calculated based on the value according to the stop specification, and the calculated value is written to the program counter before the stop. 4. The programmable controller according to 1. 16. A function having a function of invalidating the execution of an instruction already input to a pipeline and preventing execution of an illegal instruction when a stop condition is satisfied and a stop operation is started. Item 15. The programmable controller according to item 14. 17. The programmable controller according to claim 1, wherein when executing an instruction whose operation cannot be completed within one pipeline stage, the operation is terminated from an operation block executing the instruction. By stopping the increment of the program counter until the signal arrives or for the time required for the completion of the operation of the instruction set in advance by the instruction, and disabling control signals such as register write back and data memory write, A programmable controller configured to stop a pipeline operation and execute the instruction. 18. The programmable controller according to claim 1, further comprising a flag for determining whether to execute or not to execute an instruction whose operation cannot be completed within one pipeline stage. The programmable controller is configured such that when the value of the flag is non-execution, the execution of the instruction is not started and the operation of the pipeline is not stopped.