JP2001005030A - Display panel and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In a liquid crystal display panel in which a pixel electrode is formed on an overcoat film covering a thin film transistor, an auxiliary capacitance value per unit area is increased to increase an aperture ratio. A pixel electrode is provided on an overcoat film. In this case, the pixel electrode 15 is provided on the gate insulating film 6 because the opening 17 is provided in the overcoat film 14 in the central part except the peripheral part of the auxiliary capacitance electrode 4. Therefore, it is possible to increase the auxiliary capacitance per unit area in the opening 17 of the overcoat film 14. As a result, even if the degree of overlap between the auxiliary capacitance electrode 4 and the pixel electrode 15 is reduced to some extent, a necessary auxiliary capacitance value can be secured, and the aperture ratio can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel such as a liquid crystal display panel and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, some active matrix type liquid crystal display panels have an auxiliary capacitance portion in addition to a pixel capacitance portion. FIG. 19 is a plan view of a part of an example of such a conventional liquid crystal display panel, and FIG. 20 is a cross-sectional view taken along line XX. This liquid crystal display panel has a glass substrate 1. A scanning line 3 including a gate electrode 2 made of aluminum is provided at a predetermined location on the upper surface of the glass substrate 1 so as to extend in the row direction. 5 are provided extending in the row direction, and a gate insulating film 6 made of silicon nitride is provided on the entire upper surface thereof.

A semiconductor thin film 7 made of amorphous silicon is provided on a portion corresponding to the gate electrode 2 at a predetermined position on the upper surface of the gate insulating film 6. At the center of the upper surface of the semiconductor thin film 7, a blocking layer 8 made of silicon nitride is provided. Ohmic contact layers 9 and 10 made of n ⁺ silicon are provided on both sides of the upper surface of the blocking layer 8 and on the upper surface of the semiconductor thin film 7 on both sides thereof. A source electrode 11 made of chromium is provided at predetermined positions on the upper surface of one ohmic contact layer 9 and the upper surface of the gate insulating film 6. A signal line 13 including a drain electrode 12 made of chromium is provided at predetermined locations on the upper surface of the other ohmic contact layer 10 and the upper surface of the gate insulating film 6.
Are provided extending in the row direction. An overcoat film 14 made of silicon nitride is provided on the entire upper surface. A predetermined portion of the upper surface of the overcoat film 14
A pixel electrode 15 made of TO is provided. The pixel electrode 15 is connected to the source electrode 11 via a contact hole 16 provided at a predetermined location on the overcoat film 14.

The lower side of the pixel electrode 15 in FIG. 19 is overlapped with the auxiliary capacitance electrode 4, and the overlapped portion forms an auxiliary capacitance portion. on the other hand,
Although not shown, the pixel capacitance portion is formed by the pixel electrode 15, a common electrode disposed opposite to the pixel electrode 15, and liquid crystal interposed therebetween.

Next, a method of manufacturing the liquid crystal display panel will be described. First, as shown in FIG. 21, a scanning line 3 including the gate electrode 2 and an auxiliary capacitance line 5 including the auxiliary capacitance electrode 4 are formed at predetermined positions on the upper surface of the glass substrate 1 by using aluminum. Next, a gate insulating film 6 made of silicon nitride, a semiconductor layer 7A made of amorphous silicon, and a blocking layer forming layer 8A made of silicon nitride are successively formed on the entire upper surface. Next, a photoresist film 21 is formed in the blocking layer formation region on the upper surface of the blocking layer formation layer 8A. Next, the photoresist film 2
The blocking layer forming layer 8A is etched using 1 as a mask. Then, as shown in FIG. 22, the semiconductor layer 7A
A blocking layer 8 is formed in a portion corresponding to the gate electrode 2 at a predetermined location on the upper surface of the substrate. Thereafter, the photoresist film 21 is peeled off.

Next, as shown in FIG. 23, n
⁺ Ohmic contact layer forming layer 9 made of silicon
A is formed. Next, a photoresist film 22 is formed in the ohmic contact layer forming region on the upper surface of the ohmic contact layer forming layer 9A. Next, the photoresist film 2
2 as a mask for forming ohmic contact layer 9A
Then, the semiconductor layer 7A is etched. Then, as shown in FIG. 24, a semiconductor thin film 7 is formed on a portion corresponding to the gate electrode 2 at a predetermined location on the upper surface of the gate insulating film 6, and the semiconductor thin films 7 on both sides of the upper surface of the blocking layer 8 and on both sides thereof. Ohmic contact layers 9 and 10 are formed on the upper surface of the substrate. Thereafter, the photoresist film 22 is peeled off.

Next, as shown in FIG. 25, a source electrode 11 made of chromium is formed at predetermined positions on the upper surface of one ohmic contact layer 9 and the upper surface of the gate insulating film 6, and the other ohmic contact layer 10 is formed. A signal line 13 including a drain electrode 12 made of chromium is formed on a predetermined portion of the upper surface of the gate insulating film 6 and the upper surface of the gate insulating film 6. Next, an overcoat film 14 made of silicon nitride is formed on the entire upper surface. Next, a photoresist film 23 for forming a contact hole is formed on the upper surface of the overcoat film 14.
Next, the overcoat film 14 is etched using the photoresist film 23 as a mask. Then, as shown in FIG. 26, contact holes 16 are formed at predetermined locations in overcoat film 14. After this, the photoresist film 2
3 is peeled off. Next, as shown in FIGS. 19 and 20,
A pixel electrode 15 made of ITO is formed at a predetermined position on the upper surface of the overcoat film 14 by being connected to the source electrode 11 via a contact hole 16. Thus, the liquid crystal display panel is manufactured.

[0008]

Incidentally, in such a conventional liquid crystal display panel, the auxiliary capacitance electrode 4 and the pixel electrode 15 are overlapped with each other, that is, the auxiliary capacitance electrode 4 and the pixel electrode 15 and the gate therebetween. Since the storage capacitor portion is formed by the insulating film 6 and the overcoat film 14, the distance between the storage capacitor electrode 4 and the pixel electrode 15, that is, the total thickness of the two films 6, 14 is relatively large, and as a result, The auxiliary capacitance value per unit area becomes small. Therefore, in order to secure a necessary storage capacitance value, the degree of overlap between the storage capacitance electrode 4 and the pixel electrode 15 may be increased. In this case, the storage capacitance electrode 4 is formed of aminium, that is, a non-permeable metal. Therefore, there is a problem that the aperture ratio is reduced. An object of the present invention is to increase an auxiliary capacitance value per unit area.

[0009]

According to a first aspect of the present invention, there is provided a display panel in which a pixel electrode is provided on a storage capacitor electrode provided on a substrate via a lower insulating film and an upper insulating film. , An opening is provided in the upper insulating film in a region corresponding to a part of the storage capacitor electrode, and a part of the pixel electrode is provided in the opening. 7. The method of manufacturing a display panel according to claim 6, wherein an auxiliary capacitance electrode, a lower insulating film, and an upper insulating film are formed on a substrate, and the upper insulating film is formed in a region corresponding to a part of the auxiliary capacitance electrode. An opening is formed, and a pixel electrode is formed on the upper insulating film including the inside of the opening. According to this invention, even if the pixel electrode is provided on the upper insulating film, the pixel electrode is provided on the auxiliary capacitance electrode via the lower insulating film in the opening portion of the upper insulating film. Can increase the auxiliary capacitance value per unit area in the opening portion.

[0010]

(First Embodiment) FIG. 1 is a plan view of a main part of a liquid crystal display panel according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX. It is a thing. In addition, for convenience of explanation, in FIG. 1 and FIG.
19 and 20 will be described with the same reference numerals. This liquid crystal display panel is largely different from the cases shown in FIGS. 19 and 20 in that:
A part of the overlapping portion of the auxiliary capacitance electrode 4 and the pixel electrode 15 is constituted by the auxiliary capacitance electrode 4, the pixel electrode 15, and the gate insulating film 6 therebetween.

Next, the structure of the liquid crystal display panel according to the first embodiment will be described together with its manufacturing method. In this case, the steps up to the formation of the ohmic contact layer forming layer 9A in FIG. 23 are the same as those in the above-described conventional case, and the subsequent steps will be described. As shown in FIG. 3, a photoresist film 31a is formed in the ohmic contact layer forming region on the upper surface of the ohmic contact layer forming layer 9A.
And a layer 9 for forming an ohmic contact layer.
A predetermined portion of the auxiliary capacitance electrode 4 on the upper surface of A (the central portion excluding the peripheral portion of the rectangular auxiliary capacitance electrode 4 shown in FIG. 1)
A photoresist film 31b is formed in a region corresponding to.

Next, the ohmic contact layer forming layer 9A and the semiconductor layer 7A are etched using the photoresist films 31a and 31b as a mask. Then, as shown in FIG. 4, a semiconductor thin film 7 is formed in a portion corresponding to the gate electrode 2 at a predetermined position on the upper surface of the gate insulating film 6, and
Ohmic contact layers 9 and 10 are formed on both sides of the upper surface of the blocking layer 8 and on the upper surface of the semiconductor thin film 7 on both sides thereof. Further, a semiconductor thin film 7a for barrier and an ohmic contact layer 9a for barrier are formed on the upper surface of the gate insulating film 6 under the photoresist film 31b. Thereafter, the photoresist films 31a and 31b are peeled.

Next, as shown in FIG. 5, a source electrode 11 made of chromium is formed at predetermined positions on the upper surface of one ohmic contact layer 9 and the upper surface of the gate insulating film 6, and the other ohmic contact layer 10 is formed. A signal line 13 including a drain electrode 12 made of chromium is formed on a predetermined portion of the upper surface of the gate insulating film 6 and the upper surface of the gate insulating film 6. Thus,
An inverted staggered thin film transistor including the gate electrode 2, the gate insulating film 6, the semiconductor thin film 7, the ohmic contact layers 9, 10, the source electrode 11, and the drain electrode 12 is formed. Next, the overcoat film 14 made of silicon nitride is formed on the entire upper surface of the thin film transistor formed as described above and the gate insulating film 6 outside the region of the thin film transistor.
Is formed. Next, a photoresist film 32 is formed on the upper surface of the overcoat film 14. In this case, the source electrode 1
An opening 32a is formed in a portion of the photoresist film 32 corresponding to a predetermined portion of the photoresist film 32, and a portion of the photoresist film 32 corresponding to a central portion excluding a peripheral portion of the planar ohmic contact layer 9a for barrier is formed. Is formed with an opening 32b.

Next, using the photoresist film 32 as a mask, the overcoat film 14, the barrier ohmic contact layer 9a and the barrier semiconductor thin film 7a are removed by plasma etching. In this case, the overcoat film 14
Etching is performed using a mixed gas of SF ₆ and O ₂ as an etching gas, and etching of the barrier ohmic contact layer 9a and the barrier semiconductor thin film 7a is performed using a mixed gas of Cl, SF ₆ and H ₂ as an etching gas. In this way, when etching the overcoat film 14 made of silicon nitride, the barrier ohmic contact layer 9a
Further, since the barrier semiconductor thin film 7a becomes an etching barrier layer, it is possible to prevent the gate insulating film 6 made of silicon nitride from being etched or damaged. In this way, as shown in FIG. 6, the contact hole 16 is formed in the overcoat film 14 at the opening 32a of the photoresist film 32, and at the same time, the contact hole 16 is formed at the opening 32b of the photoresist film 32. The overcoat film 14, the barrier ohmic contact layer 9a and the barrier semiconductor thin film 7a are removed, and an opening 17 is formed. In this state, the ohmic contact layer for barrier 9a and the semiconductor thin film for barrier 7a serve as an etching barrier layer when the overcoat film 14 is etched as described above. Ohmic contact layer 9 for barrier
a and a size that can be accommodated in the region of the barrier semiconductor thin film 7a. Therefore, as shown in FIG.
The barrier semiconductor thin film 7a and the barrier ohmic contact layer 9a are left in a frame shape between the gate insulating film 6 and the overcoat film 14 around the opening 17 (see FIG. 1). Thereafter, the photoresist film 32 is stripped.

Next, as shown in FIGS. 1 and 2, a pixel electrode 15 made of ITO is formed at a predetermined position on the upper surface of the overcoat film 14 by being connected to the source electrode 11 through the contact hole 16. In this case, the pixel electrode 15 is formed on the upper surface of the gate insulating film 6 in the opening 17. Thus, the liquid crystal display panel according to the first embodiment is manufactured.

In the liquid crystal display panel thus obtained, even if the pixel electrode 15 is provided on the overcoat film 14, the gate insulating film is formed on the auxiliary capacitance electrode 4 at the opening 17 of the overcoat film 14. Since the pixel electrode 15 is provided only through the gate electrode 6, the auxiliary capacitance per unit area in the opening 17 of the overcoat film 14 can be increased. As a result, the auxiliary capacitance electrode 4
Even if the degree of overlap between the pixel electrode 15 and the pixel electrode 15 is reduced to a certain extent, a necessary auxiliary capacitance value can be secured, and the aperture ratio can be increased.

(Second Embodiment) Next, a structure of a liquid crystal display panel according to a second embodiment of the present invention will be described together with a manufacturing method thereof. In this case, the steps up to the formation of the blocking layer forming layer 8A made of silicon nitride in FIG. As shown in FIG. 7, a photoresist film 33a is formed in the blocking layer formation region on the top surface of the blocking layer formation layer 8A, and a central portion of the top surface of the blocking layer formation layer 8A excluding the peripheral portion of the auxiliary capacitance electrode 4 is formed. Is formed in a region corresponding to.

Next, the blocking layer forming layer 8A is etched using the photoresist films 33a and 33b as a mask. Then, as shown in FIG. 8, a blocking layer 8 is formed in a portion corresponding to the gate electrode 2 at a predetermined position on the upper surface of the semiconductor layer 7A. Also, the photoresist film 33b
A barrier blocking layer 8a is formed on the upper surface of the lower semiconductor layer 7A. After this, the photoresist film 33
a and 33b are peeled off.

Next, as shown in FIG. 9, an ohmic contact layer forming layer 9A is formed on the entire upper surface. Next, a photoresist film 34 is formed in the ohmic contact layer formation region on the upper surface of the ohmic contact layer formation layer 9A. Next, the ohmic contact layer forming layer 9A and the semiconductor layer 7A are etched using the photoresist film 34 and the barrier blocking layer 8a as a mask. Then
As shown in FIG. 10, a semiconductor thin film 7 is formed on a portion corresponding to the gate electrode 2 at a predetermined position on the upper surface of the gate insulating film 6, and both upper surfaces of the blocking layer 8 and upper surfaces of the semiconductor thin films 7 on both sides thereof Ohmic contact layer 9,
10 are formed. In addition, barrier blocking layer 8a
A barrier semiconductor thin film 7a is formed on the upper surface of the gate insulating film 6 below. Thereafter, the photoresist film 34 is peeled off.

Next, as shown in FIG. 11, a source electrode 11 made of chromium is formed at a predetermined position on the upper surface of one ohmic contact layer 9 and the upper surface of the gate insulating film 6, and the other ohmic contact layer 10 is formed. A signal line 13 including a drain electrode 12 made of chromium is formed on a predetermined portion of the upper surface of the gate insulating film 6 and the upper surface of the gate insulating film 6. Next, an overcoat film 14 made of silicon nitride is formed on the entire upper surface. Next, a photoresist film 35 is formed on the upper surface of the overcoat film 14. Also in this case, the source electrode 1
An opening 35a is formed in a portion of the photoresist film 35 corresponding to a predetermined portion of the photoresist film 35, and a portion of the photoresist film 35 corresponding to a central portion excluding a peripheral portion of the planar rectangular barrier blocking layer 8a is formed. Has an opening 35b.

Next, using the photoresist film 35 as a mask, the overcoat film 14, the barrier blocking layer 8a
Then, the semiconductor thin film for barrier 7a is etched. Then, as shown in FIG. 12, a contact hole 16 is formed in the overcoat film 14 at the opening 35a of the photoresist film 35. Also, the overcoat film 1 in the opening 35b of the photoresist film 35 is formed.
4. The barrier blocking layer 8a and the barrier semiconductor thin film 7a are removed, and an opening 17 is formed. In this state, the barrier semiconductor thin film 7 a and the barrier blocking layer 8 a remain in a frame shape between the gate insulating film 6 and the overcoat film 14 around the opening 17. In this case, as in the first embodiment, in this embodiment, the overcoat film 14 made of silicon nitride is also used.
When the barrier blocking layer 8a is etched, the barrier semiconductor thin film 7a made of amorphous silicon functions as an etching barrier layer to prevent the gate insulating film 6 made of silicon nitride from being etched. Thereafter, the photoresist film 35 is peeled off.

Next, as shown in FIG. 13, a pixel electrode 15 made of ITO is formed at a predetermined position on the upper surface of the overcoat film 14 by being connected to the source electrode 11 through the contact hole 16. Also in this case, in the opening 17, the pixel electrode 15 is formed on the upper surface of the gate insulating film 6. Thus, the liquid crystal display panel according to the second embodiment is manufactured. Also in this case, the same effect as in the case of the first embodiment can be obtained. The second
In the embodiment, the barrier blocking layer 8a and the barrier semiconductor thin film 7a are formed between the overcoat film 14 and the gate insulating film 6, but the barrier blocking layer 8a is formed by the overcoat film 14 and the gate insulating film. When formed of a material different from the film 6, the barrier semiconductor thin film 7a is not formed, and only the barrier blocking layer 8a can be used.

(Third Embodiment) Next, a structure of a liquid crystal display panel according to a third embodiment of the present invention will be described together with a manufacturing method thereof. In this case, the steps until the photoresist film 22 is stripped in FIG. 24 are the same as those in the above-described conventional case, and the subsequent steps will be described. FIG.
As shown in the figure, a metal layer 11A made of chromium
Is formed. Next, a photoresist film 36a is formed in the signal line formation region including the source electrode formation region and the drain electrode on the upper surface of the metal layer 11A. In addition, a photoresist film 36b is formed in a region corresponding to a central portion of the upper surface of the metal layer 11A except for a peripheral portion of the auxiliary capacitance electrode 4.

Next, the metal layer 11A is etched using the photoresist films 36a and 36b as a mask. Then
As shown in FIG. 15, one ohmic contact layer 9
A source electrode 11 made of chromium is formed at a predetermined location on the upper surface of the gate insulating film 6 and a drain electrode made of chromium at a predetermined location on the other upper surface of the ohmic contact layer 10 and the upper surface of the gate insulating film 6. A signal line 13 including the electrode 12 is formed. A barrier metal layer 11a is formed on the upper surface of the gate insulating film 6 below the photoresist film 36b. Thereafter, the photoresist film 36
a and 36b are peeled off.

Next, as shown in FIG. 16, an overcoat film 14 made of silicon nitride is formed on the entire upper surface.
Next, a photoresist film 37 is formed on the upper surface of the overcoat film 14. In this case as well, an opening 37a is formed in the photoresist film 37 at a portion corresponding to a predetermined portion of the source electrode 11, and a portion corresponding to the central portion excluding the peripheral portion of the planar rectangular barrier metal layer 11a. An opening 37b is formed in the photoresist film 37 in FIG.

Next, the overcoat film 14 is etched using the photoresist film 37 as a mask. Then, as shown in FIG. 17, the opening 37 of the photoresist film 37 is formed.
A contact hole 16 is formed in the overcoat film 14 in the portion a. Further, the overcoat film 14 in the opening 37b of the photoresist film 37 is removed, and the opening 17 is formed. In this case, the barrier metal layer 11a is not etched, and therefore, the underlying gate insulating film 6 is not etched. Thereafter, the photoresist film 37 is peeled off.

Next, as shown in FIG. 18, a pixel electrode 15 made of ITO is formed at a predetermined position on the upper surface of the overcoat film 14 by being connected to the source electrode 11 via the contact hole 16. In this case, in the opening 17, the pixel electrode 15 is formed on the upper surface of the barrier metal layer 11a. Thus, the liquid crystal display panel according to the third embodiment is manufactured.

In the liquid crystal display panel thus obtained, even if the pixel electrode 15 is provided on the overcoat film 14, the gate insulating film is provided on the auxiliary capacitance electrode 4 in the opening 17 of the overcoat film 14. Since the barrier metal layer 11a and the pixel electrode 15 are provided only through the gate electrode 6, the barrier metal layer 11a forms an upper electrode together with the pixel electrode 15, so that the unit in the opening 17 of the overcoat film 14 can be formed. The storage capacitance value per area can be increased. As a result, even if the degree of overlap between the auxiliary capacitance electrode 4 and the pixel electrode 15 is reduced to some extent, a necessary auxiliary capacitance value can be secured, and the aperture ratio can be increased.

In the above-described embodiment, the case where the thin film transistor is an inverted staggered type having a bottom gate structure has been described. However, the present invention is also applicable to a coplanar or normal staggered type top gate type thin film transistor. It is possible. Further, although the embodiment in which the auxiliary capacitance electrode 4 is located at one end side of the pixel electrode 15 has been described, the auxiliary capacitance electrode 4 may be arranged at the center of the pixel electrode 15 or the shape of the auxiliary capacitance electrode 4 may be changed around the pixel electrode 15. May be U-shaped or frame-shaped so as to enclose.

[0030]

As described above, according to the present invention, even if the pixel electrode is provided on the upper insulating film, the auxiliary capacitor electrode is provided on the opening portion of the upper insulating film via the lower insulating film via the lower insulating film. Since the pixel electrode is provided, the auxiliary capacitance per unit area in the opening portion of the upper insulating film can be increased, and the aperture ratio can be increased.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX of FIG. 1;

FIG. 3 is a cross-sectional view showing predetermined steps in manufacturing the liquid crystal display panel shown in FIGS. 1 and 2.

FIG. 4 is a sectional view showing a step following FIG. 3;

FIG. 5 is a sectional view showing a step following FIG. 4;

FIG. 6 is a sectional view showing a step following FIG. 5;

FIG. 7 is a sectional view showing a predetermined step in manufacturing the liquid crystal display panel according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a step following FIG. 7;

FIG. 9 is a sectional view showing a step following FIG. 8;

FIG. 10 is a sectional view showing a step following FIG. 9;

FIG. 11 is a sectional view showing a step following FIG. 10;

FIG. 12 is a sectional view showing a step following FIG. 11;

FIG. 13 is a sectional view showing a step following FIG. 12;

FIG. 14 is a sectional view showing a predetermined step in manufacturing the liquid crystal display panel according to the third embodiment of the present invention.

FIG. 15 is a sectional view showing a step following FIG. 14;

FIG. 16 is a sectional view showing a step following FIG. 15;

FIG. 17 is a sectional view showing a step following FIG. 16;

FIG. 18 is a sectional view showing a step following FIG. 17;

FIG. 19 is a partial plan view of an example of a conventional liquid crystal display panel.

FIG. 20 is a sectional view taken along the line XX in FIG. 19;

FIG. 21 is a sectional view showing an initial step in manufacturing the liquid crystal display panel shown in FIGS. 19 and 20.

FIG. 22 is a sectional view showing a step following FIG. 21;

FIG. 23 is a sectional view showing a step following FIG. 22;

FIG. 24 is a sectional view showing a step following FIG. 23;

FIG. 25 is a sectional view showing a step following FIG. 24;

FIG. 26 is a sectional view showing a step following FIG. 25;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Scanning line 4 Auxiliary capacitance electrode 5 Auxiliary capacitance line 6 Gate insulating film 7 Semiconductor thin film 8 Blocking layer 9, 10 Ohmic contact layer 11 Source electrode 12 Drain electrode 13 Signal line 14 Overcoat film 15 Pixel electrode 16 Contact hole 17 Opening 7a Barrier semiconductor thin film 8a Barrier blocking layer 9a Barrier ohmic contact layer 11a Barrier metal layer

Continued on the front page F term (reference) 2H092 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB51 JB56 JB63 JB69 KA05 KA07 KA16 KA18 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA35 MA37 MA41 NA24 NA25 NA27 QA27 NA06

Claims (9)

[Claims] In a display panel in which a pixel electrode is provided on a storage capacitor electrode provided on a substrate via a lower insulating film and an upper insulating film, an upper layer of a region corresponding to a part of the storage capacitor electrode is provided. A display panel, wherein an opening is provided in an insulating film, and a part of the pixel electrode is provided in the opening. 2. The invention according to claim 1, wherein a thin film transistor is connected to the pixel electrode, and an etching barrier layer is provided between the lower insulating film and the upper insulating film around the opening. A display panel characterized by the following. 3. The invention according to claim 1, wherein a thin film transistor is connected to the pixel electrode, and a barrier semiconductor thin film is provided between the lower insulating film and the upper insulating film around the opening. A display panel, characterized in that: 4. The display panel according to claim 1, wherein a metal layer is provided between the lower insulating film and the pixel electrode in and around the opening. 5. The display according to claim 4, wherein a thin film transistor is connected to the pixel electrode, and the metal layer is formed of the same metal material as a source electrode and a drain electrode of the thin film transistor. panel. 6. An auxiliary capacitor electrode, a lower insulating film and an upper insulating film are formed on a substrate, an opening is formed in the upper insulating film in a region corresponding to a part of the auxiliary capacitor electrode, and the inside of the opening is formed. A method for manufacturing a display panel, comprising forming a pixel electrode on the upper insulating film. 7. A step of forming a gate electrode and an auxiliary capacitance electrode on a substrate, a step of forming a gate insulating film, and forming a semiconductor thin film on the gate insulating film on the gate electrode and the auxiliary capacitance electrode A step of forming a barrier semiconductor thin film on the gate insulating film, a step of forming a source electrode and a drain electrode, a step of forming an overcoat film, and a portion corresponding to a predetermined part of the source electrode Forming a contact hole in the overcoat film and forming an opening in the overcoat film and the barrier semiconductor thin film in a region corresponding to a part of the auxiliary capacitance electrode, and Forming a pixel electrode on the coat film by connecting to the source electrode through the contact hole. And a method of manufacturing a display panel. 8. A step of forming a gate electrode and a storage capacitor electrode on a substrate, a step of forming a gate insulating film, and forming a semiconductor thin film and a blocking layer on the gate insulating film on the gate electrode, Forming a barrier blocking layer on the gate insulating film on the auxiliary capacitance electrode, forming a source electrode and a drain electrode, forming an overcoat film, and forming a predetermined portion of the source electrode Forming a contact hole in the overcoat film in a corresponding portion and forming an opening in the overcoat film and the barrier blocking layer in a region corresponding to a part of the auxiliary capacitance electrode; A pixel electrode is connected to the source electrode via the contact hole on the overcoat film including Forming a display panel. 9. A step of forming a gate electrode and an auxiliary capacitance electrode on a substrate, a step of forming a gate insulating film, and forming a semiconductor thin film, a blocking layer, and two ohmic contacts on the gate insulating film on the gate electrode. Forming a layer, forming a source electrode and a drain electrode, forming a metal layer on the gate insulating film on the auxiliary capacitance electrode, forming an overcoat film, Forming a contact hole in the overcoat film in a portion corresponding to a part of the metal layer, and forming an opening in the overcoat film in a portion corresponding to a central portion excluding a peripheral portion of the metal layer; A pixel electrode is connected to the source electrode via the contact hole on the overcoat film including A method of manufacturing a display panel.