JP2001004708A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device which incorporates an inspection auxiliary circuit capable of simultaneously inspecting a large number of devices with one inspection apparatus. A semiconductor device having a normal operation mode and a test mode, wherein a plurality of test signals for testing a plurality of internal cells included in the semiconductor device in the test mode are serially input to generate a plurality of test signals. Test signal supply means for sequentially supplying a plurality of internal cells to a corresponding plurality of internal cells, a plurality of switching means for electrically connecting or disconnecting the plurality of internal cells to a plurality of terminals, and a plurality of internal cells, A plurality of comparing means for comparing the output signals of the plurality of internal cells with a plurality of signals supplied from outside to the plurality of terminals when the plurality of terminals are disconnected from each other, and a determination for judging a comparison result of the plurality of comparing means. Means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly, to an inspection for facilitating inspection when inspecting a device to be inspected using an inspection apparatus (such as an IC tester) and a non-defective device. The present invention relates to a semiconductor device having a built-in auxiliary circuit.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor device is inspected using an inspection apparatus, the inspection is performed by connecting input / output pins of the inspection apparatus to respective terminals of a device to be inspected.
For this reason, the number of semiconductor devices that can be inspected simultaneously by one inspection device is limited by the number of pins of the inspection device and the number of terminals of the device to be inspected. For example, the number of input / output pins of the inspection apparatus is 512, and the number of terminals of the device under test is 256.
In this case, the number of semiconductor devices that can be inspected simultaneously by one inspection apparatus is two.

On the other hand, Japanese Patent Application Publication (JP-A-59-150441) discloses a semiconductor device having a structure capable of comparing and inspecting a non-defective device and a device to be inspected.

FIG. 2 is a diagram showing a connection between a non-defective device of a semiconductor device and a device under test described in the above-mentioned document. 2, a plurality of input terminals _{I 1} of the plurality of input terminals _I 1 ~I _n and the measured LSI22 non-defective LSI21
The ~I _n are connected in parallel, each of the test signal from the test device is input. Each device is switched to the normal operation mode or the test mode according to the logic level of a test control signal externally applied to the test control terminal TI. In comparison tests, good LSI21 is the normal operation mode, forms a path that leads to the output terminal P ₁ to P _n corresponding to a plurality of internal output signal. On the other hand, the measured LSI
Reference numeral 22 denotes a test mode in which a plurality of output terminals P _{1 to} P _{n are connected.}
The external output signal provided from the non-defective LSI 21 is compared with the corresponding internal output signal to generate respective comparison output signals, and the logical sum of these comparison output signals is calculated, and the test result is output from the test output terminal TO. Output as

[0005]

According to the above document, however, the number of test output signals output from the semiconductor device is reduced, but the plurality of input terminals I ₁ of the semiconductor device are reduced.
~I _n must enter each test signal from the test device, the number of test signals to be output from the inspection apparatus is not reduced. Therefore, when a plurality of devices are simultaneously inspected by one inspection apparatus, the number of devices that can be inspected simultaneously is also limited. For example, when the number of test signals that can be output from one inspection apparatus is 256 and the number of input terminals of the semiconductor device is 128, the number of devices that can be simultaneously inspected by one inspection apparatus is also 2
Was individual.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor device having a built-in test auxiliary circuit capable of simultaneously testing a large number of devices with one test apparatus.

[0007]

In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device having a normal operation mode and a test mode, and includes a plurality of semiconductor devices included in the semiconductor device in the test mode. Test signal supply means for serially inputting a plurality of test signals for testing the internal cells and sequentially supplying the plurality of test signals to the corresponding plurality of internal cells; and electrically connecting the plurality of internal cells to the plurality of terminals, respectively. A plurality of switching means for switching between connection and disconnection, and a plurality of signals supplied from outside to a plurality of terminals by outputting output signals of the plurality of internal cells when the plurality of internal cells are disconnected from the terminals. A plurality of comparing means for respectively comparing with the plurality of comparing means, and a judging means for judging a comparison result of the plurality of comparing means.

In the semiconductor device, when a signal is input in a normal operation mode, a plurality of signals supplied from outside to a plurality of terminals are respectively supplied to inputs of a plurality of internal cells through a plurality of switching means. And a means for supplying output signals of a plurality of internal cells to a plurality of terminals via a plurality of switching means when outputting signals in the normal operation mode.

The determining means may include a logical sum means for calculating a logical sum of the comparison results of the plurality of comparing means, and a holding means for holding the logical sum.

Here, the test signal supply means performs a shift operation in synchronization with one of the rising edge and the falling edge of the predetermined clock signal, and the holding means performs the shift operation with the rising edge of the predetermined clock signal. The holding operation may be performed in synchronization with the other of the falling edges.

Further, the comparing means is an exclusive OR.
A circuit may be included.

According to the semiconductor device of the present invention configured as described above, a single serial test signal for operating a plurality of internal cells is supplied from the inspection apparatus, thereby providing a plurality of internal cells and corresponding ones. Since a semiconductor device having a terminal can be inspected, a large number of devices can be inspected simultaneously by one inspection apparatus, or the inspection apparatus can be simplified.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a connection between a non-defective device and a device under test of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, a plurality of input / output terminals T1 to Tn of a non-defective device 11 and a plurality of input / output terminals T1 to Tn of a device under test 12 are connected in parallel. Although the semiconductor device according to the present embodiment has a reduced number of terminals by using an input terminal and an output terminal in common, the present invention is also applied to a semiconductor device provided with separate input terminals and output terminals. It goes without saying that you can do it.

The semiconductor device enters the test mode when a test mode signal applied from a test device (not shown) to the test control terminal Tc is at a high level, and enters the normal operation mode when the test mode signal is at a low level. In the normal operation mode, a path connecting a plurality of internal cells and corresponding input / output terminals T1 to Tn is formed. According to the present embodiment, in the comparative inspection, the non-defective device 1
1 is a test mode, and the device under test 12 is in a normal operation mode. In order to inspect a plurality of devices to be inspected, the same number of non-defective devices are used. The device to be inspected may or may not include the inspection auxiliary circuit, but here, the description will be made assuming that it has the same configuration as the non-defective device including the inspection auxiliary circuit.

Alternatively, the non-defective device 11 may be set to the normal operation mode, and the device under test 12 may be set to the test mode. In this case, one non-defective device can inspect a plurality of devices to be inspected, but all the devices to be inspected need to include an inspection auxiliary circuit. In FIG. 1, the semiconductor device has a plurality of circuits A1 to An. The first circuit A1 includes an internal cell C1, an output buffer B12 and an input buffer B13 of the internal cell, and a transistor Q12 for connecting these to the input / output terminal T1.
And a transistor Q11 and a resistor R1 for pulling up or pulling down the input / output terminal T1, a buffer B11 for inputting a test signal, and an exclusive OR (EXOR) circuit E1 for comparing output signals.

Further, the semiconductor device is provided in the circuit A1.
To An, the boundary scan circuit 1 connected to
It includes an R circuit 2, inverters 3 and 5, an OR circuit 4, a latch circuit 6, and an R / S latch circuit 7.

Next, the operation of the semiconductor device in the comparative inspection will be described.

A high-level test mode signal is supplied to the test control terminal Tc of the non-defective device 11 from the inspection device, and the non-defective device 11 is set to the test mode. In addition, a plurality of test signals for inspecting the internal cells C1 to Cn of the circuits A1 to An are serially supplied from the inspection apparatus to the scan input terminal Ts as one scan input signal, and are supplied to the boundary scan circuit 1. You. The boundary scan circuit 1 receives a scan clock together with a scan input signal from an inspection apparatus, extracts a scan clock component included in the scan input signal, or is supplied with a scan clock from another circuit in the semiconductor device. The shift operation is performed in synchronization with the rising edge or the falling edge of the scan clock, and test signals to be supplied to the circuits A1 to An are sequentially generated.

Since the test procedures of the circuits A1 to An are the same, the first circuit A1 will be described below as an example.

The test mode signal is supplied to one input of the NOR circuit 2 via the inverter 3. The other input of the NOR circuit 2 is supplied with an input / output control signal that is low when the semiconductor device is in the input mode and high when the semiconductor device is in the output mode.

When the semiconductor device is in the test mode and the input mode, the output of the NOR circuit 2 goes high. As a result, the buffer B11 for inputting the test signal is activated, the transistor Q12 is turned on, and the output of the buffer B11 is connected to the input / output terminal T1. The output buffer B12 of the internal cell is in a non-operating state. Therefore, the test signal supplied from the boundary scan circuit 1 is supplied to both the internal cell C1 and the input / output terminal T1 via the buffer B11.

On the other hand, when the semiconductor device is in the test mode and the output mode, the output of the NOR circuit 2 goes low. As a result, the buffer B11 for inputting the test signal becomes inactive, and the transistor Q12
Is turned off to disconnect the output buffer B12 in the operating state from the input / output terminal T1. This gives E
In the XOR circuit E1, the output of the internal cell C1 is compared with the output of the device under test 12 applied to the input / output terminal T1. If they match, the output of the EXOR circuit E1 goes low, and if they do not match, the output of the EXOR circuit E1 goes high.

The circuits A1 to An obtained as described above
Is input to the OR circuit 4 and ORed. That is, if at least one of the test results of the circuits A1 to An does not match, the output of the OR circuit 4 goes high.
The output of the OR circuit 4 is input to the latch circuit 6, and is latched in synchronization with the edge of the scan clock output from the boundary scan circuit 1 opposite to the shift operation edge. Further, the output is held by the R / S latch 7 and output from the test output terminal To as a test output signal. In the test mode, if the output of the non-defective device 11 and the output of the device under test 12 are different at least once, the test output signal becomes high level, so that the defective device can be found without fail. In this way, it is determined whether the device under test 12 is a good product or a defective product.

[0026]

As described above, according to the present invention, a plurality of internal cells and their corresponding terminals are provided by supplying one serial test signal for operating a plurality of internal cells from the inspection apparatus. Since the semiconductor device can be inspected, it is possible to inspect a large number of devices simultaneously with one inspection apparatus or to simplify the inspection apparatus. This has an effect that the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a connection between a non-defective device and a device under test of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a connection between a non-defective device of a conventional semiconductor device and a device under test.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 boundary scan circuit 2 NOR circuit 3, 5 inverter 4 OR circuit 6 latch circuit 7 R / S latch circuit 11 conforming device 12 device under test A1 to An internal circuit of semiconductor device B11 to B13 buffer C1 internal cell E1 EXOR circuit Q11 to Q12 Transistor R1 Resistance T1 to Tn Input / output terminal Tc Test control terminal To Test output terminal Ts Scan input terminal

Claims (5)

[Claims] 1. A semiconductor device having a normal operation mode and a test mode, wherein in a test mode, a plurality of test signals for testing a plurality of internal cells included in the semiconductor device are serially input, and Test signal supply means for sequentially supplying a plurality of test signals to the corresponding plurality of internal cells; and a plurality of switching means for switching whether to electrically connect or disconnect the plurality of internal cells to a plurality of terminals, respectively. A plurality of comparing means for comparing output signals of the plurality of internal cells with a plurality of signals supplied from outside to the plurality of terminals when the plurality of internal cells are disconnected from the plurality of terminals; Determining means for determining a comparison result of the plurality of comparing means;
The semiconductor device comprising: 2. A means for supplying a plurality of signals externally supplied to the plurality of terminals to the inputs of the plurality of internal cells via the plurality of switching means when a signal is input in a normal operation mode. And a means for supplying output signals of the plurality of internal cells to the plurality of terminals via the plurality of switching means, respectively, when outputting signals in a normal operation mode. Semiconductor device. 3. The semiconductor according to claim 1, wherein said determination means includes: a logical sum means for calculating a logical sum of the comparison results of said plurality of comparison means; and a holding means for holding said logical sum. apparatus. 4. The test signal supply unit performs a shift operation in synchronization with one of a rising edge and a falling edge of a predetermined clock signal.
4. The semiconductor device according to claim 3, wherein the holding operation is performed in synchronization with the other of the rising edge and the falling edge of the predetermined clock signal. 5. The semiconductor device according to claim 1, wherein said comparing means includes an exclusive OR circuit.