JP2001096854A - Apparatus and method for printing processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printing processing apparatus and a printing processing method wherewith data transfer efficiency and bus using efficiency between a memory, a spread processing device, and an input/output unit are heightened and a processing throughput is improved. SOLUTION: In a structure wherein printing data are spread and processed by using a rebuildable hardware, two sets of buffer groups each made up by combining input and output buffers whereto the same type access made available in a processing unit such as a band unit are formed. Processings executed simultaneously by both of the buffer groups are made only for either of reading-out or writing-in of data, and furthermore, the data bus is divided into two, one for writing-in only and another for reading-out only, and the structure is so constructed that the processing for writing-in of the data is executed only at the data bus prepared exclusively for such purpose while the processing for reading-out of the data is executed at another data bus prepared exclusively for such purpose, thereby heightening efficiency in using the bus on transferring the data, and making a high-speed processing possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a print processing apparatus and a print processing method. More specifically, high-speed data input / output is realized by adopting a configuration that enables print processing in page units, a plurality of buffer configurations that can input and output data, and a dedicated bus configuration for writing and reading data. The present invention relates to a print processing apparatus and a print processing method that enable high-speed printing.

[0002]

2. Description of the Related Art With the development of an electrophotographic page printer suitable for small-sized, high-speed digital printing, the conventional method of printing mainly on character information has been removed, and images, figures, characters, etc. are handled in the same manner. 2. Description of the Related Art A print processing apparatus that executes printing based on a drawing command using a description language that can freely control enlargement processing, rotation processing, transformation processing, and the like has been widely used. As a typical example of such a description language, P
ostScript (trademark of Adobe Systems), Interpress (trademark of Xerox), A
crobat (trademark of Adobe Systems),
GDI (Graphics Device Inter)
face, Microsoft Corporation trademark) and the like are known.

[0003] Print data created in various description languages is composed of commands and data strings in which drawing commands and data for expressing images, figures or characters at arbitrary positions in a page are arranged in an arbitrary order. Therefore, in order to print with the page printer according to the present invention, the print data must be rasterized before printing. Rasterization is
This is the process of developing a raster scan line by developing it into a series of individual dots or pixels that traverse the page or part of the page, and successively generating successive scan lines below the page.

In a conventional page printer, print data of the entire page is rasterized before printing, and the obtained raster data is stored in a page buffer memory. However, storing raster data for an entire page requires a large amount of memory. In particular, in the latest electrophotographic color page printer, C (Cyan), M
(Magenta), Y (Yellow), BK (Bl
ack) requires raster data corresponding to the four color toners, and image quality is required more than that of a black and white page printer. Need.

[0005] In response to the need for a large amount of memory, various techniques for reducing memory requirements have been devised from the viewpoint of cost reduction, and a band memory technique has recently emerged as one of the techniques. Band memory technology can rasterize print data created in a description language faster than rasterizing print data, instead of rasterizing all print data for one page before printing by a page printer. The data is converted into relatively simple intermediate data, one page is divided into a plurality of adjacent areas (bands), the intermediate data corresponding to each band is stored, and the intermediate data is sequentially transferred to a raster development processing unit to correspond to the band. This is a technology developed in a buffer memory.

In the band memory technology, a memory for storing intermediate data is newly required, but the capacity of a buffer memory which requires a large capacity for raster data can be reduced. However, in the general band memory technology, it is necessary to finish the rasterization processing from the intermediate data to the raster data for the next band before the printing of the raster data of a certain band is completed.

However, when the print data includes a complicated graphic drawing instruction or an image drawing instruction with a large data amount, or a specific band in one page includes a complicated graphic drawing instruction or image drawing instruction. For example, there is a possibility that a situation occurs in which development processing from intermediate data to raster data is not in time.

Therefore, it has been considered to use dedicated hardware in order to speed up the process of developing intermediate data into raster data. As described above, objects to be drawn on the page include various objects such as images, figures, and characters, and these require special processing according to the type of each object.

For example, when the object is an image, resolution conversion, affine conversion, interpolation processing accompanying these processing,
Color processing. In the case of a graphic, coordinate conversion, vector / raster conversion, filling processing, and the like are performed. In the case of a character, conversion of outline coordinates, hint processing, vector / raster conversion, filling processing, and the like are required.

In order to realize high-speed expansion processing by hardware, it is necessary to prepare dedicated hardware one by one for all of these processing. However, in this case, even if the memory amount can be reduced, there is a problem that the amount of dedicated hardware to be added increases and the entire system becomes expensive. In addition, hardware for the purpose of converting intermediate data to a bitmap can be used only for converting the intermediate data to a bitmap, and preparing dedicated hardware corresponding to the processing in parallel reduces the usage rate. There was a problem that it was very useless when considered.

Conventionally, as an attempt to solve such a problem, instead of separately providing hardware that can execute each of the expansion processing functions, the functions are reconfigured by reconfiguring the hardware programmability or structure. Attempts have been made to make it variable and realize many functions at high speed with a small amount of hardware. As a prior art relating to the present invention having such a concept, there is, for example, JP-A-10-278361.

[0012]

Problems to be Solved by the Invention
61 reduces the required amount of hardware by performing expansion processing for outputting input print data to an output device such as a printer by using reconfiguration hardware, and performs processing according to print data to be processed. Through the realization of an optimal hardware configuration dynamically, throughput is improved.

However, even when the speed of the expansion processing is increased by using reconfigurable hardware as described in Japanese Patent Application Laid-Open No. H10-278361, the following problem occurs. That is, an input buffer for storing print data,
One output buffer for storing data to be output to the output device
When mapping is performed on two memories, for example, SDRAM, print data input processing, data input / output processing during expansion processing by reconfiguration hardware, and output processing of expanded data to an output device are performed on a common data bus, Switching between read access and write access frequently occurs,
There is a problem that the rate of occurrence of random access is higher than in the case where the same type of access is continuous, so that the bus use efficiency is significantly reduced.

As means for improving the bus use efficiency, in addition to using the high-speed mode access, a device such as long burst transfer may be considered. However, when using reconfigurable hardware, since relatively few hardware resources are used, the number of buffers for burst transfer is limited, and it is difficult to realize a configuration in which the burst length is increased, and efficient memory access is performed. Therefore, there is a problem that the data transfer rate is reduced.

FIG. 7 shows a memory access pattern in a conventional print processing apparatus configuration, that is, one input / output buffer.
FIG. 5 shows an example of a memory access pattern in a configuration where data is mapped to two memories and a data bus is common.

The upper part of FIG. 7 shows a configuration in which the burst length is 2, that is, two burst data are read or written by one read command or write command, and the lower part of FIG. That is, 1
FIG. 9 illustrates an address data issuing mode and data read (R) and write (W) timings in a configuration in which one burst data is read or written by one read command or write command.

Referring to the upper part of FIG. 7 (burst length: 2), as addresses for reading data from the memory, row and column addresses are alternately issued at successive clock timings as shown in FIG. Pairs of rows,
When the column address is determined, a read command is issued. Here, the data storage memory is an SDRAM, and data reading (R1, R2) is performed after a predetermined delay (latency) from issuance of a read command.

Next, the row and column addresses for the write command are sequentially determined after the row and column addresses of the read command, and a write command is issued by determining a set of row and column addresses. No delay (latency) occurs at the time of data writing, and data is written to the determined address (W1, W2). In this cycle, when a read command and a write command are alternately issued based on a read row and column address and a write row and column address, data reading and writing sequentially progress as shown in FIG. Will be.

The reading and writing of these data are as follows:
It is executed in accordance with the data input / output timing between the input means and the buffer, between the buffer and the expansion processing means, and further between the buffer and the output means, that is, in response to a data input / output request command from each means. Therefore, the writing process and the reading process of the data in the memory (buffer) often occur alternately, and an access pattern almost as shown in FIG. 7 is repeatedly executed.

As shown in FIG. 7, when the switching between the read access and the write access frequently occurs, compared with the case where the same type of access, ie, only the data read or only the data write, is continuously performed. However, the rate of random access to the memory increases, and it is necessary to issue a new row and column address when issuing a command. Therefore,
The address issuance waiting time frequently occurs, resulting in a significant decrease in both the bus use efficiency and the data transfer efficiency.

The lower part of FIG. 7 shows the issuance of address data and the reading (R) and writing of data in a configuration in which the burst length is 1, that is, one burst command is read or written by one read command or write command. (W) shows the timing, and it is clear that the data read and write efficiency, that is, the bus use efficiency and the data transfer efficiency are further reduced as compared with the burst length: 2.

In the conventional print processing apparatus, the input buffer for storing the print data and the output buffer for storing the data to be output to the output device are mapped in one memory as described above, and the input of the print data to the buffer is performed. processing,
In general, a configuration is used in which the input / output processing of the expansion processing data by the reconfiguration hardware to the buffer and the output processing to the output device via the expansion data buffer are performed on a common data bus.

Therefore, it is inevitable to execute the process of reading and writing data from the memory (buffer) at the timing shown in FIG. In other words, since the data read process and the data write process must be repeatedly and alternately performed using the common bus, the data transfer efficiency and the bus use efficiency are significantly reduced,
As a result, the print processing speed is reduced.

That is, on the line "data" shown in FIG. 7, a flat portion without "R" or "W" indicates a state where the bus is not used at all,
In FIG. 7, there are many flat parts on the line "data",
It is clear that the bus use efficiency is low and the bus is not being used effectively.

When a common bus is used to perform processing for inputting intermediate data from the data input unit to the buffer, processing data input / output between the buffer and the expansion processing unit, and processing for outputting print data from the buffer to the output device, If various types of data input / output processing compete on the same bus, and if memory read processing and memory write processing are frequently switched, the rate of random access to memory access will increase. As a result, the memory access has an access pattern substantially as shown in FIG. 7, and the bus use efficiency is reduced.

The present invention has been made in consideration of the above-mentioned drawbacks of the conventional print processing apparatus. In a print processing apparatus that develops print data using reconfigurable hardware, a memory (buffer) is provided. It is possible to increase the data transfer rate and improve the overall processing throughput by increasing the bus usage efficiency in an environment where data transfer is frequently performed between the I / O device and the expansion processing device and I / O device. An object of the present invention is to provide a print processing apparatus and a print processing method.

[0027]

SUMMARY OF THE INVENTION The present invention relates to a print processing apparatus for achieving the above object. That is, a first aspect of the present invention includes an input unit that has at least one of a character, a graphic, and an image drawing element, and that inputs print data described by a predetermined drawing command, and that is input to the input unit. A conversion unit for converting the configuration information of the drawing element of the print data into an intermediate data format added to the print data; an input buffer for receiving and storing the intermediate data converted by the conversion unit for each processing unit; And an output buffer for reading out the intermediate data from an input buffer and executing expansion processing, and an output buffer for storing print data expanded by the expansion processing unit for each processing unit. Is
Each of the two input buffers and the two output buffers is composed of two input buffers and two output buffers, and the two input buffers and the two output buffers are an input / output buffer group combining one input buffer and one output buffer.
A control means for controlling so that one of data read processing and write processing is executed at the data transfer timing for each processing unit for each of the two sets of input / output buffer groups; A print processing apparatus characterized by having:

Further, in the print processing apparatus of the present invention,
The control unit is configured to execute a data read process while one input buffer and one output buffer included in one of the two input / output buffer groups of the two input / output buffer groups are executing data read processing. One input buffer and one output buffer included in the buffer group are controlled to execute a data write operation, and data write and read operations are executed in parallel in two sets of input / output buffer groups. It is characterized by having a configuration for performing control.

Further, the print processing apparatus of the present invention is characterized in that
A data write-only bus used in a process of writing data to buffers included in the set of input / output buffer groups, and data used in a process of reading data from buffers included in the set of input / output buffer groups A read-only bus.

Further, in the print processing apparatus of the present invention,
The processing unit is a band unit, and the two sets of input / output buffer groups perform only one of a read process and a write process for each band unit.

Further, in the print processing apparatus of the present invention,
The processing unit is a page unit, and the two sets of input / output buffer groups perform only one of a read process and a write process for each page unit.

Further, in the print processing apparatus of the present invention,
The two sets of input / output buffer groups each have the same capacity.

Further, in the print processing apparatus of the present invention,
The expansion processing unit is configured by rewritable hardware capable of performing a plurality of processes, and the expansion processing unit includes:
The present invention is characterized in that a hardware configuration for executing a decompression process is changed according to information indicating a hardware configuration in the decompression processing unit included in the intermediate data converted by the conversion unit.

Further, according to a second aspect of the present invention, there is provided a printing method which includes at least one of a character, a graphic, and an image drawing element and outputs print data based on print data described by a predetermined drawing command. In the processing method, an input step of inputting the print data; a conversion step of converting configuration information of a drawing element of the print data input in the input step into an intermediate data format added to the print data; An input buffer storing step of receiving the converted intermediate data for each processing unit and alternately storing the converted intermediate data in two input buffers, and a developing processing step of alternately reading out the intermediate data from the two input buffers and executing a developing process And the print data expanded in the expansion processing step into two output buffers for each processing unit. An output buffer storing step of mutually storing the print data and an output step of alternately outputting the print data stored in the two output buffers from the two output buffers to the output unit, wherein the two input buffers and the two The output buffer is divided into two sets of input / output buffer groups each including one input buffer and one output buffer, and each of the two sets of input / output buffer groups performs either data read processing or data write processing. A print processing method is characterized in that one of the processes is executed at a data transfer timing for each processing unit.

Further, in the print processing method of the present invention,
One input buffer and one output buffer included in one of the two input / output buffer groups of the two input / output buffer groups are included in the other input / output buffer group while data read processing is being performed. Data write and read processing are performed in parallel in two sets of input / output buffer groups such that one input buffer and one output buffer perform data write processing.

Further, in the printing processing method of the present invention,
The process of writing data to the input buffer or the output buffer is performed using a data write-only bus, and the process of reading data from the input buffer or the output buffer is performed using a data read-only bus. .

Further, in the printing processing method of the present invention,
The processing unit is a band unit, and the input buffer or the output buffer performs only one of a reading process and a writing process for each band unit.

Further, in the print processing method of the present invention,
The processing unit is a page unit, and the input buffer or the output buffer performs only one of a read process and a write process for each page unit.

Further, in the print processing method of the present invention,
The expansion processing step includes a step of changing a hardware configuration for executing the expansion processing in accordance with information indicating a hardware configuration included in the intermediate data converted in the conversion step.

[0040]

The print processing apparatus according to the present invention includes two input buffers and two output buffers. The input buffer and the output buffer are divided into two sets of an input buffer and an output buffer. By controlling only one of data read processing and write processing at each timing for each set, the efficiency of data input / output is improved, and the data transfer efficiency and bus use efficiency are improved. It is.

The two sets of input / output buffers in the print processing apparatus of the present invention perform only one of read processing and write processing for each unit, and read processing is performed for one set of input / output buffers. When the input / output buffer of the other set is configured to perform only the write processing, the data write processing at the continuous address,
Alternatively, the data transfer efficiency and the bus use efficiency are improved by increasing the number of read processes and reducing the random access of the memory to improve the data input / output efficiency.

Still other objects, features and advantages of the present invention are:
It will become apparent from the following more detailed description based on the embodiments of the present invention and the accompanying drawings.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a print processing apparatus and a print processing method according to the present invention will be described in detail with reference to the accompanying drawings.

[0044]

FIG. 1 is a block diagram showing the configuration of an embodiment of a print processing apparatus according to the present invention. In FIG. 1, the print processing device includes a print data creation unit 1, a print data input unit 2, a conversion processing unit 3, a development processing unit 4, and an output unit 5. Further, the expansion processing unit 4 includes a reconfigurable expansion unit 40, a reconfiguration control unit 41, and a configuration data management unit 42.

The print data creation section 1 has a function of creating print data described in a description language from document data generated by an application program for processing document creation and editing in a personal computer or a workstation. Things. The description language targeted in the present embodiment is, for example, PDF (Portable Document Fo) represented by GDI and Acrobat.
rmat), Page Description Language such as PostScript (Page Description Language)
e).

The print data input unit 2 has a communication function for inputting the print data generated by the print data creation unit 1,
Alternatively, it has a function of temporarily storing print data until the print data is output to the conversion processing unit 3.

The conversion processing unit 3 converts print data input from the print data input unit 2 into intermediate data that can be expanded into print data in the expansion processing unit 4 and rearranges the intermediate data. The conversion processing unit 3 includes a lexical analysis unit, an intermediate data generation unit, and the like. The lexical analysis unit cuts out the print data input from the print data input unit 2 as a token according to the syntax of a predetermined description language, and outputs the token to the intermediate data generation unit.

The intermediate data generation unit receives and interprets the token output from the lexical analysis unit, executes a drawing command, and generates data for each drawing command, for example, using a trapezoid as a basic unit. The purpose of generating the intermediate data is to enable high-speed expansion processing in the expansion processing unit 4. Therefore, the intermediate data is represented using, for example, a set of simple figures (trapezoids).

The expansion processing unit 4 reads the intermediate data output from the conversion processing unit 3 in, for example, a band unit, executes expansion processing, generates print data, and outputs the print data to the band buffer memory in the expansion processing unit 4. . The expansion processing unit 4 has rewritable hardware such as an FPGA for use in the expansion processing. This hardware functions as a reconfigurable reconfigurable processing unit 40.

Normally, the intermediate data generated by the conversion processing unit 3 is divided into groups that can be processed in parallel, and is stored in the intermediate data storage unit in the conversion processing unit 3 for one page in band units. The intermediate data at this time is data based on a trapezoid, such as a band ID indicating which band the image belongs to, a type of image, character, graphic, etc., a drawing attribute, a circumscribed rectangle for the trapezoid set, and a group ID that can be processed in parallel. , A hardware configuration ID and the like are added. The intermediate data storage unit of the conversion processing unit 3 sends out the intermediate data in response to a request from the development processing unit 4.

The expansion processing unit 4 inputs the configuration data from the configuration data management unit 42 as needed based on the hardware configuration ID added to the intermediate data input from the conversion processing unit 3, and the reconfiguration control unit 41 The function of the reconfigurable expansion processing unit 40 is rewritten by the control of. In the expansion processing unit 4, the rewritten reconfigurable expansion processing unit 40 performs an expansion process on the received intermediate data.

The output unit 5 is, for example, a color page printer, which takes out print data from a buffer memory and prints it. The print data stored in the buffer memory is output to the output unit 5 in response to a print data request from the output unit 5. The output unit 5 receives the developed print data output from the buffer memory of the development processing unit 4, prints it on recording paper, and outputs it.

As the output unit 5, specifically, for example, C
A color page printer using a laser scanning type electrophotographic method capable of outputting a full-color image by repeating exposure, development, and transfer for each of MYBK (cyan, magenta, yellow, and black) colors is used.

The output unit 5 is not limited to the laser printer described above, but may be an ink jet type color printer. In this case, four colors of print data are simultaneously output from the buffer memory of the expansion processing unit 4 to the output unit 5.

FIG. 2 is a block diagram of the reconfigurable expansion processing unit 40. The intermediate data for each band generated by the conversion processing unit 3 is read by the intermediate data transfer control unit 402, and the input band buffers A and 405 of the memory unit 405 are read.
0 or written to the input band buffer B, 4051.

The reconfiguration hardware unit 400 reads the intermediate data from the input band buffers A and 4050 or the input band buffers B and 4051, executes the expansion processing, and executes the output band buffers A and 4052 or the output band buffers B and 4053. , Ie, output and store the expanded data.

Work area 4 provided in memory section 405
Reference numeral 054 denotes a work area when the reconfiguration hardware unit 400 executes the expansion processing on the intermediate data input by the intermediate data transfer control unit 402.

The print data transfer control unit 403 outputs an output band buffer A, 4052 or output band buffer B,
The read print data is read from 3 and converted into serial data for each read word, and output to the output unit 5 in synchronization with the serial output clock signal.

The refresh control unit 401 includes input band buffers A and 4050 and input band buffers B and 405.
1. The refresh of the memory unit 405 including the output band buffers A and 4052, the output band buffers B and 4053, and the work area 4054 is controlled.

The arbitration unit 404 includes a reconfiguration hardware unit 400, a refresh control unit 401, an intermediate data transfer control unit 402, and a print data transfer control unit 40.
3. When the reconfiguration control unit 41 accesses the memory unit 405, it performs arbitration control according to the access priority assigned to each block.

Hereinafter, the use of the input buffer and the output buffer configured in the memory unit 405 of FIG. 2 will be described in detail.

FIGS. 3A and 3B show the input buffers A and 4050 and the input buffers B and 4051, respectively.
Intermediate data is sequentially input to the reconfiguration hardware unit 4
00 shows the use state of each buffer in the state where the expansion processing is executed and the expansion processing data is sequentially output to the output buffers B and 4053 and the output buffers A and 4052.

FIG. 3A shows the input buffer A, 4050
, New intermediate data is being input, and the output image after the expansion processing has been output from the output buffer A 4052 to the output device.

Specifically, in the state of FIG. 3A, the intermediate data corresponding to band (i) is being input from the conversion processing unit 3 to the input buffers A and 4050 and the input buffers B and 4051 are being input. Indicates that the intermediate data corresponding to the band (i-1) has already been input.

The reconfiguration hardware unit 400 receives the intermediate data (band (i) stored in the input buffer B, 4051.
-1) is read out, expanded, and drawn (output) in the output buffer B, 4053. The output buffer A 4052 already stores print data as a result of developing and rendering intermediate data corresponding to the preceding band (i-2), and the print data transfer control unit 403 (see FIG. 2) This is output to the output unit 5.

That is, FIG. 3A shows (1) the processing of inputting the intermediate data of the band (i) to the input buffer A, 4050, and (2) the input buffer B, of the intermediate data of the band (i-1). 4051, read processing from the reconfiguration hardware unit 400, write processing of expanded data to the output buffer B, 4053,
(3) The band (i-
2) Output processing of the developed data and a state in which these processings are executed in parallel.

FIG. 3B shows a state after or before the processing step of FIG. 3A. FIG. 3B illustrates a state in which new intermediate data is being input to the input buffers B and 4051, and an output image that has been subjected to the expansion processing is being output from the output buffers B and 4053.

Specifically, the state of FIG.
Assuming that the state is one step after (a),
In FIG. 3B, intermediate data corresponding to band (i + 1) is being input to input buffers B and 4051, and intermediate data corresponding to band (i) has already been input to input buffers A and 4050. . Reconfigurable hardware unit 40
0 reads out the intermediate data (corresponding to band (i)) stored in the input buffer A, 4050, expands it, and draws it in the output buffer A, 4052. The output buffer B 4053 stores print data as a result of developing and rendering the intermediate data corresponding to the band (i-1), and the print data transfer control unit 403 reads this to the output unit 5.

That is, FIG. 3B shows (1) a process of inputting the intermediate data of the band (i + 1) to the input buffers B and 4051, and (2) a process of inputting the intermediate data of the band (i) from the input buffers A and 4050. Read processing, expansion processing in the reconfiguration hardware unit 400, processing of writing expanded data to the output buffer A 4052,
(3) Band (i-
The output processing of 1) of the developed data and the state where these processings are executed in parallel are shown.

The states shown in FIGS. 3A and 3B are alternately repeated, and the input / output to each buffer and the expansion processing are sequentially executed in band units.

As can be understood from the description of FIG. 3, one input / output buffer group, ie, input buffers A and 40
The set of 50 and the output buffer B, 4053 executes one of data write or read processing at the same timing (FIG. 3 (a) or FIG. 3 (b)), and uses the other input / output buffer group. An input buffer B,
The set of the output buffer 4051 and the output buffers A and 4052 also executes only one of the data writing and reading processing at the same timing (FIG. 3A or 3B). This process is repeated for each band to execute the process. Each input / output buffer group can be configured to have the same capacity so that each input buffer and output buffer can store processing data in band units. Next, a specific configuration of the expansion processing unit that executes the processing of FIG. 3 will be described with reference to FIG.

FIG. 4 is a diagram showing a mounting form of the expansion processing unit 4 in the print processing apparatus of the present invention. As shown in FIG. 4, input buffers A and 701 and output buffers B and 704
, Input buffers B and 702 and output buffers A and 70
The data bus is divided into two groups of three, and the data bus is further divided into a read-only bus 717 and a write-only bus 718.

With the configuration of the expansion processing unit as shown in FIG. 4, each memory unit, that is, the input buffer A,
701 and output buffer B, and input buffer B,
In each set of the set 702 and the set of output buffers A and 703, only one of data read access and data write access for each band may be generated.

Work areas 710 and 711 are provided for each set of input / output buffers. Work area 71
Numeral 0,711 is a temporary work area at the time of executing the expansion processing of the intermediate data input by the reconfiguration hardware 705.

In FIG. 4, the memory controller 71
Reference numerals 2 and 713 control access to each memory area. That is, the memory controller 712
The set of the input buffers A and 701 and the output buffer B, and the memory controller 713 are the read-only bus 71 for the set of the input buffers B and 702 and the output buffers A and 703.
The control unit 714 determines the data input / output timing by executing address setting and the like in the input / output of data to / from the write bus 7 and the write-only bus 718.

The input processing section 715 generally shows the components before the conversion processing section 3 in FIG. 1, and executes input of intermediate data to the expansion processing section. Specifically, the intermediate data from the input processing unit 715 is alternately executed to the input buffers A and 701 and the input buffers B and 702 via the write-only bus 718, and thereafter,
The data is transferred to the reconfiguration hardware (expansion processing unit) 705.

The reconfiguration hardware 705 corresponds to the reconfiguration expansion processing unit 40 in FIG. 1 and is not omitted in FIG. 4 but under the control of the reconfiguration control unit 41 shown in FIG.
It is configured by rewritable hardware that can change its configuration and execute various expansion processes, for example, an FPGA.

The reconfiguration hardware 705 converts the intermediate data into the input buffers A and 701 or the input buffers B and 70.
2 is read out via one of the read-only buses 717 to execute the expansion processing. Reconfigurable hardware 70
The data subjected to the expansion processing in 5 is output to the output unit 71.
6 is output to the output buffers A and 70 via the write-only bus 718.
3 or output buffer B, 704.

Reading of the intermediate data to be expanded in the reconfiguration hardware 705 is performed alternately for the two input buffers A and 701 and the input buffers B and 702. The data writing processing of the expanded data after the expansion processing is executed alternately on the output buffers A and 703 and the output buffers B and 704. This is repeated alternately for each band as described with reference to FIG.

The expanded data stored in the output buffers A and 703 and the output buffers B and 704 are output to the output unit 716 via the read-only bus 717. Output unit 7
An output device 16 includes, for example, a color laser printer, an ink jet printer, and the like. Data output from the output buffers A and 703 and the output buffers B and 704 to the output unit 716 is also performed alternately in band units as described with reference to FIG.

Next, a memory access pattern for the read-only bus 717 and a memory access pattern for the write-only bus 718 using the data input / output buffer structure of the present invention shown in FIG. 4 will be described.

FIG. 5 shows a memory access pattern for the read-only bus 717 when the data input / output buffer configuration of FIG. 4 is used.

In the configuration of the present invention shown in FIG.
(Output processing unit) or an output device 71
6 is different from the conventional bus configuration in which the data read process and the write process are mixedly performed, so that there is a high possibility that one processing unit occupies the bus.

That is, in the read-only bus 717,
The hardware input from the input processing unit 715
05, the intermediate data for executing the expansion processing is input to the input buffers A and 701 or the input buffers B and 702.
And the reconfiguration hardware 705 executes a decompression process, and executes only a process of reading the decompressed data to be output to the output device 716 from the output buffers A and 703 or the output buffers B and 704.

FIG. 5 shows a memory (buffer) access pattern of the read-only bus 717 at this time, in which the upper row has a burst length of 2 and the lower row has a burst length of 1.

First, when the burst length shown in FIG.
The first data read address from the buffer is issued in the order of row and column in accordance with each clock timing. In the configuration of the present invention, the buffer occupies a separate memory area for read only or write only,
As in the conventional buffer configuration, data reading in a memory usage mode in which reading and writing are mixed, the possibility of random memory access that tends to occur at the time of writing is small, and in both data reading and writing processing, The ratio of accessing a continuous area in the memory increases. Therefore, in the line of "address" shown in FIG. 5, it is possible to sequentially issue a column address after a row address and designate a continuous address. Since many processes for sequentially reading data occur, the data read efficiency is improved.

In the example of the burst length: 2 in the upper part of FIG. 5, after a predetermined delay (latency) from the issuance of the first row and column address, the first data is read (R1, R2), and then each column is read. Data (R1, R2) is continuously read from a continuous area of the memory according to the address.

As shown in FIG. 5, only when a row is changed, data reading is temporarily interrupted and the bus is not used (the data line is flat).
), The use efficiency of the bus is remarkably improved.

In the case of the burst length of 1 shown in the lower part of FIG. 5, only the data (R1) is read out corresponding to each address, so that compared with the burst length of 2 shown in the upper part of FIG. Although the data read efficiency and the bus use efficiency decrease, more data read is executed as compared with the memory access pattern in the conventional example of FIG.
Clearly, efficient data transfer is being performed.

In the print processing apparatus of the present invention, C (Cyan), M (Magenta), Y (Y
In the case where a color printer that requires raster data corresponding to the four color toners of four colors (low) and BK (black) is applied, processing for repeating data transfer for each color is executed. By using the output buffer configuration, a greater improvement in data transfer efficiency can be realized as compared with the conventional configuration.

Next, FIG. 6 shows a write-only bus 71 using the data input / output buffer structure of the present invention shown in FIG.
8 shows a memory access pattern for No. 8.

In the configuration of the present invention shown in FIG.
Only the output processing of the expanded data from the (expansion processing unit) or the input processing of the data from the input processing unit 715 occurs, and unlike the conventional bus configuration in which the data reading processing and the writing processing are alternately executed, one processing is performed. There is a high possibility that one processing unit occupies the bus.

That is, in the write-only bus 718,
A process of outputting the decompressed data subjected to the decompression process in the reconfiguration hardware 705 to the output buffers A and 703 or the output buffers B and 704;
The intermediate data input from the input buffer A and the input buffer A 70
1 or only the process of writing to the input buffer B, 702 is executed.

FIG. 6 shows a memory access pattern of the write-only bus 718 at this time. The upper row shows an example where the burst length is 2, and the lower row shows an example where the burst length is 1.

First, when the burst length shown in FIG.
The first data read address from the buffer is issued in the order of row and column in accordance with each clock timing. In the configuration of the present invention, the buffer occupies a separate memory area for read only or write only,
As in the conventional buffer configuration, there is little possibility that random memory access at the time of data reading and writing occurs in a memory usage mode in which reading and writing are mixed, and in both data reading and writing processing, The ratio of accessing the continuous area increases. Therefore, in the line "address" shown in FIG.
By sequentially issuing column addresses sequentially after the row address, data can be sequentially written to a continuous area in the memory.

In the example of the burst length: 2 in the upper part of FIG. 6, the first data write is executed based on the issuance of the first row and column address (W1, W2), and then, according to each column address. , Data (W1, W2) is continuously written to the continuous area of the memory.

As shown in FIG. 6, only when the row of the memory write address is changed, the data write is temporarily interrupted and the bus is not used (the data line is flat), but the conventional configuration (see FIG. 7). ), The use efficiency of the bus is remarkably improved.

In the case of the burst length of 1 shown in the lower part of FIG. 6, only the data (W1) is written corresponding to each address, so that the burst length of 2 shown in the upper part of FIG. Although the data write efficiency and the bus use efficiency are reduced, compared to the memory access pattern in the conventional example of FIG. 7, more data is written and more efficient data transfer is performed. it is obvious.

As described above, the print processing apparatus of the present invention has two sets of buffers for executing data input / output with respect to the expansion processing means, with one input buffer and one output buffer as one set. The configuration is such that each set is a combination that does not cause data read or write to occur in a mixed manner, and data is read and written by a read-only bus and a write-only bus. The memory access pattern as shown is realized, the data transfer efficiency and the bus use efficiency are improved, and high-speed printing processing is possible.

In the above-described embodiment, a print processing apparatus that executes processing in band units has been described. However, the processing unit is not limited to band units, and may be page units. Is a unit that can be processed by each unit, such as an expansion processing unit and an output processing unit connected to
Any unit can be used.

The present invention has been described in detail with reference to the specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiments without departing from the spirit of the present invention. That is, the present invention has been disclosed by way of example, and should not be construed as limiting. In order to determine the gist of the present invention, the claims described at the beginning should be considered.

[0102]

As described above, according to the print processing apparatus and print processing method of the present invention, in a printing apparatus for developing print data by using reconfigurable hardware, two sets of input / output buffers are provided. Divide and create a buffer group configuration that combines those that generate the same type of access in processing units such as band units or page units, thereby increasing the bus use efficiency during data transfer and improving the data transfer rate As a result, it is possible to improve the overall processing throughput of the printing apparatus such as the expansion processing and the print output processing.

Further, according to the print processing apparatus and print processing method of the present invention, the data bus is divided into a write-only bus and a read-only bus. Is executed, efficient data transfer can be performed without conflict between data reading and writing on the bus, and high-speed printing processing is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a print processing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a reconfigurable expansion processing unit in the print processing apparatus of the present invention.

FIG. 3 is a diagram illustrating a use mode of an input buffer and an output buffer in the print processing apparatus of the present invention.

FIG. 4 is a block diagram illustrating details of an input / output buffer configuration and its operation in the print processing apparatus of the present invention.

FIG. 5 is a diagram showing a memory access pattern on a read-only bus in the print processing apparatus of the present invention.

FIG. 6 is a diagram showing a memory access pattern on a write-only bus in the print processing apparatus of the present invention.

FIG. 7 is a diagram illustrating an example of a memory access pattern in a conventional print processing apparatus configuration.

[Explanation of symbols]

 Reference Signs List 1 print data creation unit 2 print data input unit 3 conversion processing unit 4 expansion processing unit 5 output unit 40 reconfigurable expansion processing unit 41 reconfiguration control unit 42 configuration data management unit 400 reconfiguration hardware unit 401 refresh control unit 402 intermediate Data transfer control unit 403 Print data transfer control unit 404 Arbitration unit 405 Memory unit 4050 Input band buffer A 4051 Input band buffer B 4052 Output band buffer A 4053 Output band buffer B 4054 Work area 701 Input buffer A 702 Input buffer B 703 Output buffer A 704 Output buffer B 705 Reconfiguration hardware 710 Work area 0 711 Work area 1 712, 713 Memory controller 714 Control unit 715 Input processing unit 716 Output unit 717 Read Dedicated bus 718 Write only bus

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C061 AQ06 AR01 HH09 HJ06 2C087 BA03 BA04 BA05 BA07 BC01 BC02 BD13 5B021 DD05 DD13 DD20 9A001 BB01 BB03 BB04 DD02 DD08 EE02 HH24 HH31 JJ35 KK02 KK31 KK42

Claims (13)

[Claims] 1. An input means having at least one of a character, a graphic, and an image drawing element and inputting print data described by a predetermined drawing command, and a drawing element of the print data input to the input means. A conversion unit for converting the configuration information into an intermediate data format added to the print data; an input buffer for receiving and storing the intermediate data converted by the conversion unit for each processing unit; And an output buffer for storing the print data expanded by the expansion processing unit for each processing unit. The input buffer and the output buffer each have two inputs. Buffer and two output buffers, wherein the two input buffers and the two output buffers are one input buffer. And one output buffer, the input / output buffer group is divided into two groups, and one of the data read processing and the data write processing is performed for each of the two sets of the input / output buffer groups. A print processing apparatus, comprising: a control unit that performs control at a data transfer timing for each unit. 2. The control unit according to claim 1, wherein one input buffer and one output buffer included in one of the two input / output buffer groups of the two input / output buffer groups execute data read processing. , One input buffer and one output buffer included in the other I / O buffer group are controlled to execute data write processing, and data write and read processing are performed in parallel in two sets of I / O buffer groups. The print processing apparatus according to claim 1, wherein the print processing apparatus is configured to control the print processing to be executed. 3. The data processing apparatus according to claim 2, wherein the print processing device includes a data write-only bus used in a process of writing data to buffers included in the two sets of input / output buffer groups, and a bus included in the two sets of input / output buffer groups. 3. The print processing apparatus according to claim 1, further comprising: a data read-only bus used in a process of reading data from a buffer to be read. 4. The processing unit is a band unit, and each of the two input / output buffer groups performs only one of a read process and a write process for each band unit. 4. The print processing apparatus according to any one of 1 to 3. 5. The processing unit is a page unit, and each of the two input / output buffer groups performs only one of a read process and a write process for each page unit. 4. The print processing apparatus according to any one of 1 to 3. 6. The two input / output buffer groups include:
The print processing apparatus according to claim 1, wherein the print processing apparatuses have the same capacity. 7. The expansion processing means is constituted by rewritable hardware capable of performing a plurality of processes, and the expansion processing means includes a hardware in the expansion processing means included in the intermediate data converted by the conversion means. The print processing apparatus according to any one of claims 1 to 6, wherein a hardware configuration for executing the expansion process is changed according to the information indicating the hardware configuration. 8. A print processing method which has at least one of a character, a graphic, and an image drawing element and outputs print data based on print data described by a predetermined drawing command. An input step of converting the configuration information of the drawing element of the print data input in the input step into an intermediate data format added to the print data; and converting the intermediate data converted in the conversion step for each processing unit. An input buffer storing step of alternately receiving the intermediate data from the two input buffers and executing an expansion process by alternately reading the intermediate data from the two input buffers; Output buffer for alternately storing the printed data in two output buffers for each processing unit And pay step, and an output step of outputting the output means alternately print data stored in the two output buffers from the two output buffers, the said two input buffers two output buffers,
An input / output buffer group in which one input buffer and one output buffer are combined. The input / output buffer group is divided into two groups, and one of data read processing and data write processing is performed for each of the two sets of input / output buffer groups. Is executed at the data transfer timing of each processing unit. 9. An input / output buffer group included in one of the two input / output buffer groups, wherein one input buffer and one output buffer are executing data read processing while the other input / output buffer group is executing the data read processing. Data write and read processing are performed in parallel in two sets of input / output buffer groups so that one input buffer and one output buffer included in the buffer group execute data write processing. A print processing method according to claim 8. 10. A process for writing data to the input buffer or the output buffer is performed using a data write-only bus, and a process for reading data from the input buffer or the output buffer is performed using a data read-only bus. The print processing method according to claim 8, wherein: 11. The processing unit is a band unit, and the input buffer or the output buffer performs only one of a read process and a write process for each band unit. The print processing method according to any one of the above. 12. The processing method according to claim 8, wherein the processing unit is a page unit, and the input buffer or the output buffer performs only one of a reading process and a writing process for each page unit. The print processing method according to any one of the above. 13. The expansion processing step includes a step of changing a hardware configuration for executing the expansion processing in accordance with information indicating a hardware configuration included in the intermediate data converted in the conversion step. Item 13. The print processing method according to any one of Items 8 to 12.