JP2001094363A - Bias device and amplifier device - Google Patents

Abstract

(57) [Problem] To provide a bias device having high performance and high efficiency. SOLUTION: A negative conductance feedback circuit 11 is composed of a first differential pair transistor 11a and a second differential pair transistor 11b.
1b is connected in cascade to the first differential pair transistor via a resistor, and has a gate terminal connected to the pair of transistors M3 so that the conductance of the first differential pair transistor 11a becomes a negative conductance. , M4. The bias circuit 12 includes two transistors M3 and M3 of the second differential pair transistor 11b.
4 is connected through a resistor 2 × R1 to connect D
A C bias is supplied to input points p1, p2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias device and an amplifier device, and more particularly to a bias device constituted by MOS transistors and an amplifier device constituted by MOS transistors and amplifying an electric signal.

[0002]

2. Description of the Related Art In recent years, the degree of integration of high-frequency electronic circuits has been rapidly increasing.
2. Description of the Related Art Integrated devices such as C and LSI are used in a wide range of fields such as communication devices such as televisions and radios and mobile communication devices, and further higher performance and higher efficiency are required.

FIG. 7 is a diagram showing a conventional high impedance circuit. The high impedance circuit 100 has a PM
It comprises OS transistors P11 and P12 and N-MOS transistors M11 and M12.

The sources of the transistors P11 and P12 are connected to the power supply Vdd, and the gates of the transistors P11 and P12 are connected to the drain of the transistor P11. The back gates of the transistors P11 and P12 are connected to the respective sources. The drain of the transistor P11 is connected to the drain of the transistor M11.
Is connected to the drain of the transistor M12.

The gate of the transistor M11 is connected to the + terminal of + Vin, and the gate of the transistor M12 is -Vi.
n-terminal and + Vin-terminal and -Vin + terminal.
The terminals are connected to the same potential Ve. Transistors M11, M
Twelve back gates are connected to the respective sources, and the sources of the transistors M11 and M12 are grounded through the current source 2I0.

FIG. 8 is a diagram showing a conventional differential amplifier circuit. The differential amplifier circuit 200 includes two resistors R1 and NM
It comprises OS transistors M11 and M12. The drains of the transistors M11 and M12 are connected to the power supply Vdd via the resistor R1. Transistors M11, M1
The second back gate connects to each source. The gate of the transistor M11 is connected to the + terminal of + Vin,
The gate of the transistor M12 is connected to the negative terminal of -Vin, and the negative terminal of + Vin and the positive terminal of -Vin have the same potential Ve.
Connect with The sources of the transistors M11 and M12 are
Grounded through current source 2I0.

[0007]

In the conventional high impedance circuit 100 as described above, the input impedance viewed from the signal input point can be the parallel impedance of the impedance viewed from the drains of the P-MOS and N-MOS. Since there is no correlation, the input impedance becomes their parallel impedance.

Therefore, in order to create a large impedance, it is desired that each drain resistance is very large. Further, in order to realize this, it is necessary to increase the early voltage of the drain current, and as a result, the channel length of the transistor is lengthened, and the area of the IC chip is increased.

In addition, there is a problem that the power supply voltage needs to be increased in order to use the N-MOS and the P-MOS. On the other hand, the conventional differential amplifier circuit 2 as described above
In the case of 00, since the input dynamic range and the gain of the amplifier, and the output bias and the output dynamic range have a correlation, the degree of freedom in their design is low.

The main cause is that the load resistance cannot be increased. That is, if the load resistance is increased, DC
Since the bias is reduced, the output dynamic range is narrowed. Therefore, in order to achieve the required amplifier gain, when designing with a modest load,
Although the input dynamic range of the input differential pair must be reduced, the bias current must be increased to compensate for the dynamic range. As a result, an increase in the bias current causes a decrease in the drain voltage of the differential pair.

As described above, since all parts have a causal relationship, conventionally, an increase in the power supply voltage and an increase in the bias current are caused. As a result, the number of amplifier stages is increased to obtain a desired gain. There is a problem that power consumption is greatly contradicted.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and it is an object of the present invention to provide a bias device having high performance and high efficiency. It is another object of the present invention to provide an amplifier device that achieves high performance and high efficiency.

[0013]

According to the present invention, in order to solve the above-mentioned problems, in a bias device configured by a MOS transistor and amplifying an electric signal, a first differential circuit configured by a differential pair of transistors is provided. A dynamic transistor and
A gate terminal composed of a differential pair of transistors, cascade-connected to the first differential pair transistor via a resistor, and having a negative conductance with respect to the conductance of the first differential pair transistor; A negative conductance feedback circuit composed of a second differential pair transistor connected to the drain terminal of the paired transistor and a source terminal of both transistors of the second differential pair transistor via a resistor. And a bias circuit for supplying a DC bias to an input point.

Here, the negative conductance feedback circuit is:
The first differential pair transistor is composed of a first differential pair transistor and a second differential pair transistor. The second differential pair transistor is cascaded to the first differential pair transistor via a resistor, and the first differential pair transistor is connected to the first differential pair transistor. The gate terminals are connected to the drain terminal of the paired transistor so that the conductance of the transistor is negative. The bias circuit connects the source terminals of both transistors of the second differential pair transistor via a resistor to supply a DC bias to the input point.

Further, in an amplifier device configured by MOS type transistors and amplifying an electric signal, a first differential pair transistor configured by a differential pair transistor and a differential pair transistor configured by a differential pair transistor are provided. The first differential pair transistor is cascade-connected via a resistor, and the gate terminal is connected to the drain terminal of the paired transistor so that the first differential pair transistor has a negative conductance with respect to the conductance of the first differential pair transistor. A negative conductance feedback circuit composed of a second differential pair transistor and a source terminal of both transistors of the second differential pair transistor are connected via a resistor to apply a DC bias to an input point. A bias circuit comprising: a bias circuit configured to supply a voltage to the input point; Amplifier device is provided, characterized in that it comprises.

Here, the negative conductance feedback circuit includes:
The first differential pair transistor is composed of a first differential pair transistor and a second differential pair transistor. The second differential pair transistor is cascaded to the first differential pair transistor via a resistor, and the first differential pair transistor is connected to the first differential pair transistor. The gate terminals are connected to the drain terminal of the paired transistor so that the conductance of the transistor is negative. The bias circuit connects the source terminals of both transistors of the second differential pair transistor via a resistor to supply a DC bias to the input point. The voltage / current converter is connected to the input point.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of a bias device according to the present invention. The bias device 10 is configured by a MOS transistor. In the figure, it is composed of an N-MOS, but it may be composed of a P-MOS. The same applies hereinafter.

The negative conductance feedback circuit 11 has a first
, A differential pair transistor 11a, a second differential pair transistor 11b, and two resistors R1. The first differential pair transistor 11a includes transistors M1 and M2.

The second differential pair transistor 11b is composed of transistors M3 and M4, and is cascaded to the first differential pair transistors M1 and M2 via a resistor R1.
The gate terminal is set so that the conductance of the differential pair transistor 11a becomes negative conductance.
The drain terminals of the paired transistors M3 and M4 are connected to each other.

The bias circuit 12 has a resistor 2 × R1, and connects the source terminals of both transistors M3 and M4 of the second differential pair transistor 11b via the resistor 2 × R1 to form a DC bias. To the input points p1, p2
To supply.

In contrast to such a configuration of the bias device 10 of the present invention, the negative conductance feedback circuit 11
The conductance of the S differential pair and the conductance having the same magnitude and opposite polarity are used, and the conductances are connected in series.

As a result, the input point p
Since a very large impedance can be created with respect to 1, p2, a very large active load can be realized.

In the bias circuit 12, a necessary load resistor (2 × R1) is connected to the active load. This apparently causes the load to be in a floating state, so that no bias current flows through the load resistance. Therefore, since the load resistance can be set irrespective of the bias, the gain of the single-stage amplifier can be greatly improved.

Further, in the present invention, the circuit configuration is N-MO
It can be realized only with a single channel of S or P-MOS. As a result, since there is no coexistence of the P channel and the N channel, it is not necessary to consider matching of various characteristics, and it is possible to reduce the variation factor by that much. For this reason, the degree of freedom in design is improved, and it is advantageous for low-voltage operation.

Further, as a result, a desired gain can be achieved with a smaller number of stages as compared with the prior art, so that various performances of the circuit including SN are improved, low power consumption is achieved, and the IC chip area is reduced. It is possible to greatly reduce IC cost and manufacturing cost.

Next, the configuration and operation of the bias device (hereinafter, referred to as a high impedance bias device) 10 will be described in more detail. Regarding the connection relationship between the elements, the drains of the transistors M1 and M2 are connected to the power supply Vdd, and the gates of the transistors M1 and M2 are connected to the same potential Ve. The back gates of the transistors M1 and M2 are connected to their respective sources. Also, transistors M1, M
2 are connected to transistors M3 and M3 via a resistor R1.
4 drain.

The gate of the transistor M3 is connected to the drain of the transistor M4, and the gate of the transistor M4 is connected to the drain of the transistor M3. The back gates of the transistors M3 and M4 are connected to their respective sources. A resistor 2 × R1 is connected between the source terminals of the transistors M3 and M4, and the transistors M3 and M4
Are grounded through a current source I0.

The input point p of the transistor M3
1 is connected to + Vin, and -Vin is connected to the input point p2 of the transistor M4. Here, the drain current coefficients and threshold values of the MOS transistors M1 to M4 are all equal, and the respective drain coefficients are M and the threshold value is Vth. Further, the back gates of all the transistors connected to the sources of the respective transistors are used so that Vth becomes equal.

Generally, the drain current Id in the saturation region
Assuming that the rate of increase in Vds after the pinch-off voltage of the drain current of the transistor following the pinch-off voltage is λ (Early coefficient of the drain current in a saturation region, the same applies hereinafter), Vgs (MOS transistor (Gate-source voltage).

[0030]

Id = (M / 2) × (Vgs−Vth) ² × λ (1) Using this equation (1), the conductance gm of the MOS transistor is obtained as shown in equation (2). You.

[0031]

Gm = M × (Vgs−Vth) × λ (2) Now, when the impedance of the circuit viewed from the application points p1 and p2 of the input Vin in FIG. 1 is obtained, it is obtained by the following flow. The input impedance seen from Vin is Zin.

[0032]

## EQU3 ## (0−Vin) / (R1 + 1 / gm1) + Iin = −Vin / (R1 + 1 / gm3) (3a) ∴Iin = Vin ｛1 / (R1 + 1 / gm1) −1 / (R1 + 1 / gm3) … (3b) ∴Zin = Vin / Iin = 1 / {1 / (R1 + 1 / gm1) -1 / (R1 + 1 / gm3)} (3c) Here, if gm1 = gm3, Zin = ∞ . Also, assuming that the gm of each MOS transistor is equal, the input impedance viewed from the input Vin is very high. At the same time, the DC bias at the application points p1 and p2 of the input Vin is uniquely determined by the current source I0.

That is, the present circuit operates at the application point p of Vin.
1 shows that a DC bias is supplied to p2 with high impedance. Therefore, it was shown that this circuit can be realized only by NMOS.

In each of the above equations, when there is no leakage of drain current to a transistor other than the transistor in the saturation region of the transistor, the currents flowing through the transistors M1 and M3 are equal, and in this case, the gate-source voltage Vg
s is used to consider them equal. This is the same for the transistors M2 and M4.

FIG. 2 is a diagram showing a modification of the high impedance bias device 10. As shown in FIG. The high-impedance bias device 10-1 according to the modified example is configured such that M
The configuration is such that the sources of the OS transistors M3 and M4 are grounded as they are. Others are the same as those in FIG.

Next, the high impedance bias device 1
Another modified example of 0 will be described. FIG. 3 is a diagram showing a modification of the high impedance bias device 10. As shown in FIG. High-impedance bias device 10 of another modified example
-2 regarding the connection relationship of each element, the transistor M1,
The drain of M2 is connected to the power supply Vdd, and the gates of the transistors M1 and M2 are connected to the same potential Ve. The back gates of the transistors M1 and M2 are connected to their respective sources. The sources of the transistors M1 and M2 are connected to the drains of the transistors M3 and M4 via the resistor R1.

The gate of the transistor M3 is connected to the drain of the transistor M4 via the resistor R2, and the gate of the transistor M4 is connected to the drain of the transistor M3 via the resistor R2. Also, the transistor M3,
The gates of M4 are connected to + Vin and -Vin, respectively, and the back gates of transistors M3 and M4 are connected to their respective sources. Further, transistors M3 and M4
A resistor 2R1 is connected between the terminals of the sources of the transistors M3 and M4, and the sources of the transistors M3 and M4 are grounded through the current source I0.

Now, the drain current coefficients and the threshold values of the MOS transistors M1 to M4 are all equal.
Vth. The back gates of all the transistors used are connected to the sources of the transistors so that Vth is equal.

It is assumed that the rate of increase of Vds after the pinch-off voltage of the drain current of all transistors is λ, and that the current does not leak to other than the transistors. When the input impedance viewed from the application points p1 and p2 of the input Vin is obtained, it is obtained in the following flow. The input impedance seen from Vin is Zi
n.

[0040]

(0−Va) / (R1 + 1 / gm1) = (Va + Vin) / R2 + Vin / (R1 + 1 / gm3) (4a) {Va ｛1 / R2 + 1 / (R1 + 1 / gm1)} = − Vin ｛1 / R2 + 1 / (R1 + 1 / gm3)｝ (4b) {Va = −Vin ｛1 / R2 + 1 / (R1 + 1 / gm3)} / {1 / R2 + 1 / (R1 + 1 / gm1)} (4c) Iin = (Vin + Va) / R2 = Vin [1- {1 / R2 + 1 / (R1 + 1 / gm3)} / {1 / R2 + 1 / (R1 + 1 / gm1)}] / R2 (4d) {Zin = Vin / Iin = R2 / [1- ｛ 1 / R2 + 1 / (R1 + 1 / gm3)} / {1 / R2 + 1 / (R1 + 1 / gm1)}] (4e) Here, if gm1 = gm3, Zin = ∞. In addition, in equation (4e), assuming that gm of each MOS transistor is equal, it can be understood that the input impedance viewed from the input Vin is very high. At the same time, the DC bias of the application points p1 and p2 of the input Vin is uniquely determined by the current source I0.

In other words, this circuit shows that the DC bias is supplied with the high impedance at the application points p1 and p2 of Vin. FIG. 4 is a diagram showing a modification of the high impedance bias device 10-2. High-impedance bias device 10 of modified example
3 has a configuration in which the sources of the transistors M3 and M4 are directly grounded through the resistor R1. The other parts are the same as those in FIG.

Next, the high impedance bias device 1
An amplifier device 10a according to the present invention in which a voltage / current converter (hereinafter, referred to as a VI converter) is provided at 0 will be described. FIG. 5 is a diagram showing a configuration of the amplifier device 10a. The circuit configuration is V
-I converter 13 and high impedance bias device 1
0, and the high-impedance
The connection of the bias device 10 is bridged by a resistor 2 × R4.

Since the linearity of the VI conversion unit 13 is very important for maintaining the linearity of the circuit, it is necessary that the circuit has good linearity. FIG. 6 is a diagram showing a detailed configuration of the amplifier device 10a. VI conversion unit 13
The detailed configuration was shown. Regarding the connection relationship of each element to the VI conversion unit 13, the drain of the transistor M5 is:
Connected to the drain of transistor M4,
The drain of transistor 6 is connected to the drain of transistor M3.

The gate of the transistor M5 is connected to + Vin, and the gate of the transistor M6 is connected to -Vin. The back gates of the transistors M5 and M6 are connected to their respective sources, the source of the transistor M5 is connected to the drain of the transistor M7, and the source of the transistor M6 is connected to the drain of the transistor M8.

The gate of the transistor M7 is connected to the drain of the transistor M8, and the gate of the transistor M8 is connected to the drain of the transistor M7. The back gates of the transistors M7 and M8 are connected to their respective sources, and a resistor 2 × is connected between the sources of the transistors M7 and M8.
Connected by R3, the sources of the transistors M7 and M8 are grounded through current sources α × I0, respectively.

Here, the currents flowing through the transistors M5 and M7 are equal, and the currents flowing through the transistors M6 and M8 are equal. Further, assuming that there is no leakage of current to other than the MOS transistor, the current i flowing into the high impedance bias device 10 is
Equation (5) is obtained.

[0047]

## EQU5 ## i = Vin × R3
(5) At this time, a resistor 2 × R4 is bridged to a portion of the high impedance bias device 10 that supplies high impedance. Further, as described above, the inflow points p1 and p2 of the signal current have extremely high impedance. This is on condition that the conductances gm of the MOS transistors constituting the high impedance bias device 10 are all equal.

However, in FIG. 6, since the currents from the transistors M3 and M4 and the bias current from the VI converter 13 flow into the transistors M1 and M2, this must be considered.

Therefore, as shown in FIG.
Consider the bias current of No. 3 as α × I0. Drain current of MOS transistor M1 and MOS transistor M3
(6) and (7) show the respective gm obtained from the drain current of the above. The current coefficient of the MOS transistor M1 is M1, and the current coefficient of the MOS transistor M3 is M3.

[0050]

Drain current of MOS transistor M1: I1 = (M1 / 2) × (Vgs−Vth) ² × λ (6a) {gm of MOS transistor M1 = M1 × (Vgs−Vth) × λ =} 2 × M1 × I1 × λ｝ ^1/2 (6b)

[0051]

Drain current of MOS transistor M3: I3 = (M3 / 2) × (Vgs−Vth) ² × λ (7a) {gm of MOS transistor M3 = M3 × (Vgs−Vth) × λ =} 2 × M3 × I3 × λ｝ ^1/2 (7b) Since I1 = (1 + α) I0 and I3 = I0, M
The condition that the gm of the OS transistor M1 is equal to the gm of the MOS transistor M3 is represented by Expression (8a).

Therefore, assuming that two gm are equal,
The drain current coefficient M1 of the MOS transistor M1 and M
The relationship with the drain current coefficient M3 of the OS transistor M3 appears. This is shown in equation (8c).

[0053]

８2 × M1 × I1 × λ｝ 1/2 = {2 × M3 × I3 × λ} ^1/2 (8a) ∴ ｛2 × M1 × (1 + α) I0 × λ｝ 1/2 = {2 × M3 × I0 × λ} ^1/2 (8b) ∴M3 = (1 + α) × M1 (8c) As can be seen from the equation (8c), the drain current coefficient M3
Must be (1 + α) times M1. In other words, the drain current coefficient M1 is (1/1) of M3.
1 + α) times.

As described above, by adjusting gm, the high-impedance bias device 10 can maintain high impedance, and the impedance seen from the signal current inflow points p1 and p2 is changed by the bridged load resistance. It looks like 2 × R4. With the above in mind,
When the output V0 is obtained using the equation (5), the output V0 is as shown in the equation (9).

[0055]

Vo = i × R4 = Vin × R4 / R3 (9) As can be seen from the above, the load resistance is only 2 × R4, and at the same time, the load resistance 2 × R4 is in a bridge state at the drive point. Therefore, no bias current flows.

Therefore, the bias point of the circuit is
High impedance bias device 10 and V
This can be determined by the bias current of the -I conversion unit 13, the magnitude of the load resistance can be determined without considering the bias, and the degree of freedom in design is expanded. Thus, the conventional P-
A high gain realized by using an active load based on a combination of a MOS and an N-MOS has been changed to an N-MO.
It can be realized only by S.

Although this circuit is composed of only the N-MOS for convenience, this circuit can be constructed in exactly the same manner with only the P-MOS. As described above, in the high-impedance bias device 10 and the amplifier device 10a of the present invention, the active load conventionally realized by the combination of the P-MOS and the N-MOS can be realized by the single-channel MOS transistor. Become.

This means that it is not necessary to consider the most difficult variation among channels among the variations of transistors, and as a result, a circuit configuration of differential input and differential output can be realized. This eliminates the need to maintain balance, and is advantageous for operation at a low power supply voltage.

The high-impedance biasing device 10 by canceling the current conductance can dramatically increase the gain of the amplifier as compared with the conventional one, and can reduce the number of elements and the number of amplifier stages as compared with the conventional one. Since the target gain can be achieved, the performance of the circuit such as the SN ratio is greatly improved.

For these reasons, advantages such as an improvement in the performance of the product, a reduction in the production cost, and a reduction in the substrate area are brought as a result. Also, by creating a high gain amplifier that could not be realized conventionally, its application range is expanded, and a limiter amplifier, PLL, AMDET, FMDET, filter,
It can be used for AGC amplifiers and the like, is particularly useful in high frequency circuits, and is effective for mixed digital-analog systems of MOS circuits.

[0061]

As described above, according to the bias device of the present invention, the gate terminals of the first differential pair transistor and the first differential pair transistor have negative conductance with respect to the conductance of the first differential pair transistor. And a second differential pair transistor connected to the drain terminal of the paired transistor, and a source terminal of both transistors of the second differential pair transistor. And a bias circuit for supplying a DC bias to the input point. As a result, a DC bias can be supplied while having a large impedance at the input point, so that circuit performance and efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a principle view of a bias device according to the present invention.

FIG. 2 is a diagram showing a modification of the high impedance bias device.

FIG. 3 is a diagram showing a modification of the high impedance bias device.

FIG. 4 is a diagram showing a modification of the high impedance bias device.

FIG. 5 is a diagram illustrating a configuration of an amplifier device.

FIG. 6 is a diagram illustrating a detailed configuration of an amplifier device.

FIG. 7 is a diagram showing a conventional high impedance circuit.

FIG. 8 is a diagram showing a conventional differential amplifier circuit.

[Explanation of symbols]

10 Bias device, 11 Negative conductance feedback circuit, 11a First differential pair transistor, 11b
... The second differential pair transistor, 12... Bias circuit, M1 to M4... N-MOS transistors, p1 and p
2. Input point.

Claims (5)

[Claims] 1. A bias device comprising a MOS transistor, comprising: a first differential pair transistor comprising a differential pair of said transistors; and a first differential pair comprising said differential pair of said transistors; A cascade connection is made to the differential pair transistor via a resistor, and a gate terminal is connected to a drain terminal of the paired transistor so that the conductance of the first differential pair transistor becomes negative conductance. A negative conductance feedback circuit composed of a second differential pair transistor, and a source terminal of both transistors of the second differential pair transistor via a resistor, and a DC bias is applied. And a bias circuit for supplying an input point. 2. The bias according to claim 1, wherein the second differential pair transistors connect the gate terminals to the drain terminals of the paired transistors via a resistor. apparatus. 3. An amplifier device comprising a MOS transistor and amplifying an electric signal, comprising: a first differential pair transistor comprising said differential pair of transistors; and a differential pair comprising said transistors. Cascade-connected to the first differential pair transistor via a resistor, and a gate terminal of the paired transistor is connected to the conductance of the first differential pair transistor so as to have a negative conductance. A negative conductance feedback circuit composed of a second differential pair transistor connected to the drain terminal and a source terminal of both transistors of the second differential pair transistor connected via a resistor. And a bias circuit that supplies a DC bias to the input point. Amplifier apparatus characterized by having a voltage / current converter to continue. 4. The amplifier device according to claim 3, wherein said voltage / current conversion section is constituted by said transistors of a differential pair, and a drain terminal of each of said transistors is connected to said input point. . 5. The amplifier device according to claim 4, wherein the drain terminals are connected via a resistor.