JP2001093914A - Semiconductor active device and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor active element capable of reducing a required and sufficient degree of thermal resistance while securing high-frequency characteristics, and suppressing a decrease in strength of a semiconductor substrate and occurrence of mounting failure. And a semiconductor integrated circuit. SOLUTION: A semiconductor substrate 11 is arranged on a first main surface of the semiconductor substrate 11, has an effective finger length W in a first axis direction, and is arranged in parallel in a second axis direction orthogonal to the first axis. The plurality of first main electrode regions, the plurality of main current control regions defined by the effective finger length W, each paired with each of the plurality of first main electrode regions, and the main current control region. A second main electrode region for receiving carriers. Then, immediately below the plurality of main current control regions,
The semiconductor device further includes a concave portion formed from the second main surface to the first main surface of the semiconductor substrate and having the lengths S1 and S2 in the first axial direction shorter than the effective finger length W.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor active element which operates in a high frequency band such as a microwave or a millimeter wave, a high frequency module in which a plurality of these semiconductor active elements are arranged on the same semiconductor substrate, and a high frequency module having the same. A microwave monolithic IC (MMIC: Microwave Monolithic) in which a semiconductor active element and a passive element are arranged on the same semiconductor substrate.
Integrated Circuit).

[0002]

2. Description of the Related Art Due to the rapid growth of demand in the information communication field in recent years, it has become urgent to increase the number of communication lines. For this reason, practical use of a system using a microwave / millimeter wave band, which has not been widely used, has been rapidly progressing. Semiconductor active devices that operate in such high-frequency bands as microwaves and millimeter waves are:
Attention has been focused on high-frequency semiconductor active devices using III-V compound semiconductors such as gallium arsenide (GaAs). This is because a III-V group compound semiconductor represented by GaAs has a higher electron mobility than silicon (Si) and a large maximum value of the electron velocity in a high electric field region. . Then, a high electron mobility transistor (HEMT) using a III-V group compound semiconductor, a heterojunction bipolar transistor (HBT), a Schottky gate type F
High cutoff frequency semiconductor active devices such as ET (MESFET) have been developed.

However, since this type of semiconductor active device generally uses a high-resistance semiconductor substrate, it has a drawback that the thermal conductivity is low and the thermal resistance is large. In particular, a high-power semiconductor active device that consumes a large amount of power consumes a high channel temperature during operation, which is not preferable in terms of reliability. In addition, the characteristics are disadvantageous at high temperatures because the electron mobility decreases.

To solve this problem, (a) as shown in FIG. 17, the back surface of a high-resistance semiconductor substrate 11 such as a GaAs substrate is ground and polished to reduce its thickness, There is known a method of forming a heat-dissipating metal 18 such as gold by plating or the like (hereinafter referred to as "first conventional technique"). This heat dissipation structure is called a plated heat sink (hereinafter abbreviated as “PHS”). The semiconductor active device of the first prior art (PHS structure without a bathtub) shown in FIG.
Active region 1 indicated by a broken line on s substrate 11 (semiconductor substrate)
2, a MESFET 16 including a drain electrode 13, a source electrode 14, and a gate wiring portion 15 is formed. The semiconductor active element 150 is formed by mounting a gold tin solder (A
(u-Sn solder) 20. FIG.
A, b, c,..., J in (b) represent respective unit gates arranged in a comb shape.

(B) Further, as an improved type of the PHS structure,
A bathtub structure in which a concave portion (bathtub) for heat dissipation is provided on the back surface of a high-resistance semiconductor substrate as described in JP-A-60-45076 is known (hereinafter referred to as "second conventional technology"). ). In the second prior art, as shown in FIG. 16, a concave portion 103 is provided on the back surface of a GaAs
2 is filled with gold by plating to dissipate metal (PH
S) 104 is formed. The area of the recess 103 is formed so as to be larger than the active region 12 indicated by the dotted line. The semiconductor active device shown in FIG. 18 also has the structure of the second prior art. The semiconductor active device shown in FIG.
In the semiconductor active element of the first prior art shown in FIG. 7, a concave portion for heat radiation is provided on the back surface of the semiconductor substrate. FIG. 18 (b)
FIG. 18A is a view of the MESFET 16 portion of FIG. 18A as viewed from the back surface of the GaAs substrate.
A recess 67 is formed at a position corresponding to the back surface of the active region 12 of FIG. A heat dissipating metal (PHS) 18 made of gold is formed inside the recess 67. Also in FIG. 18, the GaAs substrate 11 has an area larger than the active region 12.
A concave portion 67 is formed on the back surface of. 16 and 18
As shown in (1), by forming a concave portion on the back surface of the active region and reducing the thickness of the GaAs substrate in the active region portion, the thermal resistance of the semiconductor substrate (chip) can be reduced.

On the other hand, in order to effectively extract the output of a semiconductor active element in a high frequency band such as a microwave or a millimeter wave, it is necessary to pay sufficient attention to parasitic impedance such as a parasitic inductance of the semiconductor active element. In a high frequency band such as a microwave or a millimeter wave, even a very small dimension acts as a large parasitic impedance, so even if the semiconductor active element itself has a high cutoff frequency and a high intrinsic high frequency driving capability, If the parasitic impedance is large,
As a result, a high-frequency output cannot be obtained. For this reason, a technique of including an amplifier circuit or the like in one semiconductor chip (semiconductor substrate) and avoiding the influence of high-frequency parasitic impedance has been developed as a so-called “MMIC” with the rapid development of semiconductor integration technology. In. The circuit formed in the semiconductor substrate in the MMIC structure has been developed in the direction of higher integration density, and the MMIC in which a functional circuit block performing one circuit function of the device is mounted (integrated) on the same semiconductor substrate. The integration density has been increasing. Furthermore, the MMI is designed so that a plurality of functional circuit blocks can be mounted on the same semiconductor substrate.
The degree of integration of C is increasing.

[0007]

Here, a comb-shaped electrode structure MESFET according to the first prior art shown in FIG.
MESFET of comb-shaped electrode structure according to second prior art shown in FIG.
Let's compare the temperature rise of the unit gate. FIG. 17, FIG.
In each of the MESFETs having the comb electrode structure shown in FIG. 8, the gate pitch is 23 μm, and the unit gate width (unit finger length).
150 μm, 10 unit gates, total gate width (total finger length) 1500 μm, source electrode / drain electrode area 20 μm × 150 μm. Therefore, the area of the active region is:
It is 210 μm × 150 μm. The thickness of the GaAs substrate is 70 μm. The recess shown in FIG.
μm and the area at the bottom of the recess is 290 μm × 230 μm
And larger than the area of the active region. FIG. 20 shows the temperature rise ΔT of the unit gate of the MESFET of the first prior art and the second prior art shown in FIGS. 17 and 18. The symbols of a, b, c,..., J on the horizontal axis are shown in FIG.
(B) or the position of the unit gate (gate finger) shown in FIG. 18 (c), and the vertical axis indicates the maximum temperature increase ΔT at each unit gate position. In FIG. 20, the temperature of the first related art is represented by a black circle, and the temperature of the second related art is represented by a white circle. As described above, the temperature increase ΔT of the gate increases from the periphery to the center, and the maximum temperature difference between the unit gates is about 12 K in the first prior art and about 12 K in the second prior art. It is about 9K. As described above, in the second conventional technique, the entire active region is made thinner, which has a great influence on the gate which does not need to suppress the temperature rise so much. Furthermore, in order to make the entire active region thin, the area of the concave portion becomes large, and the strength of the semiconductor substrate on which the semiconductor active element is formed is reduced, and when the semiconductor substrate is mounted on a mounting substrate using Au-Sn solder, The mounting failure in which the Au-Sn solder was not sufficiently filled in the recess was likely to occur.

In a high frequency band such as a microwave or a millimeter wave, the MESFET is generally operated with a source grounded. For this reason, in the MMIC in which the MESFET is mounted on the same substrate, the source electrode of the MESFET is Ga
It is necessary to connect to the ground wiring on the back surface of the As substrate via the via hole. In this case, in order to prevent chip breakage of the GaAs substrate, a certain amount of clearance is required between the via hole and the recess provided in the GaAs substrate.
Therefore, in the MMIC in which the semiconductor active element according to the second conventional technique is integrated, the source electrode is extended long due to the necessity of the clearance, and the grounded source inductance is increased, thereby deteriorating the high frequency characteristics of the MESFET.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor active device having good high-frequency characteristics and good heat radiation characteristics.

Another object of the present invention is to provide good heat radiation characteristics,
Moreover, it is an object of the present invention to provide a semiconductor active element capable of maintaining the strength of a semiconductor substrate.

Still another object of the present invention is to provide a semiconductor active device having a structure which has good heat radiation characteristics and can minimize occurrence of mounting failure.

Still another object of the present invention is to provide a semiconductor integrated circuit which has good high frequency characteristics and good heat radiation characteristics, and which can maintain the strength of the semiconductor substrate without fear of chip breakage of the semiconductor substrate. is there.

Still another object of the present invention is to provide a semiconductor integrated circuit which has both good high-frequency characteristics and good heat radiation characteristics and can suppress occurrence of mounting defects.

Still another object of the present invention is to provide a semiconductor integrated circuit in which a clearance between a via hole and a concave portion can be easily obtained and an extra area of a semiconductor substrate is not required for obtaining the clearance. is there.

Still another object of the present invention is to provide a semiconductor device in which a first main electrode region of a semiconductor active element integrated on a semiconductor substrate is grounded via a via hole, the surface being connected to the first main electrode region. An object of the present invention is to provide a semiconductor integrated circuit that does not require long wiring.

Still another object of the present invention is to provide a semiconductor integrated circuit having a small stray inductance associated with surface wiring and having excellent high-frequency characteristics.

[0017]

In order to achieve the above object, a semiconductor active device according to a first aspect of the present invention comprises:
A semiconductor substrate having a second main surface and a first main surface, having a predetermined effective finger length in a first axial direction, and being orthogonal to the first axis on the first main surface. Second
A plurality of first main electrode regions arranged in parallel in the axial direction, a plurality of main current control regions paired with each of the plurality of first main electrode regions and defined by an effective finger length; A second main electrode region for receiving carriers passing through the region, and a plurality of main current control regions formed directly below the second main surface toward the first main surface and having a length in the first axial direction. At least a concave portion shorter than the effective finger length. Here, as a semiconductor active element, HEM
T, MESFET and other FETs, HBT and other bipolar transistors (BJT), static induction transistors (SI
T) etc. are included. Furthermore, a high-frequency module may be configured by a layout in which a plurality of these semiconductor elements are arranged in parallel on the same semiconductor substrate, a layout in which a plurality of these semiconductor elements are connected in Darlington, or the like. The first main surface and the second main surface of the semiconductor substrate are main surfaces facing each other, and the first and second main surfaces are connected to each other by an end surface (side wall portion) of a peripheral portion of the semiconductor substrate. ing.

The "first main electrode region" refers to either the emitter region or the collector region in a BJT,
And SIT means either the source region or the drain region. "Second main electrode region" refers to BJT
Means either the emitter region or the collector region that does not become the first main electrode region, and either the source region or the drain region that does not become the first main electrode region in the FET or SIT. That is,
If the first main electrode region is an emitter region, the second main electrode region is a collector region. If the first main electrode region is a source region, the second main electrode region is a drain region. Further, the “main current control region” means a channel region immediately below a gate electrode in an FET or SIT, and a voltage applied to a gate electrode causes a conduction / cutoff state of a main current flowing between the source / drain regions. It means a region where the amount of current is controlled. In the BJT, the "main current control region" means a base region, and the base current flowing through the base electrode controls the conduction / cutoff state and current amount of the main current flowing between the emitter and collector regions. You.

A unit element (unit element) is defined by each of the first main electrode areas and a pair of main current control areas, and by arranging these unit elements in parallel in the second axial direction, a so-called multi-channel By configuring a structure (multi-finger structure), a large current operation is enabled, and a high-output operation at a high frequency can be realized. Finger portions of the first main electrode such as a comb-shaped metal electrode are connected to each of the plurality of first main electrode regions, and the main currents of the plurality of unit elements arranged in the multi-channel structure are concentrated. I have. F
In ET or SIT, the gate electrode defining the main current control region also has a comb-shaped gate finger portion, and forms an interdigital structure with the finger portion of the first main electrode. Also in the BJT, the base electrode through which the base current flows in the main current control region has a comb shape,
It is preferable that the finger portion of the base electrode and the finger portion of the first main electrode have a cross finger structure because the base resistance is reduced. As long as the base resistance is not increased, a common base electrode may be arranged for a plurality of main current control regions instead of a cross finger structure.

The second main electrode region is formed of a planar FET or SI
Like the T, a plurality of FEs may be arranged on the first main surface symmetrically with respect to the gate electrode.
Like T or SIT, or BJT, it may be configured as a buried region immediately below the main current control region. This buried area is a sinker area (electrode lead-out area).
It is only necessary to guide on the first main surface and to connect to the surface wiring (second main electrode) through the like. When the second main electrode region is arranged on the first main surface, the second main electrode having a comb shape is formed so as to form an interdigital structure with the finger portion of the first main electrode and the gate electrode interposed therebetween. What is necessary is just to arrange finger portions of the electrodes and make ohmic contact (ohmic contact) between the second main electrode and the second main electrode region.

In the present invention, the "effective finger length" means a dimension of a portion where a main current actually flows, such as an effective emitter width or an effective channel width, measured in the longitudinal direction of the finger. Therefore, in general, the dimension may be shorter than the length of the gate metal electrode (gate finger) in the longitudinal direction or the length of the emitter metal electrode (first main electrode) in the longitudinal direction.

A high thermal conductive material such as a metal is embedded in a concave portion provided on the second main surface of the semiconductor substrate. Then, the mounting board and the high thermal conductive material are connected by solder or the like, and the thermal energy generated in the main current control region can be released through the high thermal conductive material.

According to the semiconductor active device according to the first aspect of the present invention, the semiconductor active element has the concave portion whose length in the first axial direction is shorter than the effective finger length. The length is almost the same as that of the concave portion whose length is longer than the effective finger length, or can be further improved. In particular, the variation (temperature rise difference) of the temperature rise of each unit element (unit element) in the multi-channel structure can be made smaller than that of the concave part whose length in the first axial direction is longer than the effective finger length. It is. For this reason, while ensuring high-frequency characteristics,
This makes it possible to minimize the reduction in the strength of the semiconductor substrate and the occurrence of mounting defects.

In particular, by making the area of the concave portion provided on the second main surface of the semiconductor substrate smaller than the area of the active region of the semiconductor active element provided on the first main surface of the semiconductor substrate, the area of the concave portion is reduced. Is smaller than the area of the active region, the variation in the temperature rise of each unit element can be reduced, and the heat radiation characteristics can be made more uniform. By making the distribution of the temperature rise of each unit element uniform, the mobility of each unit element is also made uniform, and the high-frequency characteristics of each unit element are made uniform. In addition, current concentration on a specific unit element and variation in high-frequency impedance between the unit elements are suppressed. For this reason, a high-output operation at a high frequency becomes possible. Here, the active region means a region in which a main current flows, and the area of the active region is given by an effective finger length on one side, and the length of another side perpendicular to this side is set in the second axial direction. Is the area of a rectangle (rectangle) given by the entire length of the area where all the main current control areas exist. Actually, the recess may be smaller than the active region, and may be arranged on the planar pattern such that the recess is housed inside the active region.

As described above, by making the area of the concave portion smaller than the area of the active region, when configuring a high-frequency module in which a plurality of semiconductor elements are arranged in parallel on the same semiconductor substrate, sufficient semiconductor substrate A plurality of semiconductor elements can be arranged in parallel on a semiconductor substrate at the closest point while maintaining chip strength. As is clear from the above definition, making the area of the recess smaller than the area of the active region means that the area of the second axis of the recess is smaller than the total length of the area where all the main current control areas are measured in the second axis direction. This is equivalent to reducing the dimension measured in the direction, and even if a plurality of semiconductor elements are arranged in parallel on the semiconductor substrate, the distance between the respective recesses can be maintained at a constant value, so that the chip strength is reduced. Because there is nothing to do.

In the semiconductor active device according to the first aspect of the present invention, the planar shape of the concave portion provided on the second main surface is not limited to a rectangle. For example, a hexagon having a tapered portion (oblique side) may be formed such that the length in the first axial direction at the center in the second axial direction is longer than the length in the first axial direction at the end in the second axial direction. Is also good.

In the semiconductor active device according to the first aspect of the present invention, the depth of the concave portion provided on the second main surface does not need to be uniform, and the depth of the concave portion at the center in the second axial direction is not required. May be configured to be deeper than the depth of the recess at the end in the second axial direction.

A semiconductor integrated circuit according to a second aspect of the present invention relates to a structure in which another passive element is integrated on the same semiconductor substrate together with the semiconductor active element according to the first aspect. That is, a semiconductor integrated circuit according to a second aspect of the present invention includes a semiconductor substrate having first and second main surfaces, and a semiconductor active element and a passive element disposed on the first main surface of the semiconductor substrate. And a recess formed immediately below the plurality of main current control regions from the second main surface toward the first main surface and having a length in the first axial direction shorter than the effective finger length of the semiconductor active element. At least. Here, the semiconductor active element has a predetermined effective finger length in a first axis direction of a first main surface of the semiconductor substrate, and a plurality of semiconductor active elements arranged in parallel in a second axis direction orthogonal to the first axis. Multi-channel structure (multi-finger structure) having a first main electrode region and a plurality of main current control regions that are paired with each of the plurality of first main electrode regions and defined by an effective finger length
It is. Naturally, the semiconductor integrated circuit according to the second feature of the present invention further has a second main electrode region for receiving carriers passing through the main current control region. In the semiconductor integrated circuit according to the second aspect of the present invention, the passive element integrated with the semiconductor active element on the same semiconductor substrate includes:
The term means a resistor, a capacitor, an inductor, or the like, but does not necessarily need to be a lumped constant passive element, and may be a distributed constant passive element. In particular, a semiconductor active device integrated on a first main surface of a semiconductor substrate is provided by HEMT, MES,
A semiconductor device having excellent high frequency characteristics in a microwave / millimeter wave band such as FET, HBT, SIT, etc.
The semiconductor integrated circuit according to the first aspect functions as an MMIC. Strictly, in such a high frequency band such as a microwave or a millimeter wave, most passive elements need to be handled in a distributed constant manner. Further, in the MMIC, a signal line such as a high-frequency transmission line, an impedance adjusting means for the signal line, and the like may be arranged on the same semiconductor substrate.
Further, a diode such as a Schottky junction diode may be mounted on the semiconductor integrated circuit.

The semiconductor integrated circuit according to the second aspect of the present invention may further include a via hole penetrating the semiconductor substrate, and a highly conductive material for connection embedded in the via hole. The first main electrode region can be grounded using the via hole and the highly conductive material for connection embedded in the via hole. In this case, the surface wiring (first main electrode wiring) is provided in the first main electrode region.
Is connected, and this surface wiring is connected to a highly conductive material for connection embedded in the via hole and grounded.

A high thermal conductive material such as a metal is embedded in a concave portion provided on the second main surface of the semiconductor substrate. Then, the mounting substrate and the high thermal conductive material are connected by soldering or the like, and the thermal energy generated in the main current control region of the semiconductor active element integrated on the semiconductor substrate can be released through the high thermal conductive material. I can do it. The second of this semiconductor substrate
Although the concave portion provided in the main surface of the first embodiment has a length in the first axial direction shorter than the effective finger length, the heat radiation characteristic is almost the same as that of the concave portion in which the length in the first axial direction is longer than the effective finger length. Or it can be further improved. In particular, the variation (temperature rise difference) of the temperature rise of each unit element (unit element) in the multi-channel structure can be made smaller than that of the concave part whose length in the first axial direction is longer than the effective finger length. It is. For this reason, it is possible to keep the semiconductor integrated circuit according to the second feature of the present invention at high frequency characteristics while minimizing a decrease in the strength of the semiconductor substrate and the occurrence of mounting defects.

In particular, by making the area of the concave portion provided on the second main surface of the semiconductor substrate smaller than the area of the active region of the semiconductor active element provided on the first main surface of the semiconductor substrate, the area of the concave portion is reduced. Is smaller than the area of the active region, the variation in the temperature rise of each unit element can be reduced, and the heat radiation characteristics can be made more uniform. Therefore, the semiconductor integrated circuit according to the second aspect of the present invention can perform high-output operation at a high frequency.

Furthermore, in the semiconductor integrated circuit according to the second aspect of the present invention, the area occupied by the recess provided on the second main surface of the semiconductor substrate is small, and a clearance between the via hole and the recess is taken. No extra area of the semiconductor substrate is required. Therefore, when the surface wiring (first main electrode wiring) connected to the first main electrode region is grounded via the via hole, it is not necessary to route the surface wiring connected to the first main electrode region long. . As a result, a semiconductor integrated circuit having a small stray inductance accompanying the surface wiring and having excellent high-frequency characteristics can be realized.

[0033] In the semiconductor integrated circuit according to the second aspect of the present invention, the planar shape of the concave portion provided on the second main surface is not limited to a rectangle. In the case of a polygon such as a hexagon, the length in the first axial direction at the center in the second axial direction may be longer than the length in the first axial direction at the end in the second axial direction.
As described above, by making a polygon such as a hexagon and shortening the length in the first axis direction at the end in the second axis direction, by utilizing the shortened space and providing a via hole, the area can be increased. Usage efficiency increases. That is, by making the length of the concave portion provided on the second main surface in the first axial direction non-uniform, the clearance between the via hole and the concave portion is not required, so that an extra area of the semiconductor substrate is not required. Therefore, the floating inductance associated with the surface wiring connected to the first main electrode region is reduced, and a semiconductor integrated circuit having excellent high-frequency characteristics can be realized.

The depth of the concave portion provided on the second main surface does not need to be uniform, and the depth of the concave portion at the center in the second axial direction is equal to the depth of the concave portion at the end in the second axial direction. It may be configured to be deeper than that.

A semiconductor integrated circuit according to a third aspect of the present invention relates to a structure in which at least two semiconductor active elements are integrated together with other passive elements on the same semiconductor substrate. That is, the semiconductor integrated circuit according to the third feature of the present invention has the first feature.
A semiconductor substrate having first and second main surfaces, first and second semiconductor active elements disposed on the first main surface of the semiconductor substrate, and passive elements disposed on the first main surface. ,
A first recess formed immediately below the plurality of main current control regions of the first semiconductor active device and a second recess formed immediately below the plurality of main current control regions of the second semiconductor active device. At least have. The first recess is formed from the second main surface toward the first main surface, and has a length in the first axial direction shorter than an effective finger length of the first semiconductor active element. Similarly, the second recess is formed from the second main surface toward the first main surface, and has a length in the first axial direction shorter than the effective finger length of the second semiconductor active element. In addition, the first and second
The semiconductor active element is disposed on the first main surface of the semiconductor substrate and has a predetermined effective finger length in the first axial direction, similarly to the semiconductor active element according to the first feature. A plurality of first main electrode regions arranged in parallel in a second axis direction orthogonal to the one axis; and a plurality of main currents paired with the plurality of first main electrode regions and defined by an effective finger length It has a control region and a second main electrode region for receiving carriers passing through the main current control region. For example,
By preparing a plurality of semiconductor active elements in the output stage and connecting them in parallel or Darlington connection, higher output operation becomes possible.

The passive element integrated together with the semiconductor active element on the same semiconductor substrate means a resistor, a capacitor, and an inductor similarly to the semiconductor integrated circuit according to the second aspect of the present invention. The first and second semiconductor active elements integrated on the first main surface of the semiconductor substrate, and the third, fourth,...
If the semiconductor device has excellent high frequency characteristics in the microwave / millimeter wave band such as T, HBT, and SIT, the semiconductor integrated circuit according to the third feature of the present invention functions as an MMIC.
Further, in the MMIC, a signal line such as a high-frequency transmission line, an impedance adjusting means for the signal line, and the like may be arranged on the same semiconductor substrate.

The semiconductor integrated circuit according to the third feature of the present invention may further include a via hole penetrating the semiconductor substrate, and a connection highly conductive material embedded in the via hole. By using the via hole and the highly conductive material for connection embedded in the via hole, the first and second semiconductor active elements (and the third, fourth,..., Semiconductor active elements) are formed. Each of the first main electrode regions can be grounded. In this case, a surface wiring (first main electrode wiring) is connected to the first main electrode region of each of the first and second semiconductor active elements, and the surface wiring is connected to a high conductivity for connection embedded in a via hole. Connect to material and ground.

The first and second concave portions provided on the second main surface of the semiconductor substrate are filled with a high heat conductive material such as a metal. Then, the mounting substrate and the high thermal conductive material are connected by soldering or the like, and the first integrated on the semiconductor substrate.
In addition, heat energy generated in the main current control region of the second semiconductor active element can be released via the high thermal conductivity material. A first substrate provided on a second main surface of the semiconductor substrate
And the second concave portion has a length in the first axial direction shorter than the effective finger length, but has a heat radiation characteristic substantially equal to or better than that of the concave portion having the first axial length longer than the effective finger length. it can. In particular, the variation (temperature rise difference) of the temperature rise of each unit element (unit element) in the multi-channel structure can be made smaller than that of the concave part whose length in the first axial direction is longer than the effective finger length. It is. For this reason, it is possible to minimize the reduction in the strength of the semiconductor substrate and the occurrence of mounting defects while securing the high frequency characteristics of the semiconductor integrated circuit according to the third feature of the present invention.

In particular, in the semiconductor integrated circuit according to the third aspect of the present invention, the occupied area of the first and second concave portions provided on the second main surface of the semiconductor substrate is small, and the via hole and the first and second concave portions are formed. To take the clearance between the two recesses,
No extra area of the semiconductor substrate is required. Therefore, the surface wiring (first main electrode wiring) connected to the first main electrode region
Is grounded via a via hole, there is no need to extend the surface wiring connected to the first main electrode region for a long time.
As a result, a semiconductor integrated circuit having a small stray inductance accompanying the surface wiring and having excellent high-frequency characteristics can be realized.

In particular, the area of the first and second concave portions provided on the second main surface of the semiconductor substrate is made to correspond to the area of the active region of the first and second semiconductor active elements provided on the first main surface of the semiconductor substrate. By making them smaller than the area, the first and second semiconductor active elements can be arranged in parallel on the semiconductor substrate while maintaining sufficient chip strength of the semiconductor substrate.
As is clear from the definition in the first feature, making the areas of the first and second recesses smaller than the area of the active region means that the area where all the main current control regions measured in the second axis direction exist is located. This is equivalent to making the dimensions of the first and second recesses measured in the second axial direction smaller than the total length. Even if the first and second semiconductor active elements are arranged in parallel on the semiconductor substrate, This is because the distance between the second concave portion and the second concave portion can be maintained at a constant value, so that the chip strength does not decrease. Further, by making the areas of the first and second recesses smaller than the area of the active region, respectively, the first and second recesses can be made smaller in area than the area of the first and second recesses than the area of the active region. In each of the second semiconductor active elements, it is possible to reduce the variation in the temperature rise of each unit element and to achieve more uniform heat radiation characteristics. For this reason, a high-output operation of the semiconductor integrated circuit at a high frequency becomes possible.

In the semiconductor integrated circuit according to the third aspect of the present invention, the planar shapes of the first and second concave portions provided on the second main surface are not limited to rectangles. The polygon may be formed such that the length in the first axis direction at the center in the second axis direction is longer than the length in the first axis direction at the end in the second axis direction. As described above, if the length of the end portion in the first axial direction is shortened, and the shortened space is used to provide the via hole, the area utilization efficiency increases. In other words, if the length of the concave portion in the first axial direction is made non-uniform, an extra area of the semiconductor substrate is not required to provide a clearance between the via hole and the concave portion. Therefore, the stray inductance accompanying the surface wiring can be further reduced, and a semiconductor integrated circuit having excellent high-frequency characteristics can be realized.

The depths of the first and second concave portions need not be uniform, and the depth of the first or second concave portion at the center in the second axial direction is equal to the depth of the concave portion at the end in the second axial direction. It may be configured to be deeper than the depth of.

[0043]

Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

(First Embodiment) As shown in FIG. 1A, a semiconductor active device 10 according to a first embodiment of the present invention
Is a semiconductor substrate (GaAs) having first and second main surfaces.
s substrate) 11 and a GaAs substrate 11 arranged on a first main surface, having a predetermined effective finger length W in a first axis direction, and being arranged in parallel in a second axis direction orthogonal to the first axis. A plurality of first main electrode regions (source regions), and a plurality of main current control regions (channels) which are paired with the plurality of first main electrode regions (source regions) and are defined by the effective finger length W. Area) and the main current control area (channel area)
And a second main electrode region for receiving carriers passing through the MESFET. For example, if the GaAs substrate 11 has a (100) plane, the first axial direction is [11].
0] direction, the second axis direction orthogonal to the first axis is [1 bar 1
The crystal axis may be selected in the [0] direction.

As shown in the back view of FIG. 1B and the cross-sectional view of FIG. 2, a recess 17 is further formed immediately below a plurality of main current control regions (channel regions). The recess 17 is formed from the second main surface (back surface) of the GaAs substrate 11 to the first main surface (front surface), and the lengths S1 and S2 in the first axial direction are equal to the effective finger length W.
Shorter than.

In the semiconductor active device 10 according to the first embodiment of the present invention, the length S2 of the concave portion 17 in the first axial direction is 80 μm with respect to the effective finger length W = 150 μm. In FIG. 1B and FIG. 2, the side wall of the concave portion 17 is drawn to have a taper, but substantially S1 =
It may be S2. For example, if the recess 17 is formed by reactive ion etching (RIE), the sidewall becomes a substantially vertical side wall, so that S1 = S2 can be substantially set. Also,
The thickness of the GaAs substrate 11 is 70 μm, and the depth of the recess 17 is 30 μm.

More specifically, the GaAs substrate 11 is formed on the semi-insulating GaAs substrate 11 through a buffer layer which is a GaAs layer having a thickness of about 150 nm which is not intentionally doped (hereinafter referred to as “non-doped”). , 2 × 1
This is a multilayer structure in which a channel layer of n-type GaAs having an impurity density of about 0 ¹⁷ cm ⁻³ is formed. A thickness of about 100 nm and an impurity density of 2 ×
A plurality of (six) first main electrode regions (source regions) each including an n ⁺ -type GaAs region of about 10 ¹⁸ cm ⁻³ are formed (not shown). As shown in FIG. 1A, each of the plurality of first main electrode regions (source regions) has
Six finger portions of the main electrode (source electrode) 14 are connected, and have a comb shape so as to concentrate respective main currents of the plurality of source regions. The width (length measured in the second axis direction) of the source electrode is 20 μm. The gate electrode defining the main current control region (channel region) also has ten gate finger portions a, b, c,..., J corresponding to the finger portions of the six source electrodes 14, Each of the gate finger portions a, b, c,..., J is led to the gate electrode wiring portion 15 and has a comb shape.
The gate electrode has a multilayer structure of a metal such as Pt / Au or Ti / Pt / Au, or a high-melting metal silicide such as WSi ₂ or WSiN. The pitch of the gate finger portions a, b, c,..., J is 23 μm.

Further, the MES according to the first embodiment of the present invention
In the FET, a thickness of 1 is formed on the n-type channel layer.
A plurality (five) of second main electrode regions (drain regions) each including an n ⁺ -type GaAs region having a thickness of about 00 nm and an impurity density of about 2 × 10 ¹⁸ cm ⁻³ are formed (not shown). That is, on the first main surface of the GaAs substrate 11,
The respective gate finger portions a, b,
Five drain regions are arranged corresponding to c,..., j. As shown in FIG. 1A, each of the drain regions has a finger portion of a comb-shaped second main electrode (drain electrode) 13 so as to form an interdigital structure with a finger portion of a source electrode 14. Five parts are arranged. The width (length measured in the second axis direction) of the drain electrode is 20 μm. As a result, the six finger portions of the source electrode 14 and the five finger portions of the drain electrode 13
The gate finger portions a, b, c,..., J of the ten gate electrodes are arranged between the two finger portions. Then, each of the gate finger portions a, b,
.., j, ten unit elements (unit elements) are defined. In other words, these unit elements having an effective finger length W = 150 μm are 10 units in the second axial direction.
With a multi-channel structure in which a plurality of transistors are arranged in parallel, the total channel width is increased to 10 × 150 μm = 1500 μm, thereby enabling a large current operation. As the drain electrode 13 and the source electrode 14, AuGe / Ni / Au, AuGeNi
/ Au or a structure such as Ni / Au-Ge / Mo / Au can be used.

As is apparent from the back view of the GaAs substrate shown in FIG. 1B and the sectional view of FIG. 2, a concave portion 17 is formed at a position corresponding to the back surface of the active region 12 of the MESFET 16 indicated by a dotted line. ing. The length of the active region 12 measured in the second axis direction is 210 μm, and its area is 21 μm.
It will be given by 0 μm × 150 μm. On the other hand, the area of the bottom of the concave portion 17 is 290 μm × 80 μm.

As shown in FIG. 2, when the semiconductor active element 10 according to the first embodiment of the present invention is mounted on a mounting board 19, a heat dissipating metal made of gold (Au) is provided inside the concave portion 17. (PHS) 18 is embedded. As the mounting substrate 19, alumina (Al ₂ O ₃ ), aluminum nitride (Al
N) or a ceramic substrate such as beryllia (BeO) or an insulating metal substrate may be used. This mounting board 19
A heat radiation metal (PHS) 18 is bonded (fused) using a gold tin (Au-Sn) solder 20 to form a package. In order to solder the heat dissipating metal (PHS) 18 to the surface of the mounting board 19, plating or a direct bonding method is used.
A metal thin film may be formed on the surface of the mounting substrate 19 and then fused to the metal thin film using the Au-Sn solder 20.

By providing the concave portion 17, the thickness of the GaAs substrate 11 below the active region 12 is smaller than the thickness of the substrate below the other regions. Then, as shown in FIG. 2A, the concave portion 17 is provided with a center line AA of the active region 12,
That is, the protrusion protrudes from the active region 12 along the second axis direction orthogonal to the longitudinal direction of the gate finger. However, as shown in FIG. 2B, the active region 1 is drawn in a direction parallel to the longitudinal direction (first axial direction) of the gate finger.
The recess 17 does not protrude from the active region 12 in the direction of the center line BB of the line 2.

FIG. 3 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) in the semiconductor active device 10 according to the first embodiment of the present invention, according to the first prior art and the second prior art having the same dimensions. FIG. 4 is a diagram showing a comparison with a distribution of a rise temperature ΔT in a semiconductor active element. In FIG. 3, the numbers a, b, c,..., J on the horizontal axis indicate the position of each unit gate (gate finger portion) shown in FIG. 2A, and the vertical axis indicates the position of each gate finger. 5 shows the maximum temperature rise ΔT at the time. The temperature distribution in the case of the first prior art is indicated by a black circle, the temperature distribution in the case of the second prior art is indicated by an open circle, and the temperature distribution in the case of the structure according to the first embodiment of the present invention is indicated by □. It is represented by In the semiconductor active device 10 according to the first embodiment of the present invention, the temperature distribution of the gate finger near the center is high, and the temperature at the periphery of the gate finger is low. I have. Temperature rise ΔT at each gate finger position
Is smaller than that of the first prior art having no recess, and is substantially the same as the temperature difference of the second prior art in which a recess larger than the active region is formed below the active region.

As shown in FIG. 3, the rising temperature .DELTA.T of the gate fingers e and f near the center is the highest at about 38 K, and the rising temperature .DELTA.T of the gate fingers a and i near the periphery.
Is 30K, the maximum temperature difference Δ ² T between the gate fingers is about 8K. The maximum temperature difference Δ ² T between the gate fingers is also about the same as the temperature difference between the gate fingers in the second conventional technique.

The semiconductor active device 10 according to the first embodiment of the present invention can be manufactured, for example, by the following steps.

(A) First, the horizontal Bridgman method and chalk
Semi-insulating GaAs substrate 1 by Ralsky (CZ) method or the like
Prepare 1 Then, the semi-insulating GaAs substrate 1
1. At normal or reduced pressure metalorganic vapor phase epitaxy
Growth method (MOCVD method) or molecular beam epitaxy
A 150 nm-thick mask is formed by a thermal growth method (MBE method) or the like.
Buffer layer made of doped GaAs layer;
(2 × 10 ¹⁷cm^-3) N-type GaAs layer
A channel layer made of Si;
Pinged (2 × 10¹⁸cm^-3) N⁺Type GaAs
Contact layers, which are layers, are successively grown. Note that this
These layer thicknesses are examples and other thicknesses may be used.
You. For example, the thickness of the buffer layer may be zero to several μm,
The thickness of the channel layer depends on the doping level and the threshold voltage.
50 nm to 500 nm depending on the
The thickness can adopt a value such as 20 nm to 300 nm.
You.

(B) Photolithography technology
With the resist film patterned by
n⁺Part of the mold contact layer until the channel layer is exposed
Remove by etching. This etching removal is performed with chlorine (Cl
₂) May be performed by RIE using a system etching gas.
Alternatively, wet etching may be used. Wet etching
Is, for example, H in a 4: 1 ratio.₂O₂/ H₂O solution with NH
₄The pH can be adjusted to about 7.2 with OH.
As a result of this etching, n ⁺Type
Contact layer is n⁺Type source region and n⁺Drain region
Becomes

(C) Subsequently, a refractory metal silicide such as WSi ₂ is deposited by CVD or sputtering. The refractory metal silicide is patterned by photolithography and RIE using an etching gas such as Cl ₂ or CF ₄ to expose a channel layer exposed between the n ⁺ type source region and the n ⁺ type drain region. Gate finger portions a, b, c,..., J
Is patterned so that is located. At the same time, the gate electrode wiring portions 15 which concentrate these gate finger portions a, b, c,..., J are also patterned to form comb-shaped gate electrodes (see FIG. 1A).

(D) Thereafter, an interlayer insulating film composed of an oxide film (SiO ₂ film), a nitride film (Si ₃ N ₄ film), or a composite film thereof is deposited on the entire surface by a CVD method or the like.
Then, source / drain contact holes are opened by photolithography and RIE using an etching gas such as CF ₄ . Further, the resist film using the contact hole as an opening is removed, and a new resist film having an opening at a portion where the drain electrode 13 and the source electrode 14 are to be formed is formed on the insulating film. Then, Ni / Au-Ge / Mo / Au metal is deposited by an electron beam evaporation (EB evaporation) method or a sputtering method. Thereafter, by removing the resist film (so-called “lift
The "off method"), the drain electrode 13 and the source electrode 14
Are patterned. Next, rapid thermal annealing (sintering) at 420 ° C for 20 seconds or 450 ° C,
Perform sintering for about 0 minutes. Rapid thermal annealing may use infrared (IR) lamp heating. Further, a passivation film made of an insulating film such as an oxide film (SiO ₂ film), a nitride film (Si ₃ N ₄ film),
It is deposited on the entire surface by VD method, coating or the like. Thus, the processing of the surface of the semi-insulating GaAs substrate 11 is almost completed.

(E) Next, the back surface of the semi-insulating GaAs substrate 11 is processed. First, this semi-insulating GaAs substrate 1
A resist film having an opening pattern corresponding to the shape of the concave portion 17 shown in FIG. next,
Using the resist film pattern as a mask, the back surface of the semi-insulating GaAs substrate 11 is selectively etched away by RIE using a Cl ₂ -based etching gas to form a recess 17. After that, the resist film is removed.

(F) Then, the recess 17 is formed by plating.
Semi-insulating GaAs in which the inside and the recess 17 are not formed
On the back surface of the s substrate 11, a metal film made of Au or the like thicker than the depth of the concave portion 17 is formed, and the concave portion 17 is embedded. Then, if the back surface of the semi-insulating GaAs substrate 11 is flattened by polishing or the like, the semiconductor active device 10 according to the first embodiment of the present invention is completed.

The above manufacturing method is an example, and n ⁺
The source region and the n ⁺ type drain region may be formed by ion implantation using a self-alignment method. In this case, only a buffer layer and a channel layer are formed on the semi-insulating GaAs substrate 11, and there is no need to form an n ⁺ -type contact layer thereon. Then, a metal layer to be a gate electrode is deposited on the channel layer, and the gate electrode is patterned by photolithography and RIE. Next, using this gate electrode pattern, n-type impurity ions such as silicon (Si) and selenium (Se) are implanted on both sides of the gate electrode. Thereafter, by performing annealing for activating the implanted n-type impurity ions, the n ⁺ -type source region and the n ⁺ -type drain region are formed in a self-aligned manner.

FIG. 4 shows an example in which the semiconductor active device 10 according to the first embodiment of the present invention is applied to a semiconductor integrated circuit (MMIC). The MMIC 21 includes a semiconductor substrate (GaAs substrate) 11 having first and second main surfaces.
A semiconductor active element and a passive element arranged on the first main surface of the GaAs substrate 11, a via hole penetrating the GaAs substrate 11, and the via holes 31a, 31
1b, formed directly from the second main surface to the first main surface immediately below the plurality of main current control regions and having a length in the first axial direction. At least a concave portion shorter than the effective finger length of the semiconductor active element. Here, the semiconductor active element is GaAs.
A plurality of first main electrode regions having a predetermined effective finger length in a first axis direction of a first main surface of the substrate and arranged in parallel in a second axis direction orthogonal to the first axis; Book first
A multi-channel structure (multi-finger structure) having a plurality of main current control regions that are paired with the respective main electrode regions and are defined by the effective finger length. Of course, it further has a second main electrode region for receiving carriers that have passed through the main current control region. Although not shown, a metal thin film resistor, a MIM type capacitor, a metal thin film inductor having a helical shape or the like is formed on the GaAs substrate 11. Furthermore, a microstrip line, a coplanar waveguide (CPW) on a GaAs substrate 11
A signal line such as a high-frequency transmission line, an impedance adjusting means for the signal line, and the like may be arranged.

On the channel layer of the GaAs substrate 11, n
^{A +} type source region and an n ⁺ type drain region are formed;
^As shown in FIG. 4A, six finger portions of the source electrode 14 are connected to the ⁺ type source region, and five finger portions of the drain electrode 13 are connected to the n ⁺ type drain region. ing. Between the six finger portions of the source electrode 14 and the five finger portions of the drain electrode 13, the gate finger portions a, b,
, j are arranged, and ten unit elements (unit elements) are defined corresponding to the respective gate finger parts a, b, c, ..., j. .

As is apparent from the view of the back surface of the GaAs substrate shown in FIG. 4B and the sectional view of FIG. 4C, the recess 17 is located at the position corresponding to the back surface of the active region 12 of the MESFET indicated by the dotted line. Are formed. As shown in FIG. 4C, the MMIC 21 according to the first embodiment of the present invention is
When mounting on a mounting substrate 19 such as l ₂ O ₃ or AlN, a heat dissipation metal (PHS) 18 made of Au is embedded in the recess 17. Au-
A metal for heat dissipation (PHS) 18 is fused using Sn solder 20 to form a package.

FIG. 4 shows the M according to the first embodiment of the present invention.
The MIC 21 can ground the source electrode 14 using the via holes 31a and 31b and the high-conductivity material 32 for connection embedded in the via holes 31a and 31b. In this case, the source electrode 14 is connected to the highly conductive connection material 3 embedded in the via holes 31a and 31b.
2 and further to a ground line via a heat dissipating metal (PHS) 18 for grounding.

In this MMIC, by making the width of the concave portion 17 smaller than the effective finger length, the via holes 31a and 31b can be formed without moving away from the MESFET, so that the source ground inductance which causes a deterioration in high frequency characteristics is increased. Nothing.

(Second Embodiment) As shown in FIGS. 5 and 6, a semiconductor active device 51 according to a second embodiment of the present invention
The length of each of the short side and the long side of the concave portion 17 is smaller than the length of the short side and the long side of the active region 12. Specifically, for an active area of 150 μm × 210 μm,
The area of the concave bottom is 80 μm × 100 μm. Others are basically the same as those of the semiconductor active device 10 according to the first embodiment of the present invention, and thus redundant description will be omitted.

FIG. 7 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) in the semiconductor active element 51 according to the second embodiment of the present invention, according to the first prior art and the second prior art having the same dimensions. FIG. 4 is a diagram showing a comparison with a distribution of a rise temperature ΔT in a semiconductor active element. 7, the numbers a, b, c,..., J on the horizontal axis indicate the positions of the unit gates (gate finger portions) shown in FIG. 6A, and the vertical axis indicates the position of each gate finger. 5 shows the maximum temperature rise ΔT at the time. The temperature distribution in the case of the first prior art is indicated by black circles, the temperature distribution in the case of the second prior art is indicated by white circles, and the temperature distribution in the case of the structure according to the second embodiment of the present invention is indicated by +. It is represented by In the semiconductor active element 51 according to the second embodiment of the present invention, although the temperature distribution is “convex upward”, unlike the semiconductor active element 10 according to the first embodiment, a relatively wide range near the center is provided. That is, at the positions of the gate fingers c, d, e, f, g, and h, there are flat plateaus having substantially the same temperature rise ΔT. In other words, it can be seen that the temperature rise localized in the central portion is effectively suppressed, and the uniformization is achieved. The temperature rise ΔT at each gate finger position is smaller than in the first prior art having no recess, and is larger than in the second prior art in which a recess larger than the active region is formed below the active region.

As shown in FIG. 7, the temperature rise ΔT at the positions of the gate fingers c, d, e, f, g, and h near the center.
Is about 40K and the gate finger a
And since i rise temperature ΔT of is 34K, the maximum temperature difference delta ^{2 T} between gate fingers is about 6K. Since the maximum temperature difference Δ ² T between the gate fingers is 12 K in the case of the first prior art having no concave portion, it can be seen that the maximum temperature difference Δ ² T is sufficiently smaller than that of the first prior art. This is a value smaller than the temperature difference 8K in the first embodiment described above, and can be said to be smaller than the temperature difference Δ ² T between the gate fingers in the case of the second related art.

By making the temperatures of the unit gates (gate finger portions) uniform as described above, the characteristics of the unit transistors can be made uniform, and overall deterioration in characteristics can be suppressed.

The semiconductor integrated circuit according to the second embodiment of the present invention is an MMIC in which at least two semiconductor active elements are integrated together with other passive elements on the same semiconductor substrate.
That is, the MMIC 22 according to the second embodiment of the present invention
Is a semiconductor substrate (G) having first and second main surfaces as shown in the front view of FIG. 8A and the back view of FIG.
aAs substrate) 11, first and second semiconductor active elements arranged on a first main surface of the GaAs substrate 11,
A passive element disposed on the first main surface, and via holes 33a, 33b, 33c, penetrating through the GaAs substrate 11;
33d and the via holes 33a, 33b, 33c,
Highly conductive material for connection embedded in 33d (not shown)
A first recess 17a formed immediately below the plurality of main current control regions of the first semiconductor active element, and a second recess formed immediately below the plurality of main current control regions of the second semiconductor active element.
And at least a recess 17b. The first recess 17a
Formed from the second main surface to the first main surface, the length in the first axial direction is shorter than the effective finger length of the first semiconductor active element, and the length in the second axial direction is It is shorter than the total length of the region where all the main current control regions measured in the two axial directions exist. Similarly, the second concave portion 17b is formed from the second main surface toward the first main surface, has a length in the first axial direction shorter than the effective finger length of the second semiconductor active element, and The length in the biaxial direction is shorter than the total length of the region where all the main current control regions measured in the second axial direction exist.

The first semiconductor active element is a GaAs substrate 1
N formed on one channel layer ⁺Mold source area and
n⁺It has a mold drain region (not shown). n⁺Type
In the source region, as shown in FIG.
14a are connected to six fingers, and n⁺Type dray
Five finger portions of the drain electrode 13a
Is connected. Six fingers of source electrode 14a
Between the finger portion and the five finger portions of the drain electrode 13a.
Have gate finger portions a of ten gate electrodes,
b, c,..., j are arranged.
, A, b, c,..., J
A unit element (unit element) is defined. And
The gate finger portions a, b, c,...
Each of them is led to the gate electrode wiring portion 15a and has a comb shape.
ing. Gate finger parts a, b, c,..., J
The main current control region (channel region) is formed immediately below
I have.

Similarly, the second semiconductor active element is composed of GaAs
n formed on the channel layer of the s substrate 11⁺Type source
Region and n⁺Type drain region (not shown in the figure).
Omitted). n ⁺In the mold source region, as shown in FIG.
Are connected to the six finger portions of the source electrode 14b.
And n⁺The drain region of the drain electrode 13b
The finger portions of the book are connected. Source electrode 14b
Six finger portions and five fingers of the drain electrode 13b.
The gate electrodes of the ten gate electrodes
Inger parts a, b, c,..., J are arranged, and
And is led to the gate electrode wiring portion 15b to form a comb shape.
I have. The gate finger portion a of the second semiconductor active device,
b, c,..., j, the main current control region (channel
Area) is formed.

The MMIC 22 according to the second embodiment of the present invention
Is mounted on a mounting substrate such as Al ₂ O ₃ or AlN, Au is provided inside the first concave portion 17a and the second concave portion 17b.
A heat-dissipating metal (PHS) made of material is embedded. Heat dissipating metal (PHS) using Au-Sn solder on this mounting board
To form a package.

The MMIC 22 according to the second embodiment of the present invention
As shown in FIG. 8B, a predetermined clearance is provided between the first concave portion 17a and the second concave portion 17b to form via holes 33a, 33b, 33c, 33d. The via holes 33a, 33b, 33c, 33
The source electrodes 14a and 14b can be grounded using d and the highly conductive material 32 for connection embedded in the via holes 33a, 33b, 33c and 33d. In this case, the source electrodes 14a and 14b are
It is connected to the highly conductive material for connection embedded in 1a and 31b, and further connected to a ground line via a metal for heat dissipation (PHS) to be grounded.

In the MMIC shown in FIG. 8, the first recess 17a
By making the width (the length in the first axial direction) of the second concave portion 17b smaller than the effective finger length, the via hole 3
Since the 3a, 33b, 33c, and 33d can be formed without moving away from the MESFET, the common source inductance, which is a cause of deteriorating high frequency characteristics, can be reduced. Further, by forming the length (the length in the second axial direction) of the first concave portion 17a and the second concave portion 17b with an area smaller than the length of the active region 12 in the second axial direction, the distance between the adjacent semiconductor active elements is reduced. Even if the distance is not widened, sufficient chip strength can be secured. For this reason, a small MMIC with a high integration density can be provided.

Further, the layout of the MMIC shown in FIG. 8 is also effective when a high frequency module in which a plurality of semiconductor elements are arranged in parallel on the same semiconductor substrate. In such a high-frequency module configuration,
While maintaining sufficient chip strength of the semiconductor substrate, a plurality of semiconductor elements can be arranged in parallel on the semiconductor substrate closest to each other, so that the integration density can be improved or the chip area can be reduced.
As is clear from the above description, by reducing the size of the concave portion measured in the second axis direction, even if a plurality of semiconductor elements are arranged in parallel on the semiconductor substrate, the mutual interval between the concave portions is constant. This is because the value can be maintained, and the chip strength does not decrease.

(Third Embodiment) FIG. 9A is a plan view of a semiconductor active device 52 according to a third embodiment of the present invention as viewed from the front surface, and FIG. 9B is a plan view of the GaAs substrate as viewed from the back surface. FIG. 10, FIG. 10A and FIG.
1 is a sectional view taken along line FF and a sectional view taken along line GG in FIG.

In the semiconductor active device of the present invention, the semiconductor
The planar shape of the concave portion provided on the second main surface of the substrate is rectangular.
Not limited to For example, as shown in FIG.
In a rectangular (rectangular) active region 12 of 0 μm × 210 μm
On the other hand, the second main table of the semiconductor substrate (GaAs substrate) 11
Hexagonal recess 4 having a tapered portion (oblique side) on the surface (back surface)
7 are provided. The recess 47 extends along the second axial direction.
Measured along the second axis direction is 240 μm
Length S in the first axial direction at the center_c= 140 μm
is there. And the first axis at the end along the second axis direction
Direction length S_e= 20 μm. In other words, the present invention
First of the concave portions 47 of the semiconductor active element 52 according to the third embodiment
The axial length is the length S in the first axial direction at the center._c
Is the longest and approaches the end along the second axial direction
Becomes shorter and S near the section GG _gIt has become. Soshi
And the length S in the first axial direction at the end._eIs the shortest. Immediately
Chi, S_c> S_g> S_e It is. The depth of the recess 47 is 30 μm. Recess 47
Inside the Au is the same as in the first and second embodiments.
The heat dissipating metal made of the material is embedded. Others of the present invention
Semiconductor active device 10 according to first embodiment and second embodiment
Is basically the same as the semiconductor active element 51 according to the embodiment.
Therefore, duplicate description will be omitted.

FIG. 11 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) in the semiconductor active device 52 according to the third embodiment of the present invention according to the first prior art and the second prior art having the same dimensions. FIG. 4 is a diagram showing a comparison with a distribution of a rise temperature ΔT in a semiconductor active element. In FIG. 11, the numbers a, b, c,..., J on the horizontal axis indicate the position of each unit gate (gate finger portion) (see FIG. 2A), and the vertical axis indicates the position of each gate finger. The maximum rise temperature ΔT at a, b, c,..., j is shown. The temperature distribution in the case of the first prior art is indicated by black circles, the temperature distribution in the case of the second prior art is indicated by white circles, and the temperature distribution in the case of the structure according to the third embodiment of the present invention is indicated by x. Represents. Third of the present invention
In the semiconductor active device 52 according to the embodiment, the rise temperature ΔT of the gate finger near the center is high, and the rise temperature ΔT of the gate finger near the periphery is low, similar to the semiconductor active device 10 according to the first embodiment. The temperature distribution is “convex upward”. The temperature rise ΔT at each gate finger position is smaller than in the first prior art,
This is almost the same as the temperature difference in the case of the second prior art. As shown in FIG. 11, the temperature rise ΔT of the gate fingers e and f near the center is the highest at about 37K, and the temperature rise ΔT of the gate fingers a and i at the periphery is 31K. temperature difference delta ² T of is about 6K. Maximum temperature difference between the gate fingers delta ²
T is also smaller than in the second prior art. For this reason, the heat dissipation characteristics of each unit transistor can be made uniform, and overall deterioration in characteristics can be suppressed.

FIG. 12 shows an example in which the semiconductor active device 52 according to the third embodiment of the present invention is applied to an MMIC. The MMIC 23 according to the third embodiment of the present invention includes a second main surface (back surface) of a semiconductor substrate (GaAs substrate) 11.
Is provided with a hexagonal concave portion 47 having a tapered portion (oblique side). The length of the concave portion 47 in the first axial direction is the longest in the first axial direction at the central portion, and along the second axial direction. The length in the first axial direction at the end is the shortest. As described above, by narrowing the width of the recess 47 near the via holes 31a and 31b, it is easy to obtain a predetermined clearance between the recess 47 and the via holes 31a and 31b. Therefore, mechanical strength of the GaAs substrate 11 can be ensured. The other parts are basically the same as those of the MMIC 21 according to the first embodiment of the present invention, and the duplicate description will be omitted.

(Fourth Embodiment) FIG. 13A is a plan view of a semiconductor active device 53 according to a fourth embodiment of the present invention, as viewed from the front surface, and FIG. 13B is a plan view of the GaAs substrate as viewed from the back surface. FIG. 13 and FIG. 13C show FIG. 13A and FIG.
It is II sectional drawing in (b).

In the semiconductor active device of the present invention, the depth of the concave portion provided on the second main surface of the semiconductor substrate does not need to be the same. For example, as shown in FIG. 13C, the depth of the concave portion at the central portion in the second axial direction may be configured to be deeper than the depth of the concave portion at the end portion in the second axial direction. In FIG. 13, 150 μm × 210
With respect to a rectangular (rectangular) active region 12 of μm, a second main surface (back surface) of a semiconductor substrate (GaAs substrate) 11
A rectangular recess 48 of 90 μm × 100 μm is provided. Here, the depth of the concave portion 48 is the depth d at the central portion.
_c is the deepest and d _c = 30 μm. Then, along the second axis direction becomes shallower as it approaches the end, the most shallow depth d _e at the end, the depth at the end of d _{e =} 16 [mu]
m. In other words, it is a _d c> _{d e.} As in the first and second embodiments, a heat dissipating metal made of Au is embedded in the recess 48. Others are basically the same as the semiconductor active devices 10, 51, and 52 according to the first to third embodiments of the present invention, and thus redundant description will be omitted.

FIG. 14 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) in the semiconductor active device 53 according to the fourth embodiment of the present invention according to the first prior art and the second prior art having the same dimensions. FIG. 4 is a diagram showing a comparison with a distribution of a rise temperature ΔT in a semiconductor active element. In FIG. 14, the numbers a, b, c,..., J on the horizontal axis indicate the position of each unit gate (gate finger portion) shown in FIG. 13C, and the vertical axis indicates the position of each gate finger. Maximum temperature rise ΔT at
Is shown. The temperature distribution in the case of the first prior art is indicated by black circles, the temperature distribution in the case of the second prior art is indicated by white circles, and the temperature distribution in the case of the structure according to the fourth embodiment of the present invention is indicated by *. It is represented by As in the first to third embodiments,
Also in the semiconductor active element 53 according to the fourth embodiment, the rising temperature ΔT of the gate finger near the central portion is high, and the rising temperature ΔT of the gate finger near the peripheral portion is low.
3 shows the temperature distribution. The temperature rise ΔT at each gate finger position is smaller than that of the first related art, and is substantially the same as the temperature difference of the second related art.

As shown in FIG. 14, the temperature rise ΔT of the gate fingers e and f near the center is the highest at about 37K, and the temperature rise ΔG of the gate fingers a and i in the periphery is about 37K.
Since T is 31K, the maximum temperature difference Δ ² T between the gate fingers is about 6K. The maximum temperature difference Δ ² T between the gate fingers is also about the same as the temperature difference between the gate fingers in the second conventional technique. The maximum temperature difference Δ ² T between the gate fingers is smaller than in the second conventional technique. By making the temperatures of the individual unit gates (gate finger portions) uniform in this way, the characteristics of the unit transistors can be made uniform, and overall deterioration in characteristics can be suppressed.

FIG. 15 shows an example in which the semiconductor active element 53 according to the fourth embodiment of the present invention is applied to an MMIC. The MMIC 24 according to the fourth embodiment of the present invention includes a second main surface (back surface) of a semiconductor substrate (GaAs substrate) 11.
The recess 4 has a tapered bottom surface and a continuously changing depth.
8 are provided. That is, the depth at the central portion of the concave portion 48 is the deepest, and becomes shallower toward the end portion,
The shallowest depth at the end. In this manner, the via holes 31a, 3a are maintained while maintaining the strength of the GaAs substrate 11.
1b and the semiconductor active element (MESFET) can be reduced in distance, and good high-frequency characteristics can be maintained. The other parts are basically the same as those of the MMIC 21 according to the first embodiment of the present invention, and the duplicate description will be omitted.

(Other Embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments. However, it should be understood that the description and drawings constituting a part of this disclosure limit the present invention. should not do. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the description of the first to fourth embodiments, the MESFET has been exemplified, but the present invention is not limited to the MESFET. AlGa
An HEMT using an As / GaAs heterojunction, an HBT using a similar heterojunction, or the like may be used, or SIT may be used. In the HBT, the second main electrode region may be configured as a buried region immediately below the main current control region. Then, the buried region may be led onto the first main surface via a sinker region (electrode lead-out region) or the like and connected to the surface wiring (second main electrode). Further, if the base electrode for flowing the base current in the main current control region of the HBT is formed in a comb shape and the finger portion of the base electrode is formed to intersect the finger portion of the first main electrode, the base resistance is reduced, and Operation becomes possible. As long as the base resistance is not increased, a common base electrode may be arranged for a plurality of main current control regions instead of a cross finger structure.

Further, in the MESFET or HEMT to which the present invention is applied, the first and second comb-shaped main electrodes described in the first to fourth embodiments are arranged in an interdigital shape. However, the present invention is not limited to a planar structure (horizontal) in which the gate finger portion of the gate electrode is disposed between the first main electrode and the second main electrode. Like a vertical FET or SIT such as UMOS or VMOS, the second buried region just below the main current control region
The main electrode region may be configured. This buried area is H
Similarly to the BT, the surface wiring (second main electrode) is guided on the first main surface via a sinker region (electrode lead-out region) or the like.
Just connect it to.

In the semiconductor active device 52 according to the third embodiment of the present invention, a semiconductor substrate (GaAs substrate)
The second main surface (back surface) on the tapered portion 11 of the hexagonal recess 47 having a (hypotenuse) is provided, the length S _c of the first axial direction in the central portion is the longest, end along the second axial direction showed continuous short consisting shape closer to the section, through a plurality of steps (stepped portion), a length S _e of the first axial direction may be configured so becomes shortest at the end.

Further, in the semiconductor active device 53 according to the fourth embodiment of the present invention, a semiconductor substrate (GaAs substrate)
In the second bottom surface tapered on the main surface (back surface) of 11, a recess 48 which depth changes continuously provided, the deepest depth d _c at the central portion, the end portion along the second axis direction showed continuous shallow consisting shape closer to, through a plurality of steps, the depth d _e at the end may be configured to best shallower.

Further, by combining the third and fourth embodiments of the present invention, the depth at the central portion is
The shape may be such that the length in the axial direction is the longest, the depth decreases continuously as approaching the end along the second axial direction, and the length in the first axial direction decreases.

Further, FIGS. 4, 12, and 15 show diagrams of a semiconductor integrated circuit on which only one semiconductor active element is mounted, but these drawings are schematic diagrams showing a part of the semiconductor integrated circuit. However, it goes without saying that a plurality of semiconductor active elements may be mounted on the semiconductor integrated circuit of the present invention. Similarly, in each of these figures, illustration is omitted,
The semiconductor integrated circuit of the present invention includes an oscillator, a synthesizer,
A modulator, a power amplifier, a low-noise amplifier, a demodulator, and the like may be further integrated to constitute an RF unit of a high-frequency band wireless communication device. Other circuit blocks having various functions can be integrated on the same semiconductor substrate.

Further, FIGS. 1, 2, 5, 6, 9, 10, and 1
In FIG. 3, via holes are not shown, but in these individual elements (discrete devices), via holes may be provided and the surface wiring (first main electrode wiring) may be grounded via the via holes. This way,
As in the case of the semiconductor integrated circuit of the present invention, an extra area of the semiconductor substrate is not required to provide a clearance between the via hole and the concave portion. Therefore, the stray inductance accompanying the surface wiring can be reduced, and a semiconductor active element as an individual element having excellent high-frequency characteristics can be realized.

Further, a semiconductor substrate other than a GaAs substrate is a compound semiconductor substrate such as indium phosphide (InP) or silicon carbide (SiC), silicon (Si), germanium (Ge).
Of course, various semiconductor substrates such as element semiconductor substrates can be used. Further, a semiconductor substrate having a multilayer structure such as an SOI substrate may be used (however, in the case of an SOI substrate, a structure in which a heat-radiating concave portion penetrates a buried insulating film is preferable).

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0097]

As described above, according to the present invention, a semiconductor active device having good high-frequency characteristics and good heat radiation characteristics is provided, and in particular, the temperature rise of each unit device (unit device) in a multi-channel structure. Less variation,
It is possible to increase the uniformity of heat dissipation.

According to the present invention, the heat radiation characteristics are good,
In addition, a semiconductor active element capable of maintaining the strength of the semiconductor substrate can be provided.

Further, according to the present invention, it is easy to provide a clearance between the concave portions, and even if a module in which a plurality of semiconductor active elements are arranged in parallel on a semiconductor substrate is configured, the chip strength does not decrease. . Therefore, it is highly reliable,
A high-frequency, high-output semiconductor active device can be provided.

Further, according to the present invention, the heat radiation characteristics are good,
Moreover, it is possible to provide a semiconductor active device having a structure capable of minimizing the occurrence of mounting defects.

Further, according to the present invention, it is possible to provide a semiconductor integrated circuit which has both good high-frequency characteristics and good heat radiation characteristics and can maintain the strength of the semiconductor substrate.

Further, according to the present invention, it is possible to provide a semiconductor integrated circuit having both good high-frequency characteristics and good heat radiation characteristics and capable of suppressing occurrence of mounting defects.

Further, according to the present invention, it is possible to provide a semiconductor integrated circuit in which a clearance between a via hole and a concave portion can be easily obtained and an extra area of a semiconductor substrate is not required for obtaining the clearance.

Further, according to the present invention, it is possible to provide a semiconductor integrated circuit in which a clearance between the via hole and the concave portion can be easily obtained, and an extra area of the semiconductor substrate is not required for obtaining the clearance.

Further, according to the present invention, there is provided a semiconductor integrated circuit in which the clearance between the recesses can be easily obtained and the chip strength does not decrease even when a plurality of semiconductor active elements are arranged in parallel on a semiconductor substrate. Can be provided.

Further, according to the present invention, when the first main electrode region of a semiconductor active element integrated on a semiconductor substrate is grounded via a via hole, a surface wiring connected to the first main electrode region is formed. A semiconductor integrated circuit which does not need to be routed for a long time can be provided.

Further, according to the present invention, it is possible to provide a semiconductor integrated circuit having a small floating inductance associated with the surface wiring and having excellent high-frequency characteristics.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor active device according to a first embodiment of the present invention as viewed from the front surface of a GaAs substrate, and FIG. 1B is a plan view of the semiconductor active device as viewed from the back surface of the GaAs substrate. .

FIG. 2A is a sectional view taken along the line AA in FIG. 1, FIG.
(B) is BB sectional drawing in FIG.

FIG. 3 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) of the semiconductor active device according to the first embodiment of the present invention in the semiconductor active device according to the first prior art and the second prior art having the same dimensions. It is a figure shown in comparison with distribution of rise temperature ΔT.

FIG. 4 (a) is a diagram showing M according to the first embodiment of the present invention.
FIG. 4B is a plan view of a part of the MIC viewed from the front surface of the GaAs substrate, FIG. 4B is a plan view viewed from the back surface of the GaAs substrate, and FIG. 4C is a plan view of FIGS. 4A and 4B. C-
It is C sectional drawing.

FIG. 5A is a plan view of a semiconductor active device according to a second embodiment of the present invention as viewed from the front surface of a GaAs substrate, and FIG. 5B is a plan view of the semiconductor active device as viewed from the back surface of the GaAs substrate. .

6A is a sectional view taken along line DD in FIG. 5, FIG.
(B) is EE sectional drawing in FIG.

FIG. 7 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) of the semiconductor active device according to the second embodiment of the present invention in the semiconductor active device according to the first prior art and the second prior art having the same dimensions. It is a figure shown in comparison with distribution of rise temperature ΔT.

FIG. 8 (a) is a diagram showing M according to a second embodiment of the present invention.
FIG. 8B is a plan view of a part of the MIC as viewed from the front surface of the GaAs substrate, and FIG.

FIG. 9A is a plan view of a semiconductor active device according to a third embodiment of the present invention as viewed from the surface of a GaAs substrate.
(B) is a plan view seen from the back surface of the GaAs substrate.

10 (a) and 10 (b) are a sectional view taken along line FF and a sectional view taken along line GG in FIG. 9, respectively.

FIG. 11 is a graph showing the distribution of the temperature rise ΔT of the unit gate (gate finger portion) of the semiconductor active device according to the third embodiment of the present invention in the semiconductor active device according to the first prior art and the second prior art having the same dimensions. It is a figure shown in comparison with distribution of rise temperature ΔT.

FIG. 12A is a plan view of a part of the MMIC according to the third embodiment of the present invention as viewed from the front surface of a GaAs substrate, FIG. 12B is a plan view as viewed from the back surface of the GaAs substrate, FIG. 12C is a sectional view taken along the line HH in FIGS. 12A and 12B.

FIG. 13A is a plan view of a semiconductor active device according to a fourth embodiment of the present invention as viewed from the surface of a GaAs substrate.
FIG. 13B is a plan view seen from the back surface of the GaAs substrate, and FIG. 13C is a cross-sectional view taken along the line II in FIGS. 13A and 13B.

FIG. 14 shows the distribution of the temperature rise ΔT of the unit gate (gate finger portion) of the semiconductor active device according to the fourth embodiment of the present invention in the semiconductor active device according to the first prior art and the second prior art having the same dimensions. It is a figure shown in comparison with distribution of rise temperature ΔT.

FIG. 15A is a plan view of a part of the MMIC according to a fourth embodiment of the present invention as viewed from the surface of a GaAs substrate, and FIG. 15B is a plan view of a part of the MMIC showing the back surface of the GaAs substrate. 15 (c) is a cross-sectional view taken along line JJ in FIGS. 15 (a) and 15 (b).

FIG. 16 (a) is a plan view of a semiconductor active device according to a second conventional technique as viewed from the surface of a GaAs substrate, and FIG.
16 (b) and FIG. 16 (c) show a semiconductor active device according to the second prior art mounted on a package, respectively.
It is sectional drawing seen by the PP line and QQ line in (a).

FIG. 17 (a) is a plan view of a semiconductor active device according to the first prior art as viewed from the surface of a GaAs substrate, and FIG.
FIG. 2B is a sectional view taken along line RR in FIG.
FIG. 2B is a sectional view taken along the line SS in FIG.

FIG. 18 (a) is a plan view of a semiconductor active device according to a second conventional technique as viewed from the surface of a GaAs substrate, and FIG.
FIG. 2B is a plan view of the semiconductor active element viewed from the back surface of the GaAs substrate.

19A is a sectional view taken along the line TT in FIG. 18, and FIG. 19B is a sectional view taken along the line UU in FIG.

FIG. 20 is a diagram showing a distribution of a temperature rise ΔT of a unit gate (gate finger portion) of a semiconductor active device according to the first prior art and the second prior art.

[Explanation of symbols]

10, 51, 52, 53 Semiconductor active device 11, 102 Semiconductor substrate (GaAs substrate) 12 Active region 13, 13a, 13b, 81, 82 Drain electrode 14, 14a, 14b, 85 Source electrode 15, 15a, 15b, 83, 84 gate wiring part 17, 47, 48, 103 concave part (bathtub) 17a first concave part 17b second concave part 18, 104 heat dissipation metal (PHS) 19, 106 mounting substrate 20 Au-Sn solder 21, 22, 23, 24 semiconductor Integrated circuit (MMIC) 31a, 31b, 33a, 33b, 33c, 33d Via hole a, b, c,..., J Gate finger

Claims (5)

[Claims] A semiconductor substrate having first and second main surfaces; a semiconductor substrate disposed on the first main surface, having a predetermined effective finger length in a first axial direction, and orthogonal to the first axis; A plurality of first main electrode regions arranged in parallel in the second axial direction, and a plurality of main current control regions each paired with each of the plurality of first main electrode regions and defined by the effective finger length. A second main electrode region for receiving carriers passing through the main current control region; and a second main electrode region immediately below the plurality of main current control regions.
A semiconductor active element having at least a concave portion formed from the main surface to the first main surface and having a length in the first axial direction shorter than the effective finger length. 2. The apparatus according to claim 1, wherein a length in the first axial direction at a central portion in the second axial direction is longer than a length in the first axial direction at an end in the second axial direction. 1
The semiconductor active device according to any one of the preceding claims. 3. The semiconductor active device according to claim 1, wherein a depth of the concave portion at a central portion in the second axial direction is larger than a depth of the concave portion at an end portion in the second axial direction. . 4. A semiconductor substrate having first and second main surfaces; a semiconductor substrate disposed on the first main surface, having a predetermined effective finger length in a first axis direction, and being orthogonal to the first axis. A plurality of first main electrode regions arranged in parallel in the second axial direction, and a plurality of main current control regions defined by the effective finger length, each pair forming a pair with each of the plurality of first main electrode regions. A semiconductor active device having a second main electrode region for receiving carriers passing through the main current control region; a passive device disposed on the first main surface; and a plurality of main current control regions. Immediately below, the second
A semiconductor integrated circuit having at least a concave portion formed from the main surface to the first main surface and having a length in the first axial direction shorter than the effective finger length. 5. A semiconductor substrate having first and second main surfaces; a semiconductor substrate disposed on the first main surface, having a predetermined effective finger length in a first axis direction, and being orthogonal to the first axis. A plurality of first main electrode regions arranged in parallel in the second axial direction, and a plurality of main current control regions defined by the effective finger length, each pair forming a pair with each of the plurality of first main electrode regions. First and second semiconductor active devices each having a second main electrode region for receiving a carrier that has passed through the main current control region; a passive device disposed on the first main surface; Immediately below the plurality of main current control areas of one semiconductor active element, the semiconductor finger is formed from the second main surface toward the first main surface, and the length in the first axial direction is the effective finger length. A first recess shorter than said second semiconductor active Immediately below the plurality of main current control regions of the child, the first main surface is formed from the second main surface toward the first main surface, and the length in the first axial direction is shorter than the effective finger length. A semiconductor integrated circuit having at least two recesses.