JP2001092798A - Load balancing multiprocessor system and method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To be able to evenly distribute the processing load of each processor, and to perform the load distribution control suitable for the processing capacity of each processor, thereby to improve the processing performance with a simple configuration for both software and hardware. Can be improved. SOLUTION: A plurality of processors 103-1 to 103-
n load monitoring units 101, a processing delay time that is a time difference between data received from the external device 109 via the input / output bus 108 and input / output to the transmission / reception buffer 102,
The ratio of the maximum processing delay time, which is the maximum data input / output time difference in the transmission / reception buffer 102, is determined as a load factor, and the input / output control unit 105 controls the load of each of the processors 103-1 to 103-n via the monitoring bus 107. And the processor 103-1 having the lowest load rate among them.
To send the received data from the external device 109 to

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load distribution type multiprocessor system and method suitable for use in a communication control device such as a base station control device in a mobile communication system.

[0002]

2. Description of the Related Art Conventionally, as a load distribution type multiprocessor system and method, there is one disclosed in Japanese Patent Application Laid-Open No. Hei 5-197652.

In recent years, the performance of microprocessors has been remarkably improved. Even in a system for performing relatively large-scale data processing and arithmetic processing, the required performance as a processor is reduced by executing a small number of processors in parallel. It is enough to satisfy.

FIG. 7 is a block diagram showing the configuration of a conventional load balancing type multiprocessor system.

[0005] A load distribution type multiprocessor system 700 shown in FIG.
01-n, a shared memory unit 702, an arbitration unit 704,
It comprises an input / output control unit 703 and one bus 705 shared by these components.

A data processing operation by each of the processors 701-1 to 701-n is performed by an arbitration unit 704 via a bus 705.
This is executed by arbitration at
Data is input / output to / from the shared memory unit 702 or an external device (not shown) under the control of the input / output control unit 703 via the interface 05.

[0007]

However, in the conventional device, since one bus 705 is shared for memory, input / output, and monitoring, a transfer rate exceeding a certain level cannot be expected. There is a problem that it is difficult to improve the transfer speed in accordance with the increase in the number of 1-701-n.

That is, all processors 701-1 to 70-1
In order to increase the speed of the input / output communication path with the outside of the processor as compared with 1-n, efficient input / output transfer control and no bottleneck occur in the input / output speed required by each processor, In order to perform processing with a uniform load, it is necessary to perform control for dynamically allocating a necessary transfer band and processing to each processor.

Therefore, the processors 701-1 to 701-
In many cases, a large-scale circuit configuration other than n is required. In particular, when the load of all the processors 701-1 to 701-n is high, the overhead of the processing accompanying the insertion of the control circuit cannot be ignored. Each processor 701-
There is a problem that it is difficult to perform control for performing uniform processing on 1 to 701-n.

In the case of control for operating one processor 701-1 to the maximum, the other processor 701-1
2 to 701-n are in an inactive state, so that there is a problem that the processing performance of the entire apparatus cannot be exhibited.
Further, when the load increases and the processing congestion state of the processor is reached, the corresponding processor 701-1 goes down even though the load of the other processor is low, and then the same control works on the remaining processors. However, there is a serious danger that the apparatus will gradually go down one by one, eventually leading to a state where the apparatus is stopped. To prevent this </ underline></
In bold>, it is preferable that all processors having the same performance be operated equally at a predetermined number of operation rates. However, such control is performed so that processing is equally distributed to each of the processors 701-1 to 701-n to exhibit maximum performance. There is a problem that is difficult.

Here, in order to measure the load on each of the processors 701-1 to 701-n for uniform load distribution, the usage rate of the processors 701-1 to 701-n is mostly used. Was. For example, there is a method in which each processor measures the time for which the lowest priority idle task runs per unit time, and determines the remaining factor per unit time as the processing time of each processor, that is, the processor load. Was. However, according to such a method, effective load distribution cannot be performed in many devices having a structure in which data to be processed by each processor is stored in a buffer. This is because even if the processing is performed when the load factors of the processors 701-1 to 701-n indicate the same 98%, various amounts of data waiting to be processed are stored in the buffers of the processors. The processing should be distributed to the processor that has stored the data and is expected to have a small delay time before being processed, and has a small amount of data waiting to be processed. No judgment can be made in the process distribution based on the processor load ratio, and it cannot be said that the control is effective.

Further, when introducing a processor whose performance or the like has been improved by upgrading the system, since load distribution control is realized in a hardware or fixed manner, each processor 701-1 to 701-n is used. Cannot be exchanged during operation, and all processors 701-1 to 701-n need to be updated at the same time, resulting in a system stoppage.

Each of the processors 701-1 to 701-
n have different performances, the processors 701-1 to 701-1-7
There is a problem that it is difficult to control to uniformly distribute the processes by absorbing the performance difference of 01-n.

The present invention has been made in view of the above points, and can distribute the processing load of each processor evenly, and perform software and hardware by performing load distribution control corresponding to the processing capacity of each processor. It is an object of the present invention to provide a load distribution type multiprocessor system and method capable of improving processing performance with a simple configuration.

[0015]

According to the present invention, there is provided a load distribution type multiprocessor system comprising: a holding unit for holding data received from an external device; a data input / output time difference to the holding unit; A plurality of processors having load monitoring means for determining a ratio of the maximum input / output time difference to a load ratio, controlling data transmission and reception between the plurality of processors and the external device, and transmitting received data from the external device to the load. Input / output control means for transmitting to the processor with the lowest rate.

According to this configuration, the processing load of each processor can be evenly distributed, and the processing performance can be improved with a simple configuration for both software and hardware.

The load distribution type multiprocessor system according to the present invention, in the above-described configuration, includes an independent input / output bus and a monitoring bus, respectively. The input / output control means obtains a load factor from a load monitoring means via the monitoring bus.

According to this configuration, since the bus for transmitting and receiving data and the bus for performing load distribution control are different, the data transfer speed can be increased.

In the load distribution type multiprocessor system according to the present invention, in the above configuration, a memory bus independent of the input / output bus and the monitoring bus is provided, and a plurality of processors access the shared memory means via the memory bus. Take.

According to this configuration, since the memory bus is independent of the other buses, the data transfer speed to the shared memory means can be increased.

A load distribution type multiprocessor system according to the present invention controls a plurality of processors for processing data received from an external device, and controls data transmission and reception between the plurality of processors and the external device. The ratio between the data reception time and the processing delay time, which is the difference between the time at which the data is returned after processing by the processor, and the maximum processing delay time, which is the maximum processing delay time, is determined as a load factor. Input / output control means for transmitting data received from the external device to the processor having the lowest load factor.

According to this configuration, load distribution control can be performed in accordance with the processing capability of each processor, and the processing performance can be improved with a simple configuration for both software and hardware.

The load distribution type multiprocessor system according to the present invention, in the above-described configuration, includes an independent input / output bus and a memory bus, respectively. A configuration is adopted in which the access is made via a writing output bus and the plurality of processors access the shared memory means via the memory bus.

According to this configuration, since the memory bus is independent of the other buses, the data transfer speed to the shared memory means can be increased.

The base station apparatus according to the present invention employs a configuration provided with a load distribution type multiprocessor system similar to any of the above configurations.

According to this configuration, in the base station apparatus,
The same operation and effect as those of any of the above configurations can be obtained.

The base station control apparatus of the present invention employs a configuration including a load distribution type multiprocessor system similar to any one of the above configurations.

According to this configuration, in the base station controller, the same operation and effect as any of the above configurations can be obtained.

The mobile communication system of the present invention employs a configuration including the base station apparatus having the above configuration or the base station control apparatus having the above configuration.

According to this configuration, in the mobile communication system, the same operation and effect as any of the above configurations can be obtained.

According to the load distribution control method of the present invention, in a plurality of processors, a time difference between input / output of data received from an external device via an input / output bus to / from a holding unit and a maximum difference between maximum input / output of data in the holding unit. In the input / output control means for determining the ratio to the time difference as a load factor and controlling data transmission and reception between the plurality of processors and the external device via the input / output bus, via a monitoring bus independent of the input / output bus Obtaining a load factor of the plurality of processors,
The data received from the external device is transmitted to the processor having the lowest load factor.

According to this method, the processing load of each processor can be evenly distributed, and the processing performance can be improved with a simple configuration for both software and hardware.

According to a load distribution control method of the present invention, in an input / output control means for controlling data transmission / reception between a plurality of processors and the external device via an input / output bus, a data reception time from the external device, Is determined as the load factor by the ratio of the processing delay time, which is the difference between the time returned after processing by the processor, and the maximum processing delay time, which is the maximum time of the processing delay time. The received data from the external device is transmitted to the external device.

According to this method, load distribution control suitable for the processing capacity of each processor can be performed, and the processing performance can be improved with a simple configuration for both software and hardware.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a load distribution type multiprocessor system according to Embodiment 1 of the present invention.

The load distribution type multiprocessor system 100 shown in FIG. 1 is used for a base station device or a base station control device in a mobile communication system, or a switching center on the network side, and controls a functional unit for performing communication. A plurality of processors 103-1 to 103- each having a load monitoring unit 101 and a transmission / reception buffer 102.
n, a shared memory unit 104, an input / output control unit 105 having an arbitration unit, a memory bus 106, and a monitoring bus 107.
And an input / output bus 108.

The memory bus 106 is connected to the input / output control unit 105, each of the processors 103-1 to 103-n and the shared memory unit 104, and the monitoring bus 107 is connected to the input / output bus 108 and each of the processors 103-103. 1-103-n
A load monitoring unit 101 and a shared memory unit 104 are connected. An input / output bus 108 includes an input / output control unit 105 and a transmission / reception buffer 10 of each of the processors 103-1 to 103-n.
2 and the external device 109 are connected.

The load monitoring unit 101 evaluates the processing amount of the processor and displays it on the monitoring bus 107.

The transmission / reception buffer 102 includes an external device 109
And holds data received via the input / output bus 108 from, for example, a FIFO (First In First Out)
A memory is used.

The input / output control unit 105 manages input / output data with respect to the external device 109 and monitors the input data with the monitoring bus 107.
Are assigned to specific processors based on the evaluation of each of the processors 103-1 to 103-n displayed in (1).

The shared memory unit 104 is provided for each processor 10
3-1 to 103-n.

The operation of the load distribution type multiprocessor system 100 having such a configuration will be described with reference to the flowcharts of FIGS. However, FIG. 2 shows a data reception process, and FIG. 3 shows a reception data process and a process data transmission process.

In step ST201 of FIG. 2, the input / output control unit 105 constantly monitors data transmission / reception with the external device 109 by hardware polling to determine whether there is received data.

As a result of the judgment, if there is received data,
In step ST202, the input / output control unit 105
By comparing the load factors of the processors 103-1 to 103-n read via the monitoring bus 107 at the time of data reception, the processor with the lightest load factor (for example, 10
Select 3-1).

Next, in step ST203, the input / output control section 105 makes the selected processor 103-1
Is assigned to the received data as a destination, and then transferred via the monitoring bus 107.

Then, in step ST204, the relevant processor 103-1 fetches and stores the data in the transmission / reception buffer 102.

Also, in step ST301 of FIG. 3, the load monitoring unit 101 of the processor 103-1
At the time of data reception, a reception interrupt is detected, the cause of this interrupt is determined, and the data addressed to itself is captured.
Perform on 02.

The processor 103-1 receives the reception interrupt, masks the interrupt of the processor itself until the data is fetched, and releases the interrupt mask when the fetch is completed, so that the same processor 103-1 can receive the data. , That is, receiving another data during the receiving process.

In step ST302, the load monitoring unit 101 of the processor 103-1 adds a time stamp for measuring the processing delay time of the same data input / output to the transmission / reception buffer 102 to the reception data, and Stored in 102.

That is, the received data is transferred to the transmission / reception buffer 10.
2, when the data is stored in hardware, a counter value is attached by a time stamp function and held in the transmission / reception buffer 102;
In step ST304, the load monitoring unit 101
However, when the data is read from the transmission / reception buffer 102, the difference from the current counter value is internally stored as the processing delay time.

Next, in step ST305, the load monitoring unit 101 obtains a ratio between the maximum processing delay time (described later) stored in a table (not shown) and the processing delay time. The maximum processing delay time is the time from when data is input to when it is output when 100% of the data is stored in the transmission / reception buffer 102. For example, the maximum processing delay time is 10 seconds, and the processing delay time is 1 If it is seconds, the processing delay time ratio is 10%.

Next, in step ST306, the obtained processing delay time ratio is written into a register (not shown) of the input / output control unit 105 as a processor load factor. This is written as the latest state by polling each processor state collection from the input / output control unit 105.

In step ST307, the data processed by the processor 103-1 is transferred to the input / output bus 10
8 to the external device 109.

However, at the time of data reception, if there are a plurality of processors having the same load factor, the data is not re-distributed to the same processor until the data is distributed to all processors having the same load factor.

The trigger for determining the load factor is usually when data to be received is detected. However, there is a case where a plurality of identical processors exist and the load factor of the processor changes by the time of distribution of the next data. is there. In this case, when there is a processor having the same minimum load when all the processors are determined, the load factor is not monitored until the distribution to all the processors is completed.

Further, the input / output control unit 105 does not hold the passing data internally, but only controls the destination of the processor reception data sent from the external device 109. When the load of all the processors is low, Control for allocating received data to the processors in a round robin or other manner in order or at random, or control for allocating processing to a lightly loaded processor using a processor load factor may be used.

As described above, according to the load distribution type multiprocessor system 100 of the first embodiment, in the load monitoring units 101 of the plurality of processors 103-1 to 103-n, the external device 109 sends the information via the input / output bus 108. The ratio between the processing delay time, which is the time difference between the input and output of the received data to and from the transmission / reception buffer 102, and the maximum processing delay time, which is the maximum time difference between the input and output of data in the transmission / reception buffer 102, is determined as the load factor. In the unit 105, each of the processors 103-1 to 103-1 through the monitoring bus 107
The load factors of the processors 103-n are obtained, and the data received from the external device 109 is transmitted to the processor 103-1 having the lowest load factor.
The processing loads 1 to 103-n can be evenly distributed, and the processing performance can be improved with a simple configuration for both software and hardware.

(Embodiment 2) FIG. 4 is a block diagram showing a configuration of a load distribution type multiprocessor system according to Embodiment 2 of the present invention.

The load distribution type multiprocessor system 400 shown in FIG. 4 includes a plurality of processors 402-1 to 402-n each having a transmission / reception buffer 401, a shared memory unit 403, a load monitoring unit 404, and an arbitration unit. It has an input / output control unit 405, a memory bus 406, and an input / output bus 407.

The memory bus 406 is connected to the input / output control unit 405, each of the processors 402-1 to 402-n, and the shared memory unit 403.
Input / output control unit 405, each of processors 402-1 to 402
The -n transmission / reception buffer 401 and the external device 408 are connected.

The operation of the load distribution type multiprocessor system 400 having such a configuration will be described with reference to the flowcharts of FIGS. 5 shows a data reception process, and FIG. 6 shows a data transmission process.

In step ST501 of FIG. 5, the input / output control unit 405 determines whether or not there is received data by constantly monitoring data transmission / reception with the external device 408 by hardware polling.

As a result of this judgment, if there is received data,
In step ST502, the load monitoring unit 404 of the input / output control unit 405 transmits the
By comparing the load factors of 3-1 to 103-n,
The processor with the lightest load factor (for example, 402-1) is selected.

Next, in step ST503, the input / output control unit 405 sends the selected processor 402-1
Is assigned to the header of the received data as a destination, and in step ST504, the processor 40
An ID (Identifier) is assigned as the command 2-1.
The assignment of the ID may be thinned out, such as one out of ten received data.

Next, in step ST505, the input / output control section 405 stores the time stamp of the received data in its own table using its own timer function, and then transmits it to the processor 402-1.

In step ST506, when the processor 402-1 receives the transmitted data, the processor 402-1 detects a reception interrupt, determines the cause of the interruption, and fetches data addressed to itself by the transmission / reception buffer. Perform 401.

The processor 402-1 receives the reception interrupt, masks the interrupt of the processor itself until the data is fetched, and releases the interrupt mask when the fetch is completed, so that the same processor 402-1 can receive the data. , That is, receiving another data during the receiving process.

In step ST507, the processor 402-1 reads the data held in the transmission / reception buffer 401 and performs a predetermined process.

On the other hand, in step ST601 of FIG. 6, the load monitoring unit 404 of the input / output control unit 405 performs polling monitoring of transmission data transmitted from each of the processors 402-1 to 402-n to the external device 109, and It is determined whether or not there is.

As a result of this judgment, if there is transmission data,
In Step ST602, the command ID of the corresponding processor (for example, 402-1) is obtained. Next, in step ST603, the load monitoring unit 404 obtains a difference between the time stamp stored in the obtained ID table and the current time as a processing delay time.

Next, in step ST604, the load monitoring unit 404 obtains the ratio between the maximum processing delay time stored in a table (not shown) and the processing delay time.

Next, in step ST605, the obtained processing delay time ratio is written as a load factor of the processor 402-1 to a register (not shown) of the load monitoring unit 101 as the latest state.

In step ST606, the data processed by processor 402-1 is transferred to input / output bus 40.
7 to the external device 408. This is performed immediately without performing the processing of steps ST603 to ST605 if the ID is not assigned to the transmission data from the processor 402-1 in step ST602.

Further, the input / output control unit 405 does not hold the passing data internally, but only controls the destination of the processor received data sent from the external interface. May be controlled by allocating the received data in order or randomly by round robin or another method.

As described above, according to the load distribution type multiprocessor system 400 of the second embodiment, in the load monitoring unit 404 of the input / output control unit 405, the data reception time from the external device 408 and this data are processed by the processor. The ratio of the processing delay time, which is the difference from the time returned after the processing, and the maximum processing delay time, which is the maximum time of the processing delay time, is determined as a load factor, and the external device is sent to the processor with the lowest load factor. Since the received data from the 408 is transmitted, the processors 103-1 to 103-n
Load balancing control that matches the processing capacity of
Further, the processing performance can be improved with a simple configuration for both software and hardware.

In addition to the above, along with the maximum delay time when the processor load reaches 100%, which is provided for each processor, a delay time for judging a high load based on the time ratio of the maximum performance of the processor is provided in the table. For example, 90% of the maximum delay time is set as a high load, and the processor which has detected the high load by the input / output control unit 405 receives the maximum delay time, that is, the time when the processor finishes processing the received data accumulated in the buffer. In addition, the processor can be controlled not to allocate the received data.

[0078]

As described above, according to the present invention,
The processing load of each processor can be evenly distributed, and by performing load distribution control appropriate for the processing capacity of each processor, the processing performance can be improved with a simple configuration for both software and hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a load distribution type multiprocessor system according to a first embodiment of the present invention;

FIG. 2 is a flowchart for explaining an operation of a data reception process in the load distribution type multiprocessor system according to the first embodiment;

FIG. 3 is a flowchart for explaining operations of received data processing and processed data transmission processing in the load distribution type multiprocessor system according to the first embodiment;

FIG. 4 is a block diagram showing a configuration of a load balancing multiprocessor system according to a second embodiment of the present invention;

FIG. 5 is a flowchart for explaining an operation of a data reception process in the load balancing type multiprocessor system according to the second embodiment;

FIG. 6 is a flowchart for explaining an operation of a data transmission process in the load balancing multiprocessor system according to the second embodiment;

FIG. 7 is a block diagram showing a configuration of a conventional load balancing type multiprocessor system.

[Explanation of symbols]

100, 400 Load distribution type multiprocessor system 101, 404 Load monitoring unit 102 Transmission / reception buffer 103-1 to 103-n, 402-1 to 402-n Processor 104, 403 Shared memory unit 105, 405 Input / output control unit 106, 406 Memory bus 107 Monitoring bus 108,407 I / O bus 109,408 External device

Claims (10)

[Claims] 1. A holding means for holding data received from an external device, and a load monitor for determining, as a load factor, a ratio between a data input / output time difference to the holding means and a maximum data input / output time difference in the holding means. A plurality of processors having means, and input / output control means for controlling data transmission and reception between the plurality of processors and the external device, and transmitting received data from the external device to the processor having the lowest load factor. A load balancing type multiprocessor system, comprising: 2. An independent input / output bus and a monitoring bus, wherein data transmission and reception between a plurality of processors and an external device under the control of input / output control means are performed via the input / output bus. 2. The load distribution type multiprocessor system according to claim 1, wherein said input / output control means obtains a load factor from a load monitoring means. 3. The load-balancing type multi-processor according to claim 2, further comprising a memory bus independent of the input / output bus and the monitoring bus, and a plurality of processors accessing the shared memory means via the memory bus. Processor system. 4. A plurality of processors for processing data received from an external device, controlling transmission and reception of data between the plurality of processors and the external device, a data reception time from the external device, and a The ratio of the processing delay time, which is the difference between the time returned after the processing in the above, and the maximum processing delay time, which is the maximum time of the processing delay time, is determined as a load factor, and the processor with the lowest load factor is sent to the processor. An input / output control unit for transmitting data received from an external device. 5. An input / output bus and a memory bus which are independent of each other, and perform data transmission / reception between a plurality of processors and an external device under the control of the input / output control means via the input / output bus. 5. The load sharing multiprocessor system according to claim 4, wherein access to a shared memory unit is performed via said memory bus. 6. A base station apparatus comprising the load balancing type multiprocessor system according to claim 1. 7. A base station control apparatus comprising the load distribution type multiprocessor system according to claim 1. Description: 8. The base station apparatus according to claim 6, or claim 7.
A mobile communication system comprising the base station control device according to any one of the preceding claims. 9. A load ratio of a plurality of processors, which is a ratio of a time difference between input and output of data received from an external device via an input / output bus to a holding unit and a maximum time difference of data input and output in the holding unit. In the input / output control means for controlling data transmission / reception between the plurality of processors and the external device via the input / output bus, a load factor of the plurality of processors via a monitoring bus independent of the input / output bus. And transmitting the received data from the external device to the processor having the lowest load factor. 10. An input / output control means for controlling data transmission / reception between a plurality of processors and the external device via an input / output bus, wherein: a data reception time from the external device;
The ratio of the processing delay time, which is the difference between the time when this data is returned after processing by the processor, and the maximum processing delay time, which is the maximum processing delay time, is determined as the load factor. A load distribution control method, comprising transmitting received data from the external device to a low processor.