JP2001086039A - Semiconductor device and decision feedback equalizer - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device capable of reducing adjustment work for adjusting characteristics of a decision feedback equalizer. SOLUTION: An FIR equalizer 36 is provided in a stage preceding a DFE 37. The equalized signal is output to the DFE 37 by the FIR equalizer 36d. Also, F
The coefficients C1 to C5 of the IR equalizer 36d are stored in a coefficient updating circuit 3
The coefficient for minimizing the mean square error between the signal ya (n) output from the addition circuit 37b of the DFE 37 and the signal yb (n) as the result of the determination by the determination circuit 37c is calculated by 6e.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for demodulating and decoding a read signal from a read head in a hard disk device, a received signal in a high-speed communication device, and the like.

[0002] The hard disk drive is a read channel LS
The read channel LSI has a waveform equalizer for converting an analog signal read from a hard disk via a read head into a digital signal by an equalizer in the read channel LSI.

With the increase in recording density, a waveform equalizer is required to have an improved equalization capability and an improved error rate with respect to superimposed noise. Therefore, a decision feedback equalizer is used instead of the PRML waveform equalizer. Has been adopted. Also in this decision feedback type equalizer, further improvement in equalization capability and improvement in error rate with respect to superimposed noise are required, and a reduction in circuit size is also required.

[0004]

2. Description of the Related Art Generally, a hard disk drive has a read channel LSI. The read channel LSI is
An analog signal read from a hard disk is input via a read head, and various digital decoding processes are performed to generate read data. This read channel LSI
Is provided with a decision feedback equalizer for converting an analog signal read from a hard disk into a digital signal from which nonlinear intersymbol interference has been removed. This waveform equalizer is required to have an improved equalization capability and an improved error rate with respect to superimposed noise as the recording density of a hard disk is improved. Therefore, a decision feedback equalizer ( DFE (Decision Feedback Equalizer) is employed.

[0005] For example, the DFE described in Japanese Patent Application Laid-Open No. 10-83626 includes a forward equalizer (forward filter), an adder circuit, a code detector (judgment device), and a rear equalizer (feedback filter). The front equalizer and the rear equalizer are FIR (Fint
e Impulse Response) filter, and the characteristics of the two equalizers, that is, the coefficients, are set based on the detection result of the code detector.

[0006] In this way, an attempt is made to reduce errors due to manufacturing errors and noise from a head device (MR head) having nonlinear characteristics. That is, a constant signal is not always obtained in the DFE due to usage conditions, manufacturing variations, aging, and the like. If it deviates slightly from the ideal,
Many errors remain after the final playback. If this error remains, an error is likely to occur. Therefore, we want to reproduce (equalize) with the best possible characteristics. Therefore, the characteristics (coefficients) of the front equalizer and the rear equalizer of the DFE are automatically adjusted based on the reproduction state (the detection result of the code detector).

[0007]

By the way, in DFE, the correlation between the front equalizer (forward filter) and the rear equalizer (feedback filter) is very strong. That is, the coefficient of the rear equalizer (feedback filter) is determined by the characteristics of the front equalizer (forward filter). Therefore, when the coefficient of the forward equalizer (forward filter) is changed,
This means that the coefficients of the rear equalizer (feedback filter) must also be changed.

Therefore, an arithmetic circuit for changing the coefficients of the front equalizer (forward filter) and the rear equalizer (feedback filter) is required. This arithmetic circuit required the same number as the number of taps of each equalizer. Therefore, as the number of taps of the front equalizer (forward filter) and the rear equalizer (feedback filter) increases, the number of operation circuits increases, and the circuit scale of the DFE increases.

Further, the DFE is an element in which the feedback loop becomes unstable if the gain is increased in order to find the optimum coefficient for the front equalizer (forward filter) and the rear equalizer (feedback filter) in a short time and shorten the convergence time. Becomes On the other hand, when the forward equalizer (forward filter) and the backward equalizer (feedback filter) are adaptively equalized, there is a feedback loop, so that it is necessary to maintain stability at the expense of convergence time.

Further, the number of stages of the DFE is increasing due to the necessity of increasing the accuracy of the forward filter. With this increase, it is necessary to increase the gain of the forward filter itself and reproduce data with steeper characteristics. Furthermore, unlike the soft decision in the maximum likelihood decoding circuit used in the PRML method, the DFE performs decoding by hard decision, and therefore the gain of the equalizer is large to suppress decision errors. For this reason, if unknown distortion is superimposed on the input of the DFE, the equalization error tends to increase, making adaptive equalization difficult.

As described above, the DFE has a drawback that the automatic adjustment of the coefficient is difficult to converge, and the adjustment work for optimally adjusting the characteristics is extremely troublesome and time-consuming.
Further, since the DFE has a variation in the analog front-end characteristic on the input side of the DFE, coefficient training is performed to optimize a filter coefficient in accordance with the variation. However, the training work also has to be performed for the forward filter and the feedback filter, which requires much labor and time.

An object of the present invention is to provide a semiconductor device and a decision feedback equalizer which can reduce the adjustment work for adjusting the characteristics of the decision feedback equalizer.

[0013]

According to the first aspect of the present invention, the output signal from which noise has been removed by the FIR equalizer is input to the decision feedback equalizer. The type equalizer does not need to perform adaptive equalization of its own coefficient from time to time. As a result, it is only necessary to set the optimum coefficient for the known characteristic based on the FIR equalizer, and the adaptive equalization of the forward filter and the feedback filter of the decision feedback equalizer becomes unnecessary.

According to the second aspect of the present invention, an output signal from which noise generated in an analog signal system provided in a stage preceding the FIR type equalizer due to use conditions, manufacturing variations, aging, and the like has been removed is determined. Since the signal is input to the feedback equalizer, the decision feedback equalizer does not need to perform adaptive equalization of its own coefficient from time to time. As a result, it is only necessary to set the optimum coefficient for the known characteristic based on the FIR equalizer, and the adaptive equalization of the forward filter and the feedback filter of the decision feedback equalizer becomes unnecessary.

According to the third aspect of the present invention, the coefficient of the FIR type equalizer is updated based on the result of the decision made by the decision feedback type equalizer, that is, adaptive equalization is performed. The decision is made in a decision feedback equalizer.

According to the fourth aspect of the present invention, since the coefficient of the decision feedback equalizer is set to the optimum coefficient for the characteristics of the FIR equalizer, the decision feedback equalizer is used. The coefficient operation circuit for calculating the coefficients in the multiplier becomes unnecessary, and the circuit scale of the decision feedback equalizer can be reduced by the amount that the circuit for calculating the coefficients becomes unnecessary.

According to the fifth aspect of the present invention, an error between the replica signal corresponding to the periodic known write data and the read data equalized by the FIR equalizer with respect to the known write data. Since the coefficients of the FIR equalizer are updated based on the signal, that is, adaptive equalization is performed, adaptive equalization can be performed in a shorter time, and convergence can be improved.

According to the sixth aspect of the present invention, the FIR
Since the output signal from which noise has been removed by the (Finte Impulse Response) filter is input to the decision feedback equalizer, it is not necessary to perform adaptive equalization of the coefficients of the forward filter and the feedback filter each time.
As a result, it is only necessary to set the optimum coefficient for the known characteristic based on the FIR equalizer, and the adaptive equalization of the forward filter and the feedback filter of the decision feedback equalizer becomes unnecessary.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the hard disk drive 11. The hard disk device 11 is connected to a host computer 12. The hard disk device 11 records recording data input from the host computer 12 in response to a write request from the host computer 12 on a magnetic disk 13 as a recording medium. In addition, the hard disk device 11 reads the stored data recorded on the magnetic disk 13 in response to a read request from the host computer 12 and outputs the data to the host computer 12.

The hard disk drive 11 includes a magnetic disk 13, first and second motors M1 and M2,
4, a signal processing circuit 15, a servo circuit 16, a microprocessor (MPU) 17, a memory (RAM) 18, a hard disk controller (HDC) 19, and an interface circuit 20. The circuits 15 to 20 are connected to each other via a bus 21.

The magnetic disk 13 is driven to rotate at a constant rotational speed by the first motor M1. The position of the head device 14 is controlled in the radial direction of the magnetic disk 13 by the second motor M2. The head device 14 reads information recorded on the magnetic disk 13 and outputs the information to the signal processing circuit 15 as a read signal RD.

The signal processing circuit 15 is also called a read / write channel IC, and samples the read signal RD in synchronization with the read signal RD and converts it into a digital signal. The signal processing circuit 15 performs a decoding process on the converted digital signal, and outputs the signal after the decoding process.

The servo circuit 16 controls the second motor M2 based on the information for servo contained in the output signal of the signal processing circuit 15 via the bus 21 to make the head device 14 on-track to a target track.

The MPU 17 is a host computer based on program data stored in the RAM 18 in advance.
It analyzes a command for write / read processing and the like input from the CPU 21 and outputs a control signal to the HDC 19 and the like via the bus 21. The HDC 19 controls the signal processing circuit 15 and the servo circuit 16 based on a signal input from the MPU 17. The HDC 19 receives an output signal (data) of the signal processing circuit 15 via the bus 21.

The HDC 19 assembles the input data into sector units each having a predetermined number of bytes, and for each of the assembled sectors, for example, an ECC (Error Correcting Code).
And performs error correction processing and the like, and outputs the processed data to the interface circuit 20 via the bus 21.

The HDC 19 receives write data from the host computer 12 via the interface circuit 20. The HDC 19 adds data for error correction to the write data, and outputs the data to the signal processing circuit 15 via the bus 21. The signal processing circuit 15 includes an HDC 19
Output data from the magnetic disk 1 via the head device 14.
Write to 3.

Next, the configuration of the signal processing circuit 15 will be described with reference to FIG. Write data (write data) from the MPU 17 is input to the scrambler 32 via the first interface circuit 31. Scrambler 32
Performs a process of changing the order in which the bits of the write data are arranged by a predetermined method, and outputs the processed data to the encoder 33. The encoder 33 includes the scrambler 3
2 is output to a predetermined RLL code (run-le
ngth limited code: Specifically, encoding is performed based on RLL (1, 7) code). Further, the encoder 33
Adds control data such as preamble data for controlling the reading operation to the encoded data. Then, the encoder 33 outputs the processed signal to the write pre-competition 34.

The write pre-competition 34 uses the magnetic disk 1
3, a timing correction for correcting the timing of writing data to the memory 3 is performed. This timing correction is performed on the magnetic disk 13.
This is performed in order to prevent the position of the information (the magnetic poles corresponding to “1” and “0”) written in “1” from being shifted by the influence of the adjacent magnetic pole. The write pre-competition 34 outputs the data after the correction processing to the write flip-flop (write F / F) 35 in the NRZI format.

The write F / F 35 is a write pre-competition 3
4 to output a write signal WD to a write head 14a constituting the head device 14. The write head 14a is composed of a coil. The write F / F 35 supplies a current according to recording data to be written on the magnetic disk 13. By forming a magnetic pole on the magnetic disk 13 with this current, data including data, preamble, and sync byte are recorded on the magnetic disk 13.

Read head 1 constituting head device 14
4b is composed of an MR (Magneto Resistive) head.
The read head 14b outputs a read signal RD having a value corresponding to a change in the magnetic pole of the magnetic disk 13 to the preprocessing circuit 36.

The pre-processing circuit 36 amplifies the read signal RD, filters the read signal RD to a frequency suitable for demodulation and decoding, converts the digital signal into a digital signal, and then equalizes the digital signal to make a decision feedback equalizer (DFE). 37.

The DFE 37 is connected to a PLL circuit 38 for timing clock reproduction. PLL circuit 38
Is a read signal RD based on the output signal of the DFE 37.
To generate a sampling clock SCK synchronized with the sampling clock SCK. The DFE 37 converts the output signal of the preprocessing circuit 36 into a digital signal by performing waveform equalization processing based on the sampling clock SCK, and outputs the signal to the decoder 39.

FIG. 3 shows the structure of the DFE 37. DFE3
7 has a forward filter 37a, an addition circuit 37b, a determination circuit 37c, and a feedback filter 37d. The forward filter 37a is an FIR (Finte Impu
lse Response) filter, and the pre-processing circuit 36
Is output. Forward filter 37a
Outputs a signal having a waveform generated so as to maximize the S / N ratio of the input signal to the adding circuit 37b.

The addition circuit 37b includes the forward filter 3
A signal having an equalized waveform generated by adding the output signal of 7a and the feedback signal output from the feedback filter 37d is output to the determination circuit 37c.

The determination circuit 37c compares the amplitude of the equalized signal of the addition circuit 37b sampled based on the sampling clock SCK with a reference value, and determines whether the determination result is "1" or "0" based on the comparison result. The determination signal having the value is output to the feedback filter 37d.

The feedback filter 37d has an FIR
(Finte Impulse Response) filter, which operates to remove intersymbol interference contained in the signal. The feedback filter 37d outputs a feedback signal based on the determination signal to the adding circuit 37b. As a result, the determination signal becomes a reproduced signal from which interference due to past bits has been removed. The DFE 37 outputs this determination signal to the decoder 39 shown in FIG.

The decoder 39 decodes the output signal of the DFE 37 based on the RLL code, and outputs the decoded data to the descrambler 40. The descrambler 40 is
The bits of the output data of the decoder 39 are rearranged by a predetermined method to generate read data. The read data is sent to the MP via the second interface circuit 41.
Output to U17.

The DFE 37 outputs the processed signal to the control data detection circuit 42. Control data detection circuit 42
Detects control data (preamble, sync byte) for controlling the read operation of recording data and information (servo mark) for servo, and outputs a detection signal corresponding to the detected information to the sequence control circuit 43. MPU17
Output to

The sequence control circuit 43 receives the detection signal and a control signal for controlling writing / reading from the MPU 17. Sequence control circuit 43
Controls the circuits 31 to 42 according to a predetermined write / read sequence based on the detection signal and the control signal.

The MPU 17 includes a signal processing circuit 15
Input a sync byte detection signal after instructing a read operation to
Read data following the sync byte is treated as recording data (data), and processing is performed on the recording data.

Next, the pre-processing circuit 36 will be described with reference to FIG. The preprocessing circuit 36 includes an auto gain control amplifier (AGC) 36a, a low-pass filter 36b as an analog filter, an analog-digital conversion circuit (ADC) 36c, an FIR equalizer 36d, and a coefficient updating circuit 36e.

The AGC 36a outputs a signal generated by amplifying the read signal RD from the head device 14 to the low-pass filter 36b. The low-pass filter 36b has frequency characteristics suitable for demodulation and decoding, and outputs a signal generated by filtering the output signal of the AGC 36a to the ADC 36c. The ADC 36c samples the output signal of the low-pass filter 36b based on the sampling clock SCK, converts the signal into a digital signal, and outputs the digital signal to the FIR equalizer 36d.

The FIR type equalizer 36d includes a head device 14
The waveform is equalized with respect to the unknown transmission path Zx from the head device 14 including the head device 14 to the preprocessing circuit 36 and the transmission characteristics of the analog signal system from the AGC 36a to the low-pass filter 36b, and the equalized signal is converted into the DFE 37. Output to

The FIR type equalizer 36d has an FIR (Finte
Impulse Response) filter. FIG. 4 shows a block circuit of the FIR equalizer 36d. In FIG. 4, F
A plurality of IR equalizers 36d (five in this embodiment)
A shift register 51 including first to fifth registers 51a to 51e, and first to fifth multipliers 52a to 52e provided corresponding to the first to fifth registers 51a to 51e.
An adder 53 is provided.

The shift register 51 has first to fifth registers 51a to 51e. First to fifth registers 5
1a to 51e are cascaded, sample in synchronization with a sampling clock SCK, and output the sampled data to a register in the next stage. That is, the shift register 51 stores the sampled past data.

There are provided five first to fifth multipliers 52a to 52e corresponding to the first to fifth registers 51a to 51e. The first to fifth multipliers 52a to 52e store data D1 stored in the corresponding first to fifth registers 51a to 51e.
To D5 and a coefficient update circuit 36e
Input predetermined coefficients C1 to C5. The first to fifth multipliers 52a to 52e respectively multiply the data D1 to D5 by coefficients C1 to C5, respectively, and
Output to 3. The adder 53 includes first to fifth multipliers 52a.
５２52e are added and the added output Za
(N) is output to the DFE 37.

The coefficient updating circuit 36e minimizes the mean square error between the signal ya (n) output from the adding circuit 37b of the DFE 37 and the signal yb (n) as the result of the judgment by the judgment circuit 37c. The first to fifth multipliers 5
The coefficients C1 to C5 input to 2a to 52e are calculated. The calculation of each of the coefficients C1 to C5 is performed by LMS (Least Mean Square).
e) An algorithm is used and can be obtained by the following relational expression.

C1 = C1b + μ · D1 · ER C2 = C2b + μ · D2 · ER C3 = C3b + μ · D3 · ER C4 = C4b + μ · D4 · ER C5 = C5b + μ · D5 · ER C1b to C5b are coefficients before update, ER is addition The signal ya (n) output from the circuit 37b and the signal yb of the determination circuit 37c
(N) and the error amount (= ya (n) −yb (n)), D1 to
D5 is data stored in the first to fifth registers 51a to 51e, and μ is a step width.

The coefficient update circuit 36e includes an error calculation addition circuit 55 and a coefficient calculation circuit 56. The error calculation addition circuit 55 includes a signal ya (n) having an equalized waveform output from the addition circuit 37b of the DFE 37 and the determination circuit 3
The signal yb (n), which is the result of the determination in step 7c, is input. The error calculation addition circuit 55 adds an equalization error signal ER (= ya (n) -y) having an equalization error amount generated by adding the two signals.
b (n)) is generated and output to the coefficient operation circuit 56.

The coefficient operation circuit 56 is provided with the equalization error signal ER.
To input to the first to fifth multipliers 52a to 52e for minimizing the mean square error based on
Calculate C1 to C5. The coefficient calculation circuit 56 calculates the coefficients C1 to C5
A coefficient operation circuit section is provided for each coefficient. FIG. 5 shows a block circuit for calculating the coefficient C1.

In FIG. 5, a coefficient operation circuit 56 includes first and second registers 56a and 56b, a multiplier 56c, first and second addition circuits 56d and 56e, a gate circuit 56f,
A step width setting circuit 56g and an initial value setting circuit 56h are provided.

The first register 56a stores the FIR type equalizer 3
6d, the data D1 held by the first register 51a is input and synchronized with the sampling clock SCK.
Is output to the next-stage multiplier 56c.

The multiplier 56c receives, besides the data D1, the equalization error signal ER and a predetermined step width μ from the step width setting circuit 56g. The multiplier 56c outputs the data
D1, the equalization error signal ER and the step width μ are multiplied. The multiplier 56c outputs the operation result (= μ · D1 · ER) to the first adding circuit 56d.

The first adder circuit 56d includes a second register 56
output signal from b (the previous one, ie, coefficient C1b before update)
Is input, the coefficient C1b is added to the calculation result of the multiplier 56c, and the calculation result (= C1b + μ · D1 · ER) is added to the gate circuit 5.
6f. The gate circuit 56f receives the control signal CT from the MPU 17. Only when the control signal CT is at the H level, the gate circuit 56f outputs the output signal of the first addition circuit 56d to the second addition circuit 56e.

The second adding circuit 56e is provided with an initial value setting circuit 5
Input the initial value CIN from 6h. Second adder circuit 56e
Is initialized to the initial value when the first operation is performed.
After CIN is input, "0" is input from the initial value setting circuit 56h instead of the initial value CIN.

Accordingly, the second addition circuit 56e stores the initial value CIN in the second register 56
b. Thereafter, the second addition circuit 56e outputs the operation result (= C1b + μ · D1 · ER) of the first addition circuit 56d to the second register 56b.

The second register 56b receives the sampling clock SCK. The second register 56b synchronizes with the sampling clock SCK to generate a second adder 56e.
Is output to the first multiplier 56c of the FIR equalizer 54 as a new coefficient C1 (= C1b + μ · D1 · ER).

Therefore, the first multiplier 52a of the FIR type equalizer 36d multiplies the data D1 by using the new coefficient C1. Note that each coefficient operation circuit section of the coefficient operation circuit 56 for calculating the other coefficients C2 to C5 has the same configuration as that of the coefficient operation circuit section for calculating the coefficient C1, and thus is omitted for convenience of explanation.

Accordingly, the DFE equalizer 36d outputs the DFE
As the output signal output to 37, an equalized signal that minimizes the mean square error between the signal output from the addition circuit 37b and the signal that is the result of the determination by the determination circuit 37c is generated.

Next, effects of the first embodiment configured as described above will be described below. (1) In the present embodiment, the FIR equalizer 36d is provided before the DFE 37. The FIR equalizer 36
By d, the equalized signal is output to the DFE 37.
In other words, the output signal Z from which noise generated in the analog signal system due to usage conditions, manufacturing variations, aging, etc. has been removed.
a (n) is output to the DFE 37.

Therefore, the DFE 37 takes into account the noise caused by the usage conditions, manufacturing variations, aging, etc.
Since there is no need to automatically adjust the coefficients of the forward filter 37a and the feedback filter 37d, which are composed of FIR filters provided at 37, as in the prior art,
The coefficients of the forward filter 37a and the feedback filter 37d can be fixed. That is, DF
In E37, it is only necessary to set and fix an optimum coefficient for the characteristic of the FIR equalizer 36d.

As a result, unlike the related art, a coefficient calculation circuit for calculating the coefficient for each tap provided by the number of taps of the forward filter 37a and the feedback filter 37d is not required, and a circuit for coefficient calculation is not required. , The circuit scale of the DFE 37 can be reduced. More specifically, the coefficients C1 to C5 of the FIR equalizer 36d
Is provided, the number of taps (five in this embodiment) of the FIR equalizer 36d is determined by the number of taps of the forward filter 37a and the feedback filter 37d of the DFE 37. Far less. Therefore, the number of coefficients of the forward filter 37a and the feedback filter 37d can be much smaller than providing a coefficient operation circuit for each coefficient, and the circuit scale of the entire apparatus can be reduced.

(2) In this embodiment, the FIR type equalizer 3
Each of the coefficients C1 to C5 of 6d is converted into a signal ya output from the adder 37b of the DFE 37 by a coefficient update
(N) and the signal yb which is the result of the determination by the determination circuit 37c.
A coefficient that minimizes the mean square error between (n) and (n) is calculated.

That is, since the coefficients C1 to C5 of the FIR type equalizer 36d are updated based on the determination result of the DFE 37, that is, adaptive equalization is performed, a more accurate determination is made in the determination feedback type equalizer. be able to.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. For convenience of description, the same components as those in the first embodiment have the same reference numerals, and detailed description thereof will be omitted.

FIG. 6 shows a circuit configuration of the preprocessing circuit 36 and the DFE 37. As shown in FIG. 6, the preprocessing circuit 36
A replica signal generation circuit 58 and an addition circuit 59 are provided. The replica signal generation circuit 58, as shown in FIG.
It has a differentiating circuit 60 and an FIR filter 61.

The differentiating circuit 60 has an adding circuit 60a and a register 60b forming a delay circuit. Differentiating circuit 60
Inputs the read signal RD generated by the MPU 17 in advance for periodic known write data (such as printable data), differentiates the read signal RD by the adder circuit 60a and the register 60b, and supplies the differentiated read signal RD to the FIR filter 61. Output.

The FIR filter 61 has the same number of taps as the FIR equalizer 36d, and has five first to fifth FIR filters.
Shift register 62 including registers 62a to 62e
And first to fifth multipliers 63a to 63e provided corresponding to the first to fifth registers 62a to 62e, and an adder 64.
And a register 65 for output.

The shift register 62 has first to fifth registers 62a to 62e. First to fifth registers 6
2a to 62e are cascaded, sample in synchronization with the sampling clock SCK, and output the sampled data to the register of the next stage.

The data DA1 to DA5 stored in the first to fifth registers 62a to 62e are input to the corresponding first to fifth multipliers 63a to 63e, respectively. The first to fifth multipliers 52a to 52e receive data DA1 to DA5 and predetermined coefficients CA1 to CA5, respectively. Coefficient CA
1 to CA5 are predetermined values, and are values such that the read signal RD for the known write data (preprintable data or the like) is equalized with predetermined target characteristics.

The first to fifth multipliers 63a to 63e multiply the data DA1 to DA5 by coefficients CA1 to CA5, respectively, and output the operation results to the adder 64. Adder 64
Adds the operation results of the first to fifth multipliers 63a to 63e. Therefore, the added value (output) of the adder 64 is an output obtained by equalizing the read signal RD with respect to the predetermined write data (such as the printable data) with the predetermined target characteristic.

The added value (output) of the adder 64 is output to the register 65. The register 65 samples the output of the adder 64 in synchronization with the sampling clock SCK and outputs it to the addition circuit 59 as a replica signal Zb (n).

In other words, the replica signal generation circuit 58 outputs a signal that should be equalized with ideal characteristics to the DFE 37 based on the read signal RD generated by the MPU 17 in advance for the known write data and output ( A replica signal Zb (n)) is generated.

The adder circuit 59 includes a replica signal generation circuit 5
8 from the replica signal Zb (n) and the FIR equalizer 36d
From the output signal Za (n), and the deviation (= Za (n) −Zb
(n)). That is, the addition circuit 59 converts the replica signal Zb (n) and the read signal RD read from the actual head device 14 into the pre-processing circuit 36 (FIR equalizer 36).
An error from the output signal Za (n) equalized in d) is calculated. The adder 59 converts this error into an error signal err1 (= Za (n)
−Zb (n)) to the coefficient calculation circuit 56.

The coefficient calculation circuit 56 receives the error signal err1 and the equalization error signal ER from the error calculation addition circuit 55. The coefficient operation circuit 56 is provided by the MPU 17
, And selects one of the error signal err1 and the equalization error signal ER. Based on the selected error signal, each coefficient C1 of the FIR equalizer 36d is selected.
To C5 are calculated based on the relational expression in the LMS algorithm described above.

Therefore, when the error signal err1 is selected by the switching control signal SERC, the coefficients C1 to C5 of the FIR equalizer 36d are calculated based on the error signal err1. That is, the coefficient calculation circuit 56 includes coefficients C1 to C5 for minimizing the mean square error between the output signal Za (n) of the FIR equalizer 36d and the replica signal Zb (n) of the replica signal generation circuit 58.
Is calculated.

When the equalization error signal ER is selected by the L level switching control signal SERC, the equalization error signal ER
The coefficients C1 to C5 of the FIR equalizer 36d are calculated based on That is, the coefficient calculation circuit 56 calculates coefficients C1 to C5 that minimize the mean square error between the signal output from the addition circuit 37b of the DFE 37 and the signal that is the result of the determination by the determination circuit 37c.

In the present embodiment, the MPU 17
At the start of driving of C19 and when an error occurs due to an increase in the error, the switching control signal SERC is set to the H level, and the head device 14 outputs the known read data, that is, the printable data, from the information recorded on the magnetic disk 13. Is read, a read signal RD for the known preparable data is output to the replica signal generation circuit 58. Therefore, when the preparable data added in the sector is read, the read signal RD (prenable data) read from the head device 14 is converted to the pre-processing circuit 36 (FIR).
An error between the output signal Za (n) equalized by the type equalizer 36d) and the replica signal Zb (n) is calculated, and this error is converted into an error signal err1 (= Za (n) -Zb (n)). Coefficient operation circuit 5 based on
In 6, the optimum coefficients C1 to C5 are calculated.

At other times, the MPU 17
Sets the switching control signal SERC to the L level and does not output the read signal RD for the known preparable data to the replica signal generation circuit 58.

The pre-processing circuit 36 includes an AGC loop control circuit 66. The AGC loop control circuit 66
The equalization error signal ER and the error signal err1 are input. AG
The C loop control circuit 66 selects one of the error signal err1 and the equalization error signal ER based on the switching control signal SERC from the MPU 17, and determines the gain of the AGC 36a based on the amplitude error amount of the selected error signal. AGC3
The output signal 6a is controlled so as to have an optimum amplitude.

That is, when the error signal err1 is selected by the switching control signal SERC together with the coefficient operation circuit 56, the AGC loop control circuit 66 optimizes the gain of the AGC 36a based on the error signal err1. The AGC loop control circuit 66 optimizes the gain of the AGC 36a based on the equalization error signal ER when the equalization error signal ER is selected by the switching control signal SERC together with the coefficient calculation circuit 56.

The pre-processing circuit 36 includes a timing recovery PLL 67. Timing recovery P
LL67 inputs the equalization error signal ER. The timing recovery PLL 67 uses the sampling clock S of the ADC 36c based on the phase error amount of the equalization error signal ER.
Optimize the frequency of CK, and ADC3 at the optimal timing
6c is controlled to perform sampling.

Next, effects of the second embodiment configured as described above will be described below. (1) In the present embodiment, a replica signal generation circuit 58 is provided in addition to the effects of the first embodiment. The replica signal generation circuit 58 outputs a signal when the read signal RD such as the preparable data for the known write data such as the preparable data is equalized to the DFE 37 with ideal characteristics having no noise. (Replica signal Zb (n)). That is, the actual head device 1
The read signal RD for the write data such as the known preparable data read out from the preprocessing circuit 36 (F
The output signal Za (n) including the noise generated in the analog signal system due to the actual use situation, manufacturing variation, aging and the like equalized by the IR type equalizer 36d) is synchronized with the output and the replica signal is output. The generation circuit 58 generates an ideal replica signal Zb (n) that does not include the noise.

Then, based on the replica signal Zb (n) and the actual output signal Za (n), the adding circuit 59 outputs the error signal err.
1 (= Za (n) -Zb (n)), and this error is represented by an error signal err.
On the basis of 1, the coefficient calculation circuit 56 calculates the optimum coefficients C1 to C5.

Therefore, the magnitude of the error with respect to the noise can be accurately obtained. Moreover, the calculation (training) of the coefficients C1 to C5 can shorten the training loop by the amount not passing through the DFE 37, and can improve the convergence.

(2) In this embodiment, the error signal err1
Since the gain of the AGC 36a can be controlled based on (= Za (n) -Zb (n)), the optimum gain can be similarly set in a short time without passing through the DFE 37.

The embodiments of the present invention are not limited to the above embodiments, but may be implemented as follows. In the second embodiment, the replica signal Zb (n) is generated based on the preparable data. However, the replica signal Zb (n) may be implemented using sync data which is known data.

Further, the replica signal Zb (n) may be generated by using two known data, ie, the preparable data and the sync data. In the second embodiment, the replica signal Zb (n) is generated based on the preparable data. However, a dedicated training pattern may be prepared and executed. In this case, the pattern is applied to the magnetic disk 1 by the write head 14a.
3, and the written pattern is read by the read head 14b. On the other hand, based on an ideal read signal for the pattern, the replica signal generation circuit 5
8 generates a replica signal Zb (n).

In the second embodiment, the coefficients C1 to C5 are calculated using either the error signal err1 or the equalization error signal ER. However, the calculation may be performed using only the error signal err1. In the second embodiment, the calculation of the coefficients C1 to C5 using the error signal err1 is performed at the start of driving or when an error occurs.However, the present invention is not limited to this. For example, the printable data is read. It may be performed every time.

In the first embodiment, the coefficients C1 to C5 of the FIR equalizer 36d are calculated based on the equalization error signal ER in the second embodiment and the error signal err1 and the equalization error signal ER in the second embodiment. However, the coefficients C1 to C1 of the FIR equalizer 36d
C5 may be fixed. In this case, the coefficients C1 to C5 of the FIR type equalizer 36d are determined according to the usage status, manufacturing variation,
In order to output an output signal Za (n) from which noise generated in an analog signal system due to aging or the like has been removed, a coefficient is required.
A test may be performed to determine what to do with C1 to C5, and the coefficients C1 to C5 determined by the test may be fixed.
Also in this case, the load on the DFE 37 is reduced.

In each of the above embodiments, the forward filter 37a and the feedback filter 37 of the DFE 37 are used.
Although the coefficient of d is fixed, for example, adaptive equalization may be performed based on the equalization error signal ER. In this case, the circuit size is increased, but more accurate determination is possible.

In the above embodiments, the DFE 37 provided with the FIR equalizer 36d at the preceding stage is embodied in the read / write channel IC of the hard disk device. Of course, F
The present invention may be implemented as a semiconductor device including only the DFE 37 provided with the IR type equalizer 36d.

In each of the above embodiments, the DFE 37 provided with the FIR equalizer 36d at the preceding stage is embodied in a hard disk device, but may be applied to a DFE used in a baseband digital communication system, for example.

[0095]

According to the first to sixth aspects of the present invention, F
It is only necessary to set the optimum coefficient for the known characteristic based on the IR type equalizer, and the adaptive equalization of the forward filter and the feedback filter of the decision feedback type equalizer becomes unnecessary. The adjustment work for adjusting the characteristics can be reduced.

In addition, according to the third aspect of the present invention,
A more accurate decision can be made in a decision feedback equalizer. In addition, according to the invention described in claim 5,
Adaptive equalization is performed in a shorter time, and convergence can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a hard disk device.

FIG. 2 is a block circuit diagram of a signal processing circuit.

FIG. 3 is a block circuit diagram of a preprocessing circuit and a DFE.

FIG. 4 is a block circuit diagram of an FIR type equalizer;

FIG. 5 is a block circuit diagram of a coefficient operation circuit.

FIG. 6 is a block circuit diagram of a preprocessing circuit and a DFE according to a second embodiment;

FIG. 7 is a circuit diagram of a replica signal generation circuit according to a second embodiment.

[Explanation of symbols]

 Reference Signs List 11 hard disk device 14 head device 15 signal processing circuit 36 preprocessing circuit 36a auto gain control amplifier (AGC) 36b low-pass filter 36c analog-digital conversion circuit (ADC) 36d FIR equalizer 36e coefficient updating circuit 37 decision feedback equalization (DFE) 37a Forward filter 37b Addition circuit 37c Judgment circuit 37d Feedback filter 55 Addition circuit 56 Coefficient operation circuit 58 Replica signal generation circuit 59 Addition circuit 66 AGC loop control circuit 67 Timing recovery PLL C1-C5, CA1-CA5, C1b- C5b coefficient RD Read signal Zb (n) Replica signal Za (n) Output signal ER Equalization error signal err1 Error signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaru Sawada 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi F-term in Fujitsu VSI Co., Ltd. 5D044 BC01 CC04 FG02 5K029 AA03 CC07 GG03 GG05 HH06 5K046 AA01 DD13 EE06 EE10 EE52 EF13 EF19 EF46

Claims (6)

[Claims] An FIR (Fint) is provided before a decision feedback equalizer.
A semiconductor device provided with an (e Impulse Response) type equalizer. 2. The semiconductor device according to claim 1, wherein the FIR equalizer includes an auto gain control amplifier provided before the FIR equalizer, and an analog front end system including an analog filter. A semiconductor device, wherein a transmission path characteristic is adaptively equalized to a predetermined transmission characteristic. 3. The semiconductor device according to claim 1, wherein the FIR is based on a decision result of the decision feedback equalizer.
A semiconductor device comprising a coefficient updating circuit for updating a coefficient of a type equalizer. 4. The semiconductor device according to claim 1, wherein a coefficient of the decision feedback equalizer is set to an optimum coefficient for characteristics of the FIR equalizer. Semiconductor device. 5. The semiconductor device according to claim 1, wherein a replica signal corresponding to the known write data is generated,
The replica signal and F for the known write data
A semiconductor device comprising: a coefficient update circuit for obtaining an error signal from read data equalized by an IR equalizer and updating a coefficient of the FIR equalizer based on the error signal. . 6. A decision feedback equalizer including a forward filter, an adder circuit, a decision circuit, and a feedback filter, wherein a FIR (Finte Impulse Re-Frequency) is provided before the forward filter.
sponse) A decision feedback equalizer comprising a filter.