JP2001085309A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reliably and quickly detect characteristic defects due to dimensional variations in shots during exposure and improve the reliability of a semiconductor device. SOLUTION: In one shot area SA at the time of exposure,
When the four semiconductor chips 2a to 2d are irradiated, TEGs 4a to 4d are respectively formed in the scribe areas 3 near the corners in the one shot area SA, and the scribe areas 3 in the center of the one shot area SA are formed. Is formed TEG4e. If a defect in the electrical characteristics of a certain semiconductor chip is detected during a probe test of the semiconductor wafer 1, the characteristics of the defective semiconductor chip are determined based on the results of the probe test in the TEG closest to the defective area or the dimensional variation in the shot. By detecting the defect, it is possible to perform a fade-back to the manufacturing process at an early stage, and to improve the manufacturing yield of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a TEG (Test) in an exposure process.
The present invention relates to a technology that is effective when applied to the formation of an element group.

[0002]

2. Description of the Related Art According to studies made by the present inventor, in an exposure step which is one of manufacturing steps of a semiconductor device,
A combination of a plurality of masks or reticles on which individual patterns are formed is used.

The so-called alignment for making an existing pattern on a semiconductor wafer and a design pattern for the next process an optimal relative positional relationship is called an alignment target formed on the semiconductor wafer for alignment and a next process. High-precision alignment is performed by overlapping an alignment target for alignment formed on a mask or reticle of a design pattern.

As a technique for reducing the amount of misrecognition of an alignment target and inspecting an accurate alignment target position, for example, as disclosed in Japanese Patent Application Laid-Open No. After forming a registration mark made of resist only on the scribe area in one direction of the scribe area in the Y direction and providing a portion without resist around the registration mark, the offset value of the resist pattern is determined based on the registration mark. Is known.

Further, a TEG is formed in a scribe area of a semiconductor wafer. The TEG is formed from a group of test elements for circuit evaluation and process characteristic evaluation. In the exposure, only one TEG is formed in one shot which is an area irradiated by one exposure, and is formed at an arbitrary position in the scribe area.

[0006]

However, the present inventor has found that the above-described technique for recognizing a position in an overlay mark has the following problems.

That is, although the overlay accuracy of the resist pattern can be controlled by the overlay mark, it is difficult to control the variation in the dimension within the shot, and electrical characteristics failure due to the variation in the dimension within the shot occurs. There is a risk of doing it.

[0008] The characteristic failure of the semiconductor device due to the variation in the dimension in the shot can be confirmed by, for example, a destructive inspection of the semiconductor device. In this case, since the failure analysis is prolonged, early measures are taken. And the like, there is a problem that the number of man-hours required for inspection increases.

Further, the cause of the characteristic failure can be found from the dimensional variation in the TEG formed in the scribe area of the semiconductor wafer and the inspection result of the probe test. However, as described above, only one TEG is formed in one shot, and the position where the TEG is formed is not clearly defined.

Therefore, the T within the formed shot
Depending on the position of the EG and the position of the semiconductor chip, the dimensional difference between the semiconductor chip and the semiconductor chip may be large, and the characteristic defect may not be reflected. Has become difficult.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reliably and quickly detecting a characteristic defect due to dimensional variations in a shot during exposure and improving the reliability of the semiconductor device. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, at least five TEGs are formed by scattering at least five TEGs in a scribe area in one shot area where at least four semiconductor chips are irradiated by one exposure. One of the at least five TEGs is provided near the center of the scribe area, and at least four of the remaining TEGs are provided.
One TEG is provided at a position farthest from the one TEG.

Further, a method of manufacturing a semiconductor device according to the present invention
4 of the at least four TEGs are 1
It is provided at each corner of a scribe area located in the shot area.

Further, in the method of manufacturing a semiconductor device according to the present invention, a TEG is formed in a corner portion in a one-shot region where four semiconductor chips are irradiated by one exposure, and a scribe area in a central portion. .

As described above, the cause of the defective semiconductor chip can be easily grasped in a short time from the electrical characteristics of the TEG located in the vicinity of the defective semiconductor chip and the dimensional variation in the shot. The production yield can be improved.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a TE according to an embodiment of the present invention.
FIG. 2 is an explanatory view of a semiconductor wafer on which G is formed. FIG. 2 is an explanatory view of an arrangement of TEGs formed on the semiconductor wafer when exposure is performed by one shot / 4 chip according to an embodiment of the present invention. 1 shot / 4 examined by the inventor
FIG. 4 is an explanatory view of the arrangement of TEGs formed on a semiconductor wafer when exposure is performed by a chip.

In this embodiment, as shown in FIG. 1, a semiconductor wafer 1 made of a single crystal such as silicon
A plurality of semiconductor chips 2 on which integrated circuits composed of semiconductor elements are formed are formed. These semiconductor chips 2
Are formed in an array in the horizontal and vertical directions of the semiconductor wafer 1 regularly.

A scribe area 3 is provided around the outer periphery of the semiconductor chip 2 on the semiconductor wafer 1 so as to cut each semiconductor chip 2 from the semiconductor wafer 1 individually.

At predetermined positions of these scribe areas 3, a plurality of TEGs 4 are formed as shown in FIG. The TEG 4 is a test element group for circuit evaluation and process characteristic evaluation during a wafer test.

In the TEG 4, five TEGs 4a to 4e are formed in each scribe area 3 in an area irradiated by one exposure, that is, a so-called one shot area SA.

Here, one shot area SA, which is an area irradiated on semiconductor wafer 1 in one exposure, is applied to areas of four semiconductor chips 2a to 2d in one shot, as shown in FIG. , So-called 1 shot / 4 chips.

Semiconductor chips 2a to 2 in one shot area SA
Scribe area 3 near each corner in 2d
, Four TEGs 4a to 4d are formed respectively, and a TEG 4e is formed at the center of the four semiconductor chips 2a to 2d in one shot area SA.

Further, when the number of semiconductor chips in one shot area SA is more than four and the scribe area is not located at the center of one shot area SA, one chip is located near the center.
One or more TEGs are formed, and at least one TEG is also formed near one side of each semiconductor chip.
It is formed so that EG is located.

Next, the operation of the present embodiment will be described.

First, when the semiconductor chips 2 on which integrated circuits are formed on the semiconductor wafer 1 and the TEG 4 are formed, a probe test of the semiconductor wafer 1 is performed. In this probe test, first, the semiconductor wafer 1
A test of the electrical characteristics of the TEG 4 formed on the substrate is performed.

Thereafter, a probe needle is applied to a bonding pad formed on the semiconductor chip 2 to test the electrical characteristics of the integrated circuit in the semiconductor chip 2. In this probe test, for example, if a defect in the electrical characteristics is detected on the upper left side of the semiconductor chip 2a in FIG. 2, the inspection result of the probe test in the TEG 4a closest to the defective region, or the dimensional variation in the shot, etc. The cause of the characteristic failure in the semiconductor chip 2a can be detected.

Here, the layout of the TEG 30 in the one-shot area SA1 studied by the inventor will be described with reference to FIG.

Also in this case, one TEG 30 is formed in one shot area SA1 irradiated by one exposure. In the one-shot area SA1, the areas of the four semiconductor chips 31 to 34 are exposed to form a so-called one-shot / 4 chip.

A scribe area 35 for individually cutting the semiconductor chips 31 to 34 from the semiconductor wafer 1 is provided around the periphery of the semiconductor chips 31 to 34.

The TEG 30 has a one-shot area SA.
1 is formed in a scribe area 35 between the semiconductor chip 31 and the semiconductor chip 32. This TEG
The formation position of 30 is not defined and is arbitrary.

In this case, for example, even if an electrical failure is detected in the lower right area of the semiconductor chip 33, the electrical characteristics and the shot in the shot will be increased because the distance between the defective area of the semiconductor chip 33 and the TEG 30 is large. In some cases, dimensional variations and the like do not match, and the cause of the characteristic failure in the semiconductor chip 33 cannot be found.

However, by providing the TEGs 4 in the vicinity of the respective semiconductor chips 2 in the shot as in the present embodiment, it is possible to easily detect the TEG reflected on the electrical characteristics of the defective semiconductor chip.

Thus, in the present embodiment, the cause of the defective semiconductor chip 2 can be easily grasped in a short time from the electrical characteristics of the TEG 4 formed in the vicinity of the defective semiconductor chip 2. Feedback in a short period of time, and it is possible to improve the manufacturing yield of semiconductor devices by taking early measures.

Further, since the cause of the failure can be grasped in the probe test, a destructive inspection or the like of the semiconductor device becomes unnecessary, and the failure analysis and the like can be performed efficiently.

Further, in the present embodiment, the cause of the defective semiconductor chip 2 is investigated by using the TEGs 4a to 4e. For example, the patterns in the TEGs 4a to 4e are changed by SEM (scanning electr).
on Microscope) to measure the dimensional variation, or
It may be used as a defect check of alignment between different layers by EM. In the case of a defect check for different layer alignment, if a short circuit has occurred, the contrast differs due to charge-up, and a defect can be found.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0040]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by forming at least five TEGs in the scribe area in one shot area by scattering them, the TEGs can be located near the respective semiconductor chips, and the defective From the TEG located near the semiconductor chip, the cause in the semiconductor chip can be easily grasped in a short time.

(2) Further, according to the present invention, according to the above (1), it is possible to take early measures against a defect in a semiconductor device manufacturing process, and it is possible to improve a semiconductor device manufacturing yield.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a semiconductor wafer on which a TEG according to an embodiment of the present invention is formed.

FIG. 2 is a diagram illustrating the arrangement of TEGs formed on a semiconductor wafer when exposure is performed by one shot / 4 chip according to an embodiment of the present invention.

FIG. 3 shows a TE formed on a semiconductor wafer when exposure is performed by one shot / 4 chip examined by the present inventors.
It is an arrangement explanatory view of G.

[Explanation of symbols]

 Reference Signs List 1 semiconductor wafer 2 semiconductor chip 2a to 2d semiconductor chip 3 scribe area 4 TEG 4a to 4e TEG 30 TEG 31 to 34 semiconductor chip 35 scribe area

Claims (3)

[Claims] 1. A method according to claim 1, wherein at least five TEGs are formed by scattering at least five TEGs in a scribe area in one shot area where at least four semiconductor chips are irradiated by one exposure, and one of the at least five TEGs is formed. T
A method of manufacturing a semiconductor device, wherein an EG is provided near a center of the scribe area, and at least four remaining TEGs are provided at positions farthest from the one TEG. 2. The method of manufacturing a semiconductor device according to claim 1, wherein four of the remaining at least four TEGs are provided in a corner portion of a scribe area located within one shot region. A method for manufacturing a semiconductor device. 3. A method of manufacturing a semiconductor device, comprising: forming a TEG in a corner portion in a one-shot region where four semiconductor chips are irradiated by one exposure and a scribe area in a central portion.