JP2001077679A - Inverter and switched capacitor circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switched capacitor circuit, capable of reliably reducing noise using simple constitution. SOLUTION: In an inverter to be used in a switched capacitor circuit, respective gate widths WP and WN of a gate electrode 9 superimposed on a P-type diffused region 3 and the electrode 9 superimposed on an N-type diffused region 7 are nearly matched and the gate length of one or more gate electrodes 9 superimposed on the region 7 or a total sum LN of gate lengths is made larger than the gate length of one or more gate electrodes 9 superimposed to the region 3 or a total sum LP of gate lengths to nearly match the drain-side area of the region 3 with that of the region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor circuit used for A / D, D / A converters, etc., and more particularly to a switched capacitor circuit with reduced noise.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional low-pass filter using a switched capacitor. In FIG. 4A, AMP is a differential amplifier, SW1 and SW2 are analog switches, C1 to C3 are capacitors, Cp1 and Cp.
2 indicates a parasitic capacitance, and φ1 and φ2 indicate clock signals for driving an analog switch as shown in FIG. In this example, each analog switch receives the clock signal φ
1, ON / OFF from φ2, thereby operating as a low-pass filter. As the analog switch, a field-effect transistor having a high off-resistance and advantageous for making the device monolithic is often used.

[0003] However, such analog switches include factors that degrade circuit characteristics. For example, a parasitic capacitance Cp1 is formed between the analog switch SW1 and the capacitor C1 in FIG.
A parasitic capacitance Cp2 is formed between W2 and capacitor C2. Similarly, although not shown, a parasitic capacitance is formed for each of the other switches.

Here, when the analog switch SW1 is turned on, the clock signal φ1 also charges the capacitor C1 through the parasitic capacitance Cp1. This becomes clock feed-through noise and deteriorates characteristics. On the other hand, since the analog switch SW2 is also turned on at the same time, the clock signal φ
1 is charged in the capacitor C2 through the parasitic capacitance Cp2. Further, since the analog switches SW1 and SW2 are connected to a common clock signal line (not shown), the noise of the analog switch SW2 reduces the capacitance of the capacitor C1.
And the noise of the analog switch SW1 is
And the analog switches affect each other.

It is known that each of the above parasitic capacitances is affected by the size of an analog switch, the size of an inverter driving the switch, and the like. FIG. 5 is a layout diagram showing an example of the inverter. In this figure, 1 is a metal electrode connected to a power supply, 2 is a contact, 3 is a P-type diffusion region, 4 is a drain-side diffusion region of the P-type diffusion region 3, 5 is a metal electrode serving as an output, and 6 is an N-type diffusion region. Reference numeral 7 denotes a drain-side diffusion region of the N-type diffusion region 6, reference numeral 8 denotes a metal electrode connected to the ground, and reference numeral 9 denotes a gate electrode.

Normally, the gate width is designed to be about P: N = 2: 1 in order to match the rise and fall times due to the difference in the transconductance of the PN. In this case, since the area of the source / drain is different between P and N, the parasitic capacitance is also different. In this case, the noise is different between the rising edge and the falling edge. This difference in noise has a greater effect when the filter of FIG. 4 is configured by a differential system.

To cope with such a problem, there is a method of reducing clock feedthrough noise by connecting a noise compensation switch to an analog switch and supplying a clock signal having an opposite phase. FIG. 6 is a circuit diagram showing this example. In FIG. 6, SW3 is a normal analog switch composed of a P-type MOS transistor PMOS1 and an N-type MOS transistor NMOS1, and SW4 and SW5.
Are NMOS2 and PMOS2 and NMOS3, respectively.
And a noise compensating switch composed of PMOS3.

As shown in FIG. 1, SW4 and SW5 are SW
3, the drain and source of each transistor of SW4 are connected to the drain of each transistor of SW3, and the drain and source of each transistor of SW5 are connected to SW
3 are commonly connected to the source of each transistor. P
A positive-phase clock signal φn is applied to the gates of the MOS1, NMOS2, and NMOS3.
A clock signal φnb having a phase opposite to that of the clock signal φn is applied to the gates of S2 and PMOS3. Although not shown,
The clock signal φnb having the opposite phase is generated from φn through an inverter.

With such a configuration, for example, a PMO
The noise generated when S1 is turned on can be canceled by the noise generated when the PMOS2 and PMOS3 to which the clock signal of the opposite phase is applied are turned off.

[0010]

However, in the circuit to which the noise compensation switch is added as described above, a transistor is added, and as a result, the area of the drain is increased and the parasitic capacitance is increased. Compensation is required, and the design becomes difficult. In addition, since the layout area for that purpose also increases, there has been a problem that the chip unit price increases.

Further, even if the above-described noise compensating switch is added, the switched capacitor circuit as shown in FIG. 4A cannot prevent interference between the switches.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a switched capacitor circuit capable of reliably reducing noise such as feedthrough noise with a simple configuration.

[0013]

In order to achieve the above object, a first aspect of the present invention comprises a capacitor and a plurality of analog switches each comprising a P-type MOS transistor and an N-type MOS transistor for charging and discharging the capacitor. And an inverter used in a switched capacitor circuit that is driven by applying positive and negative phase clock signals to two gates of the analog switch, respectively.
The gate widths of the gate electrode overlapping the P-type diffusion region and the gate electrode overlapping the N-type diffusion region are substantially equal, and the gate length or the gate length of one or more gate electrodes overlapping the N-type diffusion region Is greater than the gate length or the sum of the gate lengths of one or more gate electrodes overlapping the P-type diffusion region, and the drain-side area of the P-type diffusion region and the drain-side area of the N-type diffusion region The feature is that they substantially match.

With such a structure, the parasitic capacitance between the drain and the gate electrode of the P-type diffusion region and the parasitic capacitance between the drain and the gate of the N-type diffusion region are made smaller to eliminate the difference, and the difference between the conductances of the respective transistors is reduced. can do.

A second invention relates to a capacitor, a P-type MOS transistor for charging and discharging the capacitor, and an N-type MOS transistor.
A plurality of analog switches comprising S-transistors, wherein a positive-phase clock signal and a negative-phase clock signal are applied to two gates of the analog switches to drive the analog switches. The output of the inverter is connected and inserted into each of two gates of the analog switch.

With this configuration, all the gates of the analog switch to which the same clock signal is input are made independent, and no current path connecting the gates is formed.

According to a third aspect, in the second aspect,
The inverter according to the first aspect of the present invention is further connected to the inverter connected to one of the two gates of the analog switch, and the inverter forms a reverse-phase clock signal from the positive-phase clock signal. I do.

With this configuration, all the inverters used in the switched capacitor circuit can have a common structure.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The same or corresponding components are denoted by the same reference symbols throughout the drawings, and description thereof will be omitted.

FIG. 1 is a pattern diagram showing an example of the inverter according to the first invention. As shown in the figure, substantially aligned with the gate width W _P and W _N of the gate electrode 9 to be superimposed on each of the P-type diffusion regions 3 and the N-type diffusion region 6, a gate length L _N
Is larger than L _P, and the respective areas of the P-type drain-side diffusion region 4 and the N-type drain-side diffusion region 7 are made substantially equal.

The transconductance of a MOS transistor is proportional to the resistivity of the diffusion region and the gate width W, and is inversely proportional to the gate length L. In the inverter of the present invention, the width of the P-type diffusion region 3 having a high resistivity is narrowed and the gate width W _P of the gate electrode 9 overlapping with the P-type diffusion region 3 is shortened. Increase the gate length L _N ,
The P-type MOS transistor and the N-type MOS transistor have the same mutual conductance.

Further, since the drain diffusion region has an area substantially equal to P and N, the parasitic capacitance between the gate and the drain with respect to the metal electrode 5 is a P-type MOS transistor, N
Since both types of MOS transistors are substantially constant, noise at the time of rising and falling when the analog switch is turned ON / OFF can be made substantially uniform. Therefore,
This inverter is suitably applied to a switched capacitor circuit configured by a differential method.

FIG. 2 is a diagram showing another example of the inverter according to the first invention. FIG. 2 (a) is a pattern diagram, and FIG.
(B) shows a circuit diagram. The difference from FIG. 1 is that two gate electrodes overlap the N-type diffusion region 6. At this time, the sum of the gate lengths L _N1 and L _N2 of each gate electrode is equal to L _N in FIG. As shown in FIG. 2B, the circuit diagram has a configuration in which an N-type MOS transistor is further connected in series beside the N-type MOS transistor of a normal inverter including a P-type MOS transistor and an N-type MOS transistor. Become.

As described above, in the first invention, a plurality of gate electrodes may be formed. This is not a gate electrode overlapping the N-type diffusion region but a gate electrode overlapping the P-type diffusion region. Is also good. However, the gate length L _P or L _N at that time, a sum of the gate length of the divided gate electrode.

FIG. 3 is a diagram showing an embodiment of a switched capacitor circuit according to the second invention. FIG. 3A is a schematic diagram of the entire circuit in which the periphery of each analog switch is equivalently replaced with a transmission switch. FIG. 3B shows details of the periphery (G1) of the analog switch. In this figure,
G1 and G2 are switches equivalently showing the periphery of the analog switch by transmission gates, φ1b is a clock signal having a phase opposite to φ1, and φ2b is a clock signal having a phase opposite to φ2.

The difference from the conventional analog switch is that, as shown in FIG. 3B, an inverter 10 is inserted in each gate of the conventional analog switch SW1. The inverter 10 is the same as that shown in FIG. 2, and its output is connected to a gate, and positive and negative phase clock signals φ1 and φ1b are applied, respectively.

The switched capacitor circuit of the present invention has a P
Since the type MOS transistor and the N-type MOS transistor are individually driven by the inverter, it is possible to prevent noise interference between the analog switches. That is, by inserting the inverter, the gates of the analog switches can be individually cut off from the current paths connecting the gates of the plurality of analog switches.

Also, the parasitic capacitance of each of the analog switch SW1 and the inverter 10 is connected in series. As a result, the combined capacitance becomes a parasitic capacitance.
Parasitic capacitance is lower than the conventional one without 0,
The noise level is also reduced.

Next, the third invention will be described. FIG.
In (a), the clock signals φ1 and φ1b and the clock signals φ2 and φ2b are separately generated in advance by a clock (not shown) and a counter, respectively. And φ2b. At this time, the inverter of FIGS. 1 and 2 according to the first invention is further connected to an inverter connected to one of two gates of the analog switch of the switched capacitor circuit of FIG. 3 according to the second invention. This is an embodiment of the switched capacitor circuit according to the third invention.

According to this, all the inverters used in the circuit can have a common structure, and the shapes of the noise at the time of rising and falling can be further matched.
When the analog switches are driven by these inverters, noise at the time of rising and noise at the time of falling cancel each other out, so that a circuit with extremely low noise can be configured.

[0031]

As described above, according to the first aspect of the present invention, the difference between the parasitic capacitance and the mutual conductance between the P-type MOS transistor and the N-type MOS transistor can be reduced, so that the rise and fall of the inverter can be reduced. It is possible to reduce a difference in noise generated at the time, and to provide a suitable inverter applied to a switched capacitor circuit having a differential configuration.

According to the second aspect of the present invention, it is possible to realize a switched capacitor circuit such as a filter in which characteristic deterioration is reduced by preventing interference of noise between switches and reducing a change in noise due to a switch state.

According to the third aspect, since the noise at the time of rising and the noise at the time of falling cancel each other out, it is possible to provide a switched capacitor circuit such as a filter having very little noise.

[Brief description of the drawings]

FIG. 1 is a pattern diagram showing an example of an inverter according to a first invention.

FIG. 2 is a diagram showing another example of the inverter according to the first invention.

FIG. 3 is a diagram showing an embodiment of a switched capacitor circuit according to the second invention.

FIG. 4 is a diagram illustrating an example in which a low-pass filter is configured by a conventional switched capacitor circuit.

FIG. 5 is a pattern diagram of a conventional inverter for applying a clock signal.

FIG. 6 is a circuit diagram showing an example of a conventional analog switch to which a noise compensation switch is added.

[Explanation of symbols]

 1, 5, 8: electrode, 2: contact, 3: P-type diffusion area
Region 4: Drain diffusion region of P-type MOS transistor
Region, 6: N-type diffusion region, 7: N-type MOS transistor
Drain side diffusion region, 9: gate electrode, 10: of the present invention
Inverter, AMP: differential amplifier, C1 to C3: capacity
Sita, Cp1, Cp2: parasitic capacitance, φ1, φ2, φn:
Positive phase clock signal, φ1b, φ2b, φnb:
Clock signal, PMOS1 to PMOS3: P-type MOS transistor
Transistors, NMOS1 to NMOS3: N-type MOS transistor
Transistor, W, W_P, W_N: Gate width, L, L_P, L_N, L
_N1, L _N2： Gate length

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toru Sekiguchi 2-1-1 Fukuoka, Kamifukuoka-shi, Saitama FJ-term in NJ Semiconductor Ltd. (reference) 5J023 CA01 CB06 CB12 5J055 AX25 AX55 AX56 BX17 CX24 DX13 DX14 DX22 DX56 DX83 EY10 EY21 EY29 EZ00 EZ07 EZ12 EZ24 GX01 GX08 5J056 AA00 BB22 DD13 DD28 DD51 DD52 EE12 FF08 HH01 HH02

Claims (3)

[Claims] 1. An analog switch comprising: a capacitor; and a plurality of analog switches each including a P-type MOS transistor and an N-type MOS transistor for charging and discharging the capacitor. An inverter used in a switched capacitor circuit driven by application of a clock signal, wherein the gate width of a gate electrode superimposed on a P-type diffusion region and the gate width of a gate electrode superimposed on an N-type diffusion region are substantially equal to each other. The gate length or the sum of the gate lengths of one or more gate electrodes overlapping the diffusion region is greater than the gate length or the sum of the gate lengths of the one or more gate electrodes overlapping the P-type diffusion region; Wherein the drain-side area of the N-type diffusion region and the drain-side area of the N-type diffusion region substantially match. Inverter that. 2. A semiconductor device comprising: a capacitor; and a plurality of analog switches each including a P-type MOS transistor and an N-type MOS transistor for charging / discharging the capacitor. A switched capacitor circuit driven by applying a clock signal, wherein the inverter according to claim 1 is inserted by connecting an output of the inverter to each of two gates of the analog switch. 3. The inverter of claim 1 further connected to said inverter connected to one of two gates of said analog switch, said inverter forming a clock signal of opposite phase from said clock signal of positive phase. 3. The switched capacitor circuit according to claim 2, wherein: