JP2001077168A - Semiconductor substrate evaluation method, semiconductor substrate and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate evaluation method, a semiconductor substrate, and a semiconductor device capable of highly accurately evaluating the quality of a high-quality wafer used for a product requiring a high yield. A method for evaluating a semiconductor substrate according to the present invention includes:
From a plurality of cells each including a pn junction having an area small enough to detect a junction leakage current having an activation energy Ea of 0.1 eV or more and 0.4 eV or less, specifically a pn junction having an area of 5 mm ² or less. The junction leak current is evaluated by using the following TEG. The semiconductor substrate according to the present invention has a junction leak current evaluation TEG formed of a plurality of cells each including a pn junction having the above area. A semiconductor device according to the present invention includes a plurality of cells each including a pn junction having the above-mentioned area, and is used for evaluating a junction leak current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for evaluating a semiconductor substrate, a semiconductor substrate and a semiconductor device, and more particularly, to a method for evaluating a junction leak current of a semiconductor substrate and a semiconductor substrate and a semiconductor device used for the method.

[0002]

2. Description of the Related Art With the miniaturization and high performance of semiconductor devices such as memories and CCDs, high quality silicon wafers as materials are required in order to improve the product yield. In particular, the crystallinity of the surface layer of the wafer, which directly affects the product characteristics, is important. As measures for improving the crystallinity, 1) a "high-temperature annealed wafer" treated at a high temperature in an atmosphere containing an inert gas or hydrogen; "Improved CZ wafers" in which glow-in defects have been reduced by the improvement of GaN have been developed. In particular, for the former high-temperature annealed wafer, a high product yield has been achieved for MOS products such as memories, and other products have been developed.

[0003]

However, recently, it has been found that even with the use of the above-mentioned improved wafer, the yield may be reduced depending on the type of product, such as a CCD or CMOS sensor.

Therefore, in a lot with a high yield and a lot with a low yield of CMOS sensors, an oxide film breakdown voltage (TZDB) evaluation and a junction leak current evaluation were performed using remaining wafers which were not put into a product process.

FIG. 9 is a graph showing the results of conventional oxide film breakdown voltage evaluation of a high yield wafer and a low yield wafer of a CMOS sensor.

The oxide film breakdown voltage evaluation was performed under the conditions of an oxide film thickness of 20 nm and an electrode area of 10 mm ² . The results of the oxide film breakdown voltage evaluation are as follows: A mode in which the oxide film is broken at an electric field of less than 1 MV / cm, B mode in which the oxide film is broken at an electric field of 1 MV / cm to 5 MV / cm, and oxide film at an electric field of 8 MV / cm or more. It destroyed the C ^- mode, even oxide film electric field 8 MV / cm or more is classified into ^{C +} mode not destroyed. As shown in the graph of FIG. 9, the evaluation results of both the high-yield wafer and the low-yield wafer show that the C ⁺ mode is 100% as in the characteristic of the high-temperature annealed wafer, and no difference is observed.

FIG. 10 is an explanatory view schematically showing the results of a conventional junction leak current evaluation on a high yield wafer and a low yield wafer of a CMOS sensor.

[0008] The conventional evaluation of junction leakage current is 1 μm in depth.
After forming an n-type well with m and phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ³ near the wafer surface, a depth of 0.2 μm and a boron concentration of 1 × 10 ¹⁹ atoms are formed inside the n-type well.
/ Cm ³ p-type diffusion layer was formed at 112 points in the wafer surface, and junction leakage current was measured between the n-type well and the p-type diffusion layer.

FIG. 1 shows the results of the conventional junction leakage current evaluation.
As shown in FIG. 0, both the high-yield wafer and the low-yield wafer had a small leakage current, and no significant difference was found in the leakage current distribution and the like.

As described above, it has been found that the conventional semiconductor substrate evaluation method cannot evaluate the difference in the quality of the semiconductor substrate between a lot having a high product yield such as a CCD and a CMOS sensor and a lot having a low product yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to evaluate the quality of a high quality wafer used for a product requiring a high yield, such as a CCD or a CMOS sensor, with high accuracy. It is an object of the present invention to provide a method for evaluating a semiconductor substrate, and a semiconductor substrate and a semiconductor device capable of performing the above.

[0012]

According to the method of evaluating a semiconductor substrate of the present invention, the activation energy Ea is 0.1 eV.
A pn junction having an area small enough to detect a junction leakage current of 0.4 eV or less, specifically, an area of 5
It is characterized in that a junction leak current is evaluated using a TEG composed of a plurality of cells each including a pn junction of mm ² or less.

According to the semiconductor substrate of the present invention, a pn having a sufficiently small area for detecting a junction leak current having an activation energy Ea of 0.1 eV or more and 0.4 eV or less is provided.
TE for evaluating junction leakage current comprising a plurality of cells each including a pn junction having an area of 5 mm ² or less, specifically, a junction.
G is formed.

According to the semiconductor device of the present invention, a pn having a sufficiently small area for detecting a junction leak current having an activation energy Ea of 0.1 eV or more and 0.4 eV or less is provided.
It consists of a plurality of cells each including a pn junction having an area of 5 mm ² or less, and is used for evaluating junction leakage current.

With the above structure, the method for evaluating a semiconductor substrate and the semiconductor substrate and the semiconductor device according to the present invention comprise a CCD,
The quality of a high-quality wafer used for a product requiring a high yield, such as a CMOS sensor, can be evaluated with high accuracy.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION When evaluating the quality of a semiconductor wafer by evaluating a junction leakage current, a TEG (Te
st Element Group: a test element group), and the leakage current at the pn junction included in the TEG cell is measured. The measurement accuracy is determined by the area of the pn junction included in the TEG cell and the cell Depends on the number. In other words, if the area of the pn junction contained in the cell is large and the number of cells is small, if a certain defect exists, the defect becomes p-type.
Although the probability of being included in the n-junction increases, the current density of the leak current decreases due to the large area of the pn junction, and the detection sensitivity of the leak current decreases. On the other hand, if the area of the pn junction included in the cell is small and the number of cells is large, the probability that a defect is included in the pn junction is reduced. The current density increases, and the leak current detection sensitivity increases.

Conventionally, T used for some evaluation methods
Since the EG was shared, the area of the pn junction included in the TEG cell was relatively large, and the number of cells was small. As a result, it is assumed that the leak current detection sensitivity in the evaluation of the junction leak current was low.

Therefore, in the evaluation method of the semiconductor device according to the present invention, when evaluating the junction leakage current, a TEG dedicated to the evaluation of the junction leakage current is formed on the wafer, and the evaluation of the junction leakage current is performed. That is, in the semiconductor substrate according to the present invention, a semiconductor device according to the present invention is formed in which the area of the pn junction included in the cell is sufficiently small and the number of cells is sufficiently large, and the TEG is joined. Used for leak current evaluation.

Hereinafter, an embodiment of a semiconductor device evaluation method, a semiconductor substrate, and a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart showing a procedure for preparing and evaluating a wafer for verifying a semiconductor device evaluation method according to the present invention.

In order to perform each evaluation, first, a plurality of wafers are respectively cut out from a plurality of ingots a, b, c, d, and e each having a diameter of 200 mm, a p-type, and a resistivity of 5 Ωcm manufactured by the CZ method. , Those wafers a, b,
c, d, and e were set (step S1). Then, the wafers a, b, c, d, and e were subjected to high-temperature annealing at 1200 ° C. for one hour in a hydrogen atmosphere (step S2). The high-temperature annealing is performed in an inert gas atmosphere or a hydrogen-containing atmosphere at a temperature of 1100 ° C. or higher. After high-temperature annealing, wafers a, b, c, d, and e
Were divided into first, second, and third groups, respectively, and the following evaluations were performed for wafers a, b, c, d, and e for each group.

The first group of wafers a, b, c,
For d and e, oxide film breakdown voltage evaluation was performed. To evaluate the oxide film breakdown voltage, a 20 nm thick oxide film is formed on each wafer by heat treatment at a temperature of 900 ° C., and a 4000 Å thick polysilicon layer serving as an electrode is laminated on the oxide film and patterned. To form a TEG for oxide film breakdown voltage evaluation (step S3). Then, the oxide film breakdown voltage was evaluated using the TEG (step S4).

FIG. 2 is a graph showing the results of oxide film breakdown voltage evaluation for wafers a, b, c, d, and e.

As shown in the graph of FIG. 2, the mode in part of the wafer a C ^- section but is seen, rather than the ratio as a particular problem, characterized as high-temperature annealed wafer with full wafer, C ⁺ mode Was 95% or more, good results were obtained.

The second group of wafers a, b, c,
For d and e, the junction leak current was evaluated. In order to evaluate the junction leakage current, first, a semiconductor substrate according to the present invention on which a TEG for evaluating a junction leakage current was formed.

FIG. 3 shows a wafer used in the method for evaluating a semiconductor device according to the present invention, that is, a cell of a junction leak current evaluation TEG which is a semiconductor device according to the present invention formed on a semiconductor substrate according to the present invention. It is sectional drawing. In the TEG cell for evaluating junction leak current, which is the semiconductor device according to the present invention shown in FIG. 3, phosphorus (P) having an impurity concentration of 1 × 10 ¹⁷ atoms / cm ³ is implanted into a p-type wafer 4 having a resistivity of 5 Ωcm. An n-type well 3 having a depth of about 1 μm;
Impurity concentration 1 × 10 ¹⁹ atoms in n-type well 3
/ Cm ³ of boron (B) implanted at a depth of about 0.2 μm
The p-type diffusion layer 2 has an area of 1 × 1 mm ² and an aluminum wiring 1 formed by being connected to the p-type wafer 4, the n-type well 3, and the p-type diffusion layer 2.

The n-type well 3 has a phosphorus concentration of 1 × 10 ¹⁷ at.
oms / cm ^{3 to} 1 × 10 ¹⁸ atoms / cm ³ ,
The depth is 2 μm or less, and the p-type diffusion layer 2 has a boron concentration of 1 × 10
¹⁸ atoms / cm ^{3 to} 1 × 10 ²⁰ atoms / cm
cm ³ and a depth of 0.5 μm or less may be used. In addition, the well 3 has a boron concentration of 1 × 10 ¹⁷ atoms / cm ^{3 to} 1 × 10 ¹⁸ atoms / cm ³ and a depth of 2 μm or less.
And the diffusion layer 2 has a phosphorus concentration of 1 × 10 ¹⁸ atoms /
cm ^{3 to} 1 × 10 ²⁰ atoms / cm ³ , depth 0.
It may be an n type of 5 μm or less.

The TEG cell for evaluating junction leak current, which is the semiconductor device according to the present invention, is manufactured as follows. First, an impurity concentration of 1 × 10 ¹⁷ a
The n-type well 3 having a depth of about 1 μm is formed by implanting phosphorus (P) of toms / cm ³ . Next, boron (B) having an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ is implanted into the n-type well 3 to have a depth of 0.2 μm or less and an area of 1 × 1 mm.
² p-type diffusion layers 2 are formed. Finally, aluminum is laminated, and a p-type wafer 4, an n-type well 3, and a p-type diffusion layer 2 are formed.
When the aluminum wiring 1 is patterned so as to form the portions connected to the TEG, the junction leak current evaluation TEG cell shown in FIG. 3 is obtained. In the method for evaluating a semiconductor substrate according to the present invention, a TEG for evaluating a junction leak current including about 9000 cells as described above, each including a pn junction, was manufactured (Step S5). The device isolation was performed using an oxide film formed from TEOS (Tetra Ethyl Ortho Silicate).

The evaluation of the junction leak current by the method for evaluating a semiconductor substrate according to the present invention uses the semiconductor substrate according to the present invention on which the TEG for evaluating the junction leak current, which is the semiconductor device according to the present invention, is used. 4V, temperature 25
The test was performed under the conditions of a temperature of 0 ° C. and a bias voltage of 0.2 V between the p-type wafer 4 and the n-type well 3 for preventing a diffusion current (step S6).

FIG. 4 is a junction leakage current distribution diagram showing a distribution of junction leakage current detected in the wafer surface by the junction leakage current evaluation by the semiconductor substrate evaluation method according to the present invention. Here, in particular, the wafer d (FIG. 4A),
Although only the wafer e (FIG. 4B) is shown, the other wafers a, b, and c were similarly evaluated. The white spots appearing in the junction leak current distribution diagram of FIG. 4 are the locations where the leak current is detected, and in the wafer e, many are scattered near the center.

FIG. 5 is a graph showing a histogram analysis result of junction leak current data obtained by evaluating the junction leak current of the wafers a, b, c, d, and e by the semiconductor substrate evaluation method according to the present invention. is there.

Comparing the histograms of the junction leak current data of the wafers a, b, c, d, and e, the positions of the main distribution (the highest frequency) are almost the same. A difference is seen in the distribution on the side where the leak current is large. That is, even if the wafer is a high-temperature annealed wafer, it indicates that a considerable number of crystal defects exist near the surface layer depending on the wafer. This cannot be detected and identified by the conventional method for evaluating a semiconductor substrate. In the method for evaluating a semiconductor substrate according to the present invention, the pn junction area is significantly smaller than the conventional one, and the measurement is performed. For the first time, the number of points can be detected and identified by greatly increasing the score.

The third group of wafers a, b, c,
With respect to d and e, the yield of white scratches was evaluated. In order to evaluate the white defect yield, a 1/4 inch, 330,000 pixel product was first manufactured as a white defect yield evaluation CMOS sensor (step S7). Their CMOS
The sensor was used to evaluate the white spot yield, that is, the output yield at dark.

FIG. 6 is a graph showing the results of evaluation of the yield of white defects on wafers a, b, c, d and e.

Compared with the above-mentioned junction leak current evaluation result, a wafer having a large junction leak current, specifically, a junction leak current value of 10 ⁻¹⁰ A to 10 ⁻⁸ A, and therefore a logarithmic value (log I) It can be seen that, as shown in the graph of FIG. 6, the yield of white scratches decreases as the number of junctions (wafers c and e) increases in which -10 to -8 are distributed.

Therefore, in order to investigate the cause of the occurrence of the junction leakage current, the activation energy Ea was obtained from the temperature characteristics in each distribution of the junction leakage current.

FIG. 7 is a graph showing the activation energy Ea in each distribution of the junction leak current.

The activation energy Ea corresponding to the junction leakage current in the main distribution of the histogram is 0.5 eV or more and 0.6 eV or less, which is almost equal to the theoretical value of 0.55 eV. The distribution in which there is a difference in the leakage current, that is, the logarithmic value (Lo
The activation energy Ea in the distribution of gI) of -10 to -8 is 0.1 eV to 0.4 eV, which is lower than the above theoretical value.

Therefore, the relationship between the ratio of the pn junction having the activation energy Ea of 0.2 eV or more and 0.4 eV or less and the white flaw yield was further examined.

FIG. 8 shows that the activation energy Ea is 0.2 eV.
4 is a graph showing the relationship between the ratio of pn junctions of 0.4 eV or less and the white flaw yield.

As can be seen from the graph of FIG. 8, the activation energy Ea is 0.1
It is understood that the ratio of the pn junction of eV or more and 0.4 eV or less needs to be suppressed to 3% or less, preferably 1% or less.

From the above verification results, the conditions for the method of evaluating a semiconductor substrate according to the present invention, which can detect defects that affect the product yield, such as CCD and CMOS sensors,
The conditions for evaluating the junction leakage current are as follows. In the graph of FIG. 7, the leakage current value at which the activation energy Ea becomes 0.1 eV or more and 0.4 eV or less is:
The logarithmic value (Log I) is a value around −11, and the difference from the main distribution (−12 to −11) is 1/10 or less. Considering that the pn junction area in this embodiment is 1 mm ² , the detection sensitivity as a whole becomes 1/10 in the case of a pn junction having an area of 10 mm ² , so that some junction leakage currents cannot be detected. Will be.

However, if the detection sensitivity is about 1/5,
Considering the accuracy of current measuring equipment, the activation energy E
Junction leak current where a is 0.1 eV or more and 0.4 eV or less can also be detected and identified. Therefore, if the pn junction area of the cell of the junction leak current evaluation TEG is 5 mm ² or less, it is possible to detect a defect such as a CCD or a CMOS sensor that affects the product yield.

The number of pn junctions measured in the evaluation of junction leakage current, which is the method for evaluating a semiconductor substrate according to the present invention, is such that the activation energy Ea is 0.1 eV or more and 0.4 eV.
It is sufficient that the number of pn junctions equal to or less than V is sufficient to determine that the ratio is 3% or less, and it is not limited to a specific numerical range. However, the greater the number of measurements, the higher the reliability of the evaluation, and the correlation with the product yield can be clarified.

[0045]

According to the semiconductor substrate evaluation method of the present invention, the activation energy Ea is 0.1 eV or more and 0.4 eV.
A pn junction having an area small enough to detect a junction leak current of, for example, a p-n junction having an area of 5 mm ² or less.
Since the junction leak current was evaluated using a TEG composed of a plurality of cells each including an n-junction, CC
The quality of a high-quality wafer used for a product requiring a high yield, such as a D or CMOS sensor, can be evaluated with high accuracy.

According to the semiconductor substrate of the present invention, a pn having a sufficiently small area for detecting a junction leak current having an activation energy Ea of 0.1 eV or more and 0.4 eV or less is used.
TE for evaluating junction leakage current comprising a plurality of cells each including a pn junction having an area of 5 mm ² or less, specifically, a junction.
Since G is formed, the quality of a high-quality wafer used for a product requiring a high yield, such as a CCD or a CMOS sensor, can be evaluated with high accuracy.

According to the semiconductor device of the present invention, the pn of a sufficiently small area for detecting a junction leak current having an activation energy Ea of 0.1 eV or more and 0.4 eV or less is detected.
It is composed of a plurality of cells each including a pn junction having an area of 5 mm ² or less, and is used for evaluating junction leak current. Therefore, it is used for products requiring a high yield, such as CCDs and CMOS sensors. The quality of a high quality wafer can be evaluated with high accuracy.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of wafer creation and evaluation for verifying a semiconductor device evaluation method according to the present invention.

FIG. 2 is a graph showing the results of oxide film breakdown voltage evaluation.

FIG. 3 is a sectional structural view of a cell of a TEG for evaluating a junction leak current, which is a semiconductor device according to the present invention formed on a semiconductor substrate according to the present invention.

FIG. 4 is a junction leak current distribution diagram showing a distribution in a wafer surface of a junction leak current detected by a junction leak current evaluation by a semiconductor substrate evaluation method according to the present invention.

FIG. 5 is a graph showing a histogram analysis result of junction leak current data obtained by a junction leak current evaluation by a semiconductor substrate evaluation method according to the present invention.

FIG. 6 is a graph showing the results of white scratch yield evaluation.

FIG. 7 is a graph showing activation energy Ea in each distribution of a junction leak current.

FIG. 8 is a graph showing the relationship between the percentage of pn junctions having an activation energy Ea of 0.2 or more and 0.4 eV or less and the yield of white spots.

FIG. 9 is a graph showing the results of a conventional oxide film breakdown voltage evaluation of a high yield wafer and a low yield wafer of a CMOS sensor.

FIG. 10 is an explanatory view schematically showing a result of a conventional junction leak current evaluation for a high yield wafer and a low yield wafer of a CMOS sensor.

[Explanation of symbols]

 Reference Signs List 1 aluminum wiring 2 p-type diffusion layer 3 n-type well 4 p-type wafer

Claims (8)

[Claims] 1. The method according to claim 1, wherein the activation energy Ea is 0.1 eV or more.
A semiconductor substrate characterized in that a junction leak current is evaluated using a TEG (Test Element Group) including a plurality of cells each including a pn junction having a sufficiently small area for detecting a junction leak current of 4 eV or less. Evaluation method. 2. A method for evaluating a semiconductor substrate, comprising: performing a junction leakage current evaluation using a TEG including a plurality of cells each including a pn junction having an area of 5 mm ² or less. 3. A semiconductor substrate of a first conductivity type having a resistivity of 5 Ωcm.
Plate and an impurity concentration of 1 formed in the surface layer of the semiconductor substrate.
× 10¹⁷atoms / cm³~ 1 × 10¹⁸ato
ms / cm³, The second conductivity type having a depth of 2 μm or less or the first conductivity type
Conductivity type wells and impurities formed inside the wells.
Material concentration 1 × 10¹⁸atoms / cm³~ 1 × 10
²⁰atoms / cm³, Depth 0.5μm or less, area
5mm²The following diffusion layer of the first conductivity type or the second conductivity type
Using a TEG consisting of multiple cells each containing
Semiconductor substrate characterized by evaluating junction leakage current
Evaluation method. 4. The method according to claim 1, wherein the activation energy Ea is 0.1 eV or more.
A semiconductor substrate, comprising: a junction leak current evaluation TEG including a plurality of cells each including a pn junction having a sufficiently small area for detecting a junction leak current of 4 eV or less. 5. A semiconductor substrate having a junction leak current evaluation TEG formed of a plurality of cells each including a pn junction having an area of 5 mm ² or less. 6. A semiconductor substrate of a first conductivity type having a resistivity of 5 Ωcm.
Plate and an impurity concentration of 1 formed in the surface layer of the semiconductor substrate.
× 10¹⁷atoms / cm³~ 1 × 10¹⁸ato
ms / cm³, The second conductivity type having a depth of 2 μm or less or the first conductivity type
Conductivity type wells and impurities formed inside the wells.
Material concentration 1 × 10¹⁸atoms / cm³~ 1 × 10
²⁰atoms / cm³, Depth 0.5μm or less, area
5mm²The following diffusion layer of the first conductivity type or the second conductivity type
Of junction leakage current consisting of multiple cells each containing
Semiconductor substrate characterized in that a valence TEG is formed.
Board. 7. A semiconductor device comprising a plurality of cells each including a pn junction having an area of 5 mm ² or less and used for evaluating a junction leakage current. 8. A semiconductor substrate of a first conductivity type having a resistivity of 5 Ωcm.
Plate and an impurity concentration of 1 formed in the surface layer of the semiconductor substrate.
× 10¹⁷atoms / cm³~ 1 × 10¹⁸ato
ms / cm³, The second conductivity type having a depth of 2 μm or less or the first conductivity type
Conductivity type wells and impurities formed inside the wells.
Material concentration 1 × 10¹⁸atoms / cm³~ 1 × 10
²⁰atoms / cm³, Depth 0.5μm or less, area
5mm²The following diffusion layer of the first conductivity type or the second conductivity type
And the junction leakage current
A semiconductor device used for evaluation.