JP2001069127A - High speed data receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly receive data without controlling the delay quantity of a circuit or wiring and to correctly receive the data even when the duty of the reception data is deteriorated. SOLUTION: In a five-point sampling part 230, the reception data are fetched by five clocks of different phases and in a clock selection determining part 240, the phases of reception data fetched by the five-point sampling part 230 are compared and it is detected whether the data fetched by a clock having the central phase among relevant five pieces of data are included within a duty degradation range or not. On the basis of the compared result and the detected result, in a clock selecting part 220, the clock to be inputted to the five-point sampling part 230 is selected among plural clocks generated by a multiphase clock generating part 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed data receiving circuit, and more particularly to a high-speed data receiving circuit which receives received data accurately even when the phase of the received clock and the received data fluctuates or the duty of the received data deteriorates. The present invention relates to a high-speed data receiving circuit capable of performing such operations.

[0002]

2. Description of the Related Art Conventionally, in a data receiving circuit of this type, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 10-247903, the phase of a data is compared with that of a multi-phase clock. The clock phase for taking in data is controlled based on the comparison result.

FIG. 20 is a block diagram showing one configuration example of a conventional data receiving circuit, and shows an example in which a clock is used in four phases.

In this conventional example, as shown in FIG. 20, a system clock is input, and delay circuits 101a to 101c for multiplying the system clock by delaying the system clock by a predetermined delay amount; The clock, the clock pulse output from the delay circuits 101a to 101c and the received data are input, and the change point of the received data, the system clock and the delay circuits 101a to 101c are input.
Based on the rising edge of the clock pulse output from 1c, a phase comparison pulse generation circuit 102 that generates and outputs a reception data pulse and a clock pulse having a certain width, and a phase selection signal that is input, A phase selection circuit 103 for selecting and outputting one of the clock pulses generated by the phase comparison pulse generation circuit 102, and a system clock and delay circuit 101a to 101c based on the input phase selection signal
Selecting circuit 104 for selecting and outputting one of the clock pulses output from the phase shifter, a phase of the received data pulse output from the phase comparison pulse generating circuit 102, and a selected clock output from the phase selecting circuit 103. A phase comparison circuit 105 for comparing the phase of the pulse
/ DOWN counter, and based on the comparison result in the phase comparison circuit 105, the phase selection circuits 103 and 10
Phase determination circuit 1 for generating a phase selection signal input to
06, and a latch circuit 107 that takes in received data with the clock output from the phase selection circuit 104, and the clock selected by the phase selection circuit 104 is output as an output clock.

[0005] The operation of the data receiving circuit configured as described above will be described below.

First, in the delay circuits 101a to 101c, the system clock is delayed based on the delay time set for each, whereby a multi-phase clock pulse is output.

Next, the system clock and delay circuit 101
The clocks output from a to 101c and the received data are input to the phase comparison pulse generation circuit 102, and in the phase comparison pulse generation circuit 102, the change points of the received data and the system clock and the output from the delay circuits 101a to 101c are output. Based on the rising point of the clock pulse, a received data pulse and a clock pulse having a certain width are generated and output.

Next, the phase selection signal generated by the phase determination circuit 106 is input to the phase selection circuit 103, and the clock pulse generated by the phase comparison pulse generation circuit 102 is generated based on the phase selection signal. Is selected and output.

Next, the phase comparison circuit 105 compares the phase of the received data pulse output from the phase comparison pulse generation circuit 102 with the phase of the selected clock pulse output from the phase selection circuit 103.

The comparison result of the phase comparison circuit 105 is input to a phase judgment circuit 106, and the comparison result is output to the phase comparison pulse generation circuit 102.
Data pulse and phase selection circuit 103 output from
If there is a possibility that the setup time may not be satisfied with the selected clock pulse output from the phase selection circuit 103, the phase selection circuit 103 may be used to increase the setup time.
A phase selection signal is generated such that the phase of the clock pulse selected in the step is delayed, and between the received data pulse output from the phase comparison pulse generation circuit 102 and the selected clock pulse output from the phase selection circuit 103 If there is a possibility that the hold time may not be satisfied, the phase selection circuit 1 may be used to increase the hold time.
03, a phase selection signal is generated such that the phase of the clock pulse selected advances, and the received data pulse output from the phase comparison pulse generation circuit 102 and the selected clock pulse output from the phase selection circuit 103 are generated. If both the setup time and the hold time are satisfied, a phase selection signal is generated such that the phase of the clock pulse selected in the phase selection circuit 103 is maintained, and the phase selection signal is generated. Output to the selection circuits 103 and 104.

In the phase selection circuit 104, one of the system clock and the clock pulse output from the delay circuits 101a to 101c is selected based on the phase selection signal output from the phase determination circuit 106, and the output clock is selected. Is output as

The clock output from the phase selection circuit 104 as an output clock is also input to the latch circuit 107. The latch circuit 107 receives the received data with the clock output from the phase selection circuit 104 and outputs it as output data. You.

[0013]

However, in the conventional data receiving circuit as described above, the received data actually latched and output via the latch circuit 107 is
The path is different from the received data input to the phase comparison circuit 105 via the phase comparison pulse generation circuit 102 for adjusting the phase of the clock, and is actually output via the phase selection circuit 104. The path of the clock which is input to the phase comparison circuit 105 via the phase comparison pulse generation circuit 102 and the phase selection circuit 103 for adjusting the phase of the clock is different from each other. Depending on the combination of the delay amounts in the above, even if the comparison result in the phase comparison circuit 105 satisfies both the setup time and the hold time, the clock selected by the phase selection circuit 104 at that time is Latch circuit 10
7, the setup time and the hold time are not always satisfied when receiving the received data, and there is a possibility that correct data cannot be captured.

For example, the amount of delay in the phase selection circuit 104 is half of one cycle of the clock, and
Consider a case where the delay amount other than the above is 0.

In this case, even if the result of the phase comparison in the phase comparison circuit 105 is such that the change point of the received data and the phase of the rising edge of the clock are shifted by one half of one cycle of the clock, the input to the phase selection circuit 104 is not performed. The delayed clock is delayed by half of one cycle of the clock, whereby the change point of the data input to the latch circuit 107 coincides with the phase of the rising edge of the clock, and the setup time and the hold time are not satisfied. Cannot be imported.

To solve such a problem, a phase comparison pulse generation circuit 102, a phase selection circuit 103,
From the branch points 108 and 109 such as 104
In addition, it is necessary to adjust the amount of delay between the circuit and the wiring existing up to the phase comparison circuit 105.

However, when the frequency of the received data is low, such adjustment is easy. However, as the frequency of the received data increases, the amount of delay must be adjusted within a minute range. There is a problem that implementation is difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and can correctly receive received data without adjusting a delay amount in a circuit or a wiring. It is an object of the present invention to provide a high-speed data receiving circuit capable of correctly receiving received data even when the duty of the received data is deteriorated.

[0019]

In order to achieve the above object, the present invention provides a high-speed data receiving circuit for receiving received data with a clock that satisfies a predetermined setup time and hold time, wherein the received data is determined in advance. Sampling means for capturing with three clocks having the obtained phase difference, and selecting means for comparing the three data captured by the sampling means with each other and outputting the three clocks based on the comparison result. And a clock having a center phase among the three clocks input to the sampling means is output as an output clock, and data captured by the output clock is output as output data.

The output of the three clocks by the selection means and the reception of the reception data by the sampling means are repeatedly performed by a loop.

In addition, as a result of comparing the three data with each other, if the data captured by the clock having the most advanced phase is different from the data captured by the clock having the central phase, When the phases of the three clocks to be output are respectively delayed, and the data captured by the clock having the most delayed phase is different from the data captured by the clock having the central phase,
It is characterized in that the phases of the three output clocks are advanced respectively.

[0022] Further, there is provided a multi-phase clock generation means for multiplying the received clock, wherein the selection means selects one of the plurality of clocks generated by the multi-phase clock generation means based on the comparison result. It is characterized in that three clocks are selected and output.

[0023] Also, there is provided a multi-phase clock generating means for multiplying the received clock, and the selecting means selects one of the plurality of clocks generated by the multi-phase clock generating means based on the comparison result. One clock is selected, and the selected one clock is output as three clocks with a predetermined phase difference.

The selecting means compares the three data fetched by the sampling means with each other, and fetches the data fetched by the clock having the most advanced phase and the clock having the central phase. If the data is different, the selection signals for respectively delaying the phases of the three clocks to be selected are output, and the data captured by the clock with the most delayed phase and the clock captured with the clock having the central phase are captured. If the data is different,
A clock selection determining unit that outputs a selection signal for advancing each of the three clocks to be selected, and a multi-phase clock generation unit that generates the selection signal based on the selection signal output from the clock selection determination unit. A clock selection unit that selects and outputs three clocks from among a plurality of clocks.

The selecting means compares the three data taken in by the sampling means with each other, and takes in the data taken in by the clock having the most advanced phase and the data having the center phase. If the data is different, the selection signals for respectively delaying the phases of the three clocks to be selected are output, and the data captured by the clock with the most delayed phase and the clock captured with the clock having the central phase are captured. If the data is different,
A clock selection determining unit that outputs a selection signal for advancing each of the three clocks to be selected, and a multi-phase clock generation unit that generates the selection signal based on the selection signal output from the clock selection determination unit. A clock selecting unit that selects one clock from among a plurality of clocks, provides the selected one clock with a predetermined phase difference, and outputs the selected clock as three clocks.

[0026] The clock selection unit may further include a selector for selecting one of a plurality of clocks generated by the multi-phase clock generation unit based on a selection signal output from the clock selection determination unit. And delay means for delaying the clock selected by the selector by a different delay amount and outputting the two clocks. The clock selected by the selector and the two clocks output from the delay means are provided. Clocks are output as the three clocks.

The clock selection determining section compares the three data fetched by the sampling means with each other, and uses the data fetched by the clock having the most advanced phase and the clock having the central phase. If the captured data is different, an UP signal is output. If the data captured by the clock with the most delayed phase and the data captured by the clock having the central phase are different, a DOWN signal is output. And a counter that increments a count value when an UP signal is output from the phase comparison unit, decrements the count value when a DOWN signal is output, and outputs the count value as the selection signal. And the clock selecting unit, when the count value in the counter unit is incremented, It delayed three clock phases of-option, respectively, when the count value in the counter is decremented, characterized in that advancing the three clock phases of selecting respectively.

Further, the clock selection determining section compares the three data fetched by the sampling means with each other, and uses the data fetched by the clock having the most advanced phase and the clock having the central phase. If the captured data is different, an UP signal is output. If the data captured by the clock with the most delayed phase and the data captured by the clock having the central phase are different, a DOWN signal is output. And a counter that increments a count value when an UP signal is output from the phase comparison unit, decrements the count value when a DOWN signal is output, and outputs the count value as the selection signal. And the clock selecting unit, when the count value in the counter unit is incremented, Delaying one clock phase to-option, if the count value in the counter is decremented, characterized in that advancing the one clock phase to be selected.

When the UP signal or the DOWN signal is output, the phase comparison unit outputs the UP signal or the DOWN signal for a predetermined period after the output of the UP signal or the DOWN signal.
No signal or the DOWN signal is output.

A high-speed data receiving circuit for receiving received data with a clock that satisfies a predetermined setup time and a hold time, and a sampling means for capturing the received data with five clocks having a predetermined phase difference; , 5 captured by the sampling means.
The two data are compared with each other, and it is detected whether or not the data captured by the clock having the central phase out of the five data is included in the duty deterioration range, and based on the comparison result and the detection result, Selecting means for outputting the five clocks, a clock having a central phase among the five clocks input to the sampling means is output as an output clock,
Data captured by the output clock is output as output data.

The output of the five clocks by the selection means and the reception of the received data by the sampling means are repeatedly performed by a loop.

In addition, as a result of comparing the five data with each other, the selecting means finds that the data fetched by the clock having the central phase is different from the data fetched by the clock having a phase advanced from that. If output 5
If the data captured by the clock having the center phase is different from the data captured by the clock delayed in phase, the phases of the five clocks to be output are respectively delayed. It is characterized by proceeding.

When the selecting means detects that the data fetched by the clock having the center phase is included in the duty deterioration range, the selection means causes the data to fall out of the duty deterioration range. It is characterized by outputting a clock.

[0034] Further, when detecting that the data taken in by the clock having the center phase is included in the duty deterioration range, the selecting means changes the phases of the five clocks to be output. Thus, a clock is output such that the data comes out of the duty deterioration range.

The multi-phase clock generating means for multiplying the received clock is provided. The selecting means selects one of the plurality of clocks generated by the multi-phase clock generating means based on the comparison result. It is characterized in that five clocks are selected and output.

The multi-phase clock generator includes a multi-phase clock generator for multiplying the received clock. The selector selects one of the plurality of clocks generated by the multi-phase clock generator based on the comparison result. One clock is selected, and the selected one clock is output as five clocks with a predetermined phase difference.

The selecting means compares the five data fetched by the sampling means with each other, and selects the data fetched by the clock having the central phase and the clock fetched with a phase advanced from the clock. If the captured data is different, a selection signal for delaying the phase of each of the five clocks to be selected is output, and the data captured by the clock having the central phase and the clock delayed in phase therefrom are output. If the received data is different, a selection signal is output to advance the phase of each of the five clocks to be selected, and the data captured by the clock having the center phase of the five data is degraded in duty. It is detected whether the data is within the range, and the data captured by the clock having the central phase A clock selection determining unit that outputs a selection signal for selecting a clock that causes the data to fall out of the duty deterioration range when detecting that the data falls within the duty deterioration range; A clock selection unit for selecting and outputting five clocks from among the plurality of clocks generated by the multi-phase clock generation means based on the selected selection signal.

The selecting means compares the five data fetched by the sampling means with each other, and uses the data fetched by the clock having the central phase and the clock advanced in phase with the data fetched. If the captured data is different, a selection signal for delaying the phase of each of the five clocks to be selected is output, and the data captured by the clock having the central phase and the clock delayed in phase therefrom are output. If the received data is different, a selection signal is output to advance the phase of each of the five clocks to be selected, and the data captured by the clock having the center phase of the five data is degraded in duty. It is detected whether the data is within the range, and the data captured by the clock having the central phase A clock selection determining unit that outputs a selection signal for selecting a clock that causes the data to fall out of the duty deterioration range when detecting that the data falls within the duty deterioration range; One of a plurality of clocks generated by the multi-phase clock generation means is selected based on the selected selection signal, and the selected one clock is provided with a predetermined phase difference to be five clocks. And a clock selection unit for outputting.

Further, the clock selection deciding section selects one of the five data fetched by the sampling means.
Comparing data captured with a clock having a central phase, data captured with a clock advanced in phase from the central phase, and data captured with a clock delayed in phase from the central phase If the data captured by the clock having the central phase is different from the data captured by the clock having the advanced phase, an UP signal is output, and the data captured by the clock having the central phase is captured. If the data obtained by the clock with the delayed phase is different from the data captured by the clock with the delayed phase, a phase comparator for outputting a DOWN signal, and a clock having a central phase among the five data captured by the sampling means. Data fetched at and lags behind the center phase by the data fetched by the clock that is ahead of the center phase by the clock The data captured by the lock is compared with each other, and it is detected whether the data captured by the clock having the central phase is included in the duty deterioration range, and the clock having the central phase is detected by the clock having the central phase. A duty deterioration detector that outputs a DUP signal or a DDOWN signal when detecting that the captured data is included in the duty deterioration range;
When the UP signal is output from the phase comparison unit, the count value is incremented. When the DOWN signal is output, the count value is decremented. When the DUP signal is output from the duty deterioration detection unit, the center value is decremented. The count value is incremented so that the data fetched by the clock having the phase falls out of the duty deterioration range, and when the DDOWN signal is output, the data fetched by the clock having the center phase has the duty deterioration. A counter section for decrementing the count value so as to fall out of the range, and outputting the count value as the selection signal, wherein the clock selection section selects when the count value in the counter section is incremented. Delay the phase of each of the five clocks, When the count value in the counter portion is decremented, characterized in that advancing the five clock phase to be selected.

In addition, the clock selection determining unit is configured to select one of the five data fetched by the sampling means.
Comparing data captured with a clock having a central phase, data captured with a clock advanced in phase from the central phase, and data captured with a clock delayed in phase from the central phase If the data captured by the clock having the central phase is different from the data captured by the clock having the advanced phase, an UP signal is output, and the data captured by the clock having the central phase is captured. If the data obtained by the clock with the delayed phase is different from the data captured by the clock with the delayed phase, a phase comparator for outputting a DOWN signal, and a clock having a central phase among the five data captured by the sampling means. Data fetched at and lags behind the center phase by the data fetched by the clock that is ahead of the center phase by the clock The data captured by the lock is compared with each other, and it is detected whether the data captured by the clock having the central phase is included in the duty deterioration range, and the clock having the central phase is detected by the clock having the central phase. A duty deterioration detector that outputs a DUP signal or a DDOWN signal when detecting that the captured data is included in the duty deterioration range;
When the UP signal is output from the phase comparison unit, the count value is incremented. When the DOWN signal is output, the count value is decremented. When the DUP signal is output from the duty deterioration detection unit, the center value is decremented. The count value is incremented so that the data fetched by the clock having the phase falls out of the duty deterioration range, and when the DDOWN signal is output, the data fetched by the clock having the center phase has the duty deterioration. A counter section for decrementing the count value so as to fall out of the range, and outputting the count value as the selection signal, wherein the clock selection section selects when the count value in the counter section is incremented. Delay the phase of one clock, and When the count value in the section is decremented, characterized in that advancing the one clock phase to be selected.

In addition, the clock selection determining unit may be configured to output the UP signal or the DOWN signal from the phase comparing unit, or to output the DUP signal or the DDOWN signal from the duty deterioration detecting unit. For a predetermined period after the output of the UP signal, the DOWN signal, the DUP signal, or the DDOWN signal, the UP signal, the DOWN signal, the DUP signal, or the DDOWN signal is not output from the phase comparison unit or the duty deterioration detection unit. It is characterized by having an output regulating unit.

(Operation) In the present invention configured as described above, the received data is fetched by the sampling means with three clocks having a predetermined phase difference, and the selected data is fetched by the sampling means. The three data are compared with each other, and if the data captured by the clock having the most advanced phase is different from the data captured by the clock having the center phase, the three clocks currently selected are compared with each other. Phase delayed 3
If one clock is selected and the data captured by the clock with the latest phase is different from the data captured by the clock having the central phase, the phase of the three clocks selected at present is different. Are selected, the received data is captured by the selected three clocks in the sampling means, a clock having a central phase is output as an output clock, and the data captured by the output clock is output. Is output as output data.

As described above, since the phase of the clock is adjusted based on the data taken in by the clock actually output as the output clock, it is not necessary to adjust the amount of delay in the circuit or wiring.

The selection of the three clocks by the selection means and the reception of the reception data by the sampling means are repeatedly performed by a loop, so that it is possible to always respond to the phase fluctuation of the reception clock and the reception data.

In the case where the selecting means selects only one clock and outputs three clocks of the selected clock and two clocks obtained by delaying the selected clock by different delay amounts, If the data captured by the clock with the most advanced phase and the data captured by the clock with the central phase are different,
If a clock delayed in phase with respect to the currently selected clock is selected, and the data captured by the clock with the latest phase is different from the data captured by the clock with the center phase, A clock whose phase is ahead of the currently selected clock is selected,
In the sampling means, the received data is fetched by three clocks: a clock selected by the selection means and two clocks obtained by delaying the selected clock by different delay amounts, and a clock having a central phase is obtained. The data is output as an output clock, and data captured by the output clock is output as output data.

Further, the received data is captured by five clocks having a predetermined phase difference in the sampling means, and the five data captured by the sampling means are compared with each other by the selection means, and the central phase is changed. If the data captured by the clock having the clock and the data captured by the clock with a phase earlier than that are different, five clocks whose phases are delayed from the currently selected five clocks are selected, If the data fetched by the clock having the center phase is different from the data fetched by the clock lagging behind, the five clocks whose phases are advanced with respect to the currently selected five clocks Is selected, and the data captured by the clock having the center phase is included in the duty deterioration range. If it is detected that the data is out of the duty deterioration range, five clocks are selected, and the sampling means captures the received data with the selected five clocks, and adjusts the central phase. The output clock is output as an output clock, and data captured by the output clock is output as output data.

As described above, the phase of the clock is adjusted based on the data taken in by the clock actually output as the output clock, and the clock is selected so that the received data comes out of the duty deterioration range. Therefore, it is not necessary to adjust the amount of delay in the circuit or wiring, and the received data can be accurately received even when the reception duty is deteriorated.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a high-speed data receiving circuit according to a first embodiment of the present invention.

In this embodiment, as shown in FIG. 1, a multi-phase clock generator 10 for delaying a reception clock stepwise by 1 / N (N ≧ 4) of one cycle thereof, and a clock selection signal input thereto , A clock selection unit 20 that selects and outputs three clocks having a predetermined phase difference among the clocks that have been multi-phased by the multi-phase clock generation unit 10, and an output from the clock selection unit 20. The three clocks input are input, a three-point sampling unit 30 including a flip-flop that captures received data at the rising timing of each of the three clocks, and the data captured by the three-point sampling unit 30 are input. The three input data are compared, and a clock selection signal to be input to the clock selection unit 20 is generated and output based on the comparison result. It is composed of a selection determination section 40. In the clock selection section 20, three clock is selected based on the clock selection signal outputted from the clock selection decision unit 40.

The three-point sampling unit 30 includes a flip-flop 31 for receiving received data using the clock with the most advanced phase among the three clocks output from the clock selection unit 20, and a clock selection determination unit A buffer 34 for supplying the received data using a clock having a central phase among the three clocks output from the clock selector 20, and a buffer 35 for outputting the clock. And a flip-flop 33 that takes in the received data using the clock with the most delayed phase among the three clocks output from the clock selector 20, and that the load capacity of the clock is the same as the load capacity of the other two clocks. And a buffer 36 for adjusting the Data output from 32 is output as the output data, clock output from the buffer 35 is output as the output clock.

The clock selection determining section 40 receives the three data output from the three-point sampling section 30, compares the three input data, and outputs the three data to the clock selecting section 20 based on the comparison result. The phase comparison unit 50 determines whether to advance or delay the phase of the selected clock, and outputs a result of the determination. The phase comparison unit 50 includes an UP / DOWN counter based on the determination result output from the phase comparison unit 50. , A counter section 60 that increments or decrements the value of the counter and outputs it as a clock selection signal.

FIG. 2 is a block diagram showing the clock selection unit 20 shown in FIG.
FIG. 3 is a block diagram showing an example of the configuration.

The clock selection unit 20 shown in this configuration example is the same as that shown in FIG.
As shown in FIG. 2, the selectors 21 to 23 are composed of three clocks CLK0 to CLK multi-phased by the multi-phase clock generator 10 in each of the selectors 21 to 23.
(N−1) and the clock selection signal SEL output from the clock selection determination unit 40 are input. Note that the k-th clock CLKk is the (k + 1) -th input of the selector 21, the k-th input of the selector 22, and the
Is input to the (k-1) th input. However, the 0th input of the selector 21 is CLK (N−1), the selector 2
The (N-1) th input of CLK3 is CLK0.

The clock selector 2 configured as described above
At 0, one of the input clocks CLK0 to CLK (N-1) is selected in each of the selectors 21 to 23 based on the clock selection signal SEL.

The clock selected by selector 21 is output as clock CK1, the clock selected by selector 22 is output as clock CK2, and the clock selected by selector 23 is output as clock CK3.

As a result, the three clocks CK1 to CK3 output from the clock selection unit 20 become clocks having a phase difference of 1 / N of one cycle from each other, and CK1, CK2, CK3 and Become.

FIG. 3 is a circuit diagram showing a configuration example of the phase comparison section 50 shown in FIG.

As shown in FIG. 3, the phase comparison unit 50 shown in this configuration example performs an exclusive OR operation on the data output from the flip-flop 31 and the data output from the flip-flop 32 in the three-point sampling unit 30. XOR gate 51a, and the data output from flip-flop 32 in three-point sampling section 30 and flip-flop 33
XOR gate 51b that takes an exclusive OR with the data output from XOR gate 51, flip-flop 52a that takes in the signal output from XOR gate 51a based on the clock supplied from three-point sampling unit 30, and XOR gate 51b A three-point sampling unit 30 outputs the output signal.
A flip-flop 52b that takes in the clock based on the clock supplied from the FF, AND gates 53a and 53b, flip-flops 54a and 54b, an OR gate 55, flip-flops 56a to 56d, and a NOR gate 57. In a circuit including AND gates 53a and 53b, flip-flops 54a and 54b, an OR gate 55, flip-flops 56a to 56d, and a NOR gate 57, when 1 is set to the flip-flop 52a, the UP which becomes the output of the flip-flop 54a Is output for only one pulse, 0 is output for the next 5 clocks, and 1 is output to the flip-flop 52b.
Is set, 1 is output for one pulse to DOWN which is the output of the flip-flop 54b, and 0 is output for the next five clocks. When 1 is set to the flip-flops 52a and 52b at the same time, the flip-flop 52a has priority.

The operation of the high-speed data receiving circuit configured as described above will be described below.

FIG. 4 is a timing chart for explaining the operation of the high-speed data receiving circuit shown in FIGS. 1 to 3, and shows the operation when the multi-phase clock generating unit 10 generates an eight-phase clock. Is shown.

When the received clock is input to the multi-phase clock generator 10, the multi-phase clock generator 10 first changes the phase in steps of 1 / N (N ≧ 4) of one cycle of the received clock. N delayed clocks are generated.
In the present embodiment, eight clocks CLK0 to CLK7 are generated.

8 generated by the multi-phase clock generator 10
Clocks CLK0 to CLK7
And three clocks having a phase difference of 1 / N of one cycle among the clocks CLK0 to CLK7 in the clock selection unit 20 based on the clock selection signal SEL output from the clock selection determination unit 40.
1 to CK3.

Here, as shown in FIG. 4, when the clock selection signal SEL output from the clock selection determining unit 40 switches at time t0, the clocks output as the clocks CK1 to CK3 also change accordingly. . When the clock selection signal SEL is 5, the clock C
LK4 is selected and output as clock CK1, clock CLK5 is selected and output as clock CK2, and clock CLK6 is selected and output as clock CK3. When the clock selection signal SEL is 6, the clock CLK5 is selected and output as the clock CK1, the clock CLK6 is selected and output as the clock CK2, and the clock CLK7 is selected and output as the clock CK3. Thus, CK
The numbers of the clocks CLK0 to CLK7 output as 1 are SEL-1, the numbers of the clocks CLK0 to CLK7 output as CK2 are SEL, and the numbers of the clocks CLK0 to CLK7 output as CK3 are SE.
L + 1.

As described above, the clocks CK1 to CK3 output from the clock selector 20 are clocks having a phase difference of 1/8 of one cycle from each other. In this configuration example, the selectors 21 to 21 are provided for easy understanding.
23 is 0.

The clocks CK1 to CK3 output from the clock selection unit 20 are input to the three-point sampling unit 30, and the three-point sampling unit 30 outputs the clock CK1.
To CK3 are input to the buffers 34 to 36,
In the flip-flops 31 to 33, the clock CK1
The received data is taken in at the timing of the rising edge of CK3 and output to the clock selection determining unit 40.

In the clock selection determining section 40, the data output from the flip-flop 31 and the flip-flop 3 in the XOR gate 51a in the phase comparing section 50 are output.
2 is compared with the data output from 2 and the comparison result is taken into the flip-flop 52a. Therefore, when 1 is set in the flip-flop 52a, a change point of the received data exists between the rise of the clock CK1 and the rise of the clock CK2. In this case, it is determined that the margin of the setup time is small,
As a signal, 1 is output for only one pulse, and the counter section 60
In, the counter value is incremented, and a clock selection signal based on the increment is output to the clock selection unit 20.

As a result, the three clocks CK1 to CK3 selected by the clock selection unit 20 become clocks each incremented by one of the clocks CLK0 to CLK7, and the phases of the clocks CK1 to CK3 are delayed. Thereby, the flip-flop 32
The time for setup time is increased.

The XOR gate 5 in the phase comparator 50
In 1b, the data output from the flip-flop 32 is compared with the data output from the flip-flop 33, and the comparison result is taken into the flip-flop 52b. Therefore, when 1 is set to the flip-flop 52b, a change point of the received data exists between the rising edge of the clock CK2 and the rising edge of the clock CK3. In this case, it is determined that the margin of the hold time is short, and the DOWN signal is set to 1 for one pulse.
Is output, the counter value is decremented in the counter section 60, and a clock selection signal based on the decrement is output to the clock selection section 20.

As a result, the three clocks CK1 to CK3 selected by the clock selection unit 20 become decremented clocks by one of the clocks CLK0 to CLK7, respectively, and the phases of the clocks CK1 to CK3 are advanced. Thereby, the margin of the hold time of the flip-flop 32 increases.

When the outputs from the flip-flops 52a and 52b are both 0, reception is performed between the rising edges of the clock CK1 and the clock CK2 and between the rising edges of the clock CK2 and the clock CK3. There is no data change point. In this case, it is determined that the margin of the setup time and the hold time is sufficiently large, 0 is output for both the UP signal and the DOWN signal, and the counter unit 60 holds the current counter value.

Therefore, the clocks CK1 to CK3 output from the clock selection unit 20 do not change, and a state in which there is sufficient setup time and hold time is maintained.

When the outputs from the flip-flops 52a and 52b are both 1, both the rising edge of the clock CK1 and the rising edge of the clock CK2, and the rising edge of the clock CK2 and the rising edge of the clock CK3. There will be a transition point in the received data, which is an abnormal condition that cannot normally occur. In this case, 1 is output as an UP signal from the phase comparison unit 50, and the counter value is incremented in the counter unit 60.

As described above, the flip-flops 31 to 33
Are compared with each other, and when a mismatch is detected and it is determined that the margin of the setup time or the hold time is small, the clock selection unit 2 increases the margin.
Although the clock selected at 0 is switched, the above-described comparison operation is restarted even after the clock is switched,
When the margin of the setup time or the hold time is reduced again due to the fluctuation of the power supply voltage or the temperature, the clock is switched again.

Here, a mismatch between the outputs from the flip-flops 31 to 33 is detected, 1 is output as one pulse as an UP signal or a DOWN signal, and then the clock selected by the clock selection unit 20 is switched to restart the comparison. Although several clocks are required before the operation is performed, in the present embodiment, the flip-flop 5
6a to 56d and a NOR gate 57 are provided,
As a result, the comparison result of the flip-flops 52a and 52b is ignored for five clocks after 1 is output as one pulse as the UP signal or the DOWN signal. In this embodiment, the four flip-flops 56a
Although ~ 56d is provided, the number of flip-flops may be increased or decreased according to the time required until the comparison is restarted.

The operation of the clock selection determining section 40 based on the operation of the three-point sampling section 30 will be described below.

FIG. 5 is a timing chart for explaining the operation of the three-point sampling section 30 and the clock selection determining section 40 shown in FIGS.

First, in the flip-flop 31, the received data is fetched at the rising edge of the clock CK1, and is input to the phase comparator 50 as data D1.

In the flip-flop 32, the received data is fetched at the rising edge of the clock CK2 and input to the phase comparator 50 as data D2.

In the flip-flop 33, the received data is fetched at the rising edge of the clock CK3 and is input to the phase comparator 50 as data D3.

In the XOR gate 51a in the phase comparison unit 50, the data D1 output from the flip-flop 31 and the data D1 output from the flip-flop 32
Exclusive OR with 2 is obtained, and 1 is output only when they do not match.

The XOR gate 5 in the phase comparator 50
In 1b, the exclusive OR of the data D2 output from the flip-flop 32 and the data D3 output from the flip-flop 33 is obtained, and 1 is output only when the two do not match.

Next, in the flip-flop 52a,
The output from the XOR gate 51a is taken in at the rising edge of the clock CK1, and the AND gate 53a
Is input to one of the input terminals.

In the flip-flop 52b,
The output from the XOR gate 51b is taken in at the rising edge of the clock CK1, and the AND gate 53b
Is input to one of the input terminals.

Here, in the initial state, since both the UP output and the DOWN output are 0, the NOR gate 57
Output is 1.

When 1 is output from the flip-flop 52a in this state, 1 is taken into the flip-flop 54a at the rising timing of the clock CK1, and 1 is output as the UP signal.

That is, when the data D1 and the data D2 are different, 1 is output as the UP signal, and the clocks CK1 to CK3 selected by the clock selector 20 are incremented by one.

When 1 is output from the flip-flop 52b, 1 is taken into the flip-flop 54b at the rising timing of the clock CK1, and 1 is output as the DOWN signal.

That is, when the data D2 is different from the data D3, 1 is output as the DOWN signal, and the clocks CK1 to CK3 selected by the clock selector 20 are decremented one by one.

In FIG. 5, the phase of the received data fluctuates, and the rising edge of the clock CK1 and the clock CK2
There are three points of change in the received data between the rising edge of.

In this case, 1 is output from the flip-flop 52a three times. However, the output from the NOR gate 57 becomes 0 for five clocks by the OR gate 55 and the flip-flops 56a to 56d. The third pulse is ignored, and 1 is output as the UP signal only by the first pulse.

As described above, in this embodiment, 3
By always controlling the clock to be selected so that the three data taken in by the point sampling unit 30 match, it is possible to cope with the fluctuation of the phase relationship between the data and the clock, and always keep the margin of the setup time and the hold time sufficiently. , Can receive data accurately.

Further, a phase comparison unit 50 is provided immediately after the three-point sampling unit 30 to compare the phases using the three data acquired by the three-point sampling unit 30. There is no need to adjust the amount of delay. Therefore, it can be applied to high-speed data reception.

FIG. 6 is a block diagram showing the clock selection unit 20 shown in FIG.
FIG. 13 is a block diagram showing another example of the configuration.

The clock selection unit 20 shown in this configuration example is the same as that shown in FIG.
As shown in FIG. 3, the selectors 24 to 26 are composed of three clocks CLK0 to CLK which are multiphased by the multiphase clock generator 10.
(N−1) and the clock selection signal SEL output from the clock selection determination unit 40 are input. Note that the k-th clock CLKk is supplied to the (k + 2) -th input of the selector 24, the k-th input of the selector 25, and the
Is input to the (k-2) th input.

The clock selector 2 configured as described above
In 0, one of the input clocks CLK0 to CLK (N-1) is selected in each of the selectors 24 to 26 based on the clock selection signal SEL.

In the selector 24, the clock CLK
0 to CLK (N-1), the clock selection signal (SE
The clock of the number L-2) is output as the clock CK1.
Among the clocks LK (N−1), the clock of the number of the clock selection signal SEL is output as the clock CK2, and the clocks CLK0 to CLK (N−1) are output from the selector 26.
Among them, the clock of the number of the clock selection signal (SEL + 2) is output as the clock CK3.

As a result, three clocks having a phase difference of 2 / N (N ≧ 6) are output from the clocks CK1 to CK3.

Similarly, from the clocks CK1 to CK3, 1
It is also possible to output three clocks having a phase difference of K / N (K ≧ 3, N ≧ 2K + 2) of the cycle.

Further, clock CK1 and clock CK2
The phase difference between the clock CK1 and the clock CK2 and the clock C are set such that the phase difference between the clock CK2 and the clock CK3 is 1 / N of the cycle.
The phase difference between K2 and clock CK3 may be different.

FIG. 7 is a block diagram of the clock selection unit 20 shown in FIG.
FIG. 13 is a block diagram showing another example of the configuration.

The clock selecting section 20 shown in this configuration example is the same as that shown in FIG.
As shown in the figure, the clocks CLK0 to CLK (N-1) multi-phased by the multi-phase clock generation unit 10 and the clock selection signal SEL output from the clock selection determination unit 40 are input, and based on the clock selection signal SEL. And one of the clocks CLK0 to CLK (N-1) is
A selector 27 for setting K1; a delay unit 28 for delaying the clock CK1 output from the selector 27 by a predetermined delay amount to output the clock CK2; and a clock CK2 output from the delay unit 28 are determined in advance. And a delay unit 29 that delays by the delay amount and outputs the clock CK3.

The clock selector 2 configured as described above
At 0, the delay amounts in the delay units 28 and 29 can be set arbitrarily, so that the clocks CK1 to CK3
Can be set arbitrarily.

Here, in the above-described embodiment,
When the duty of the received data is deteriorated, there is a possibility that correct data cannot be received.

FIG. 8 is a timing chart for explaining the operation of the high-speed data receiving circuit shown in FIG. 1 when the rise of the received data is delayed and the duty of the received data is degraded. Deteriorated and the rising edge of the received data is CLK1
Between the rising edge of CLK7 and the rising edge of CLK2.
This shows a case between the rising edge of zero.

First, it is assumed that CLK5 is first selected as the clock CK2 input to the flip-flop 32.

In this case, the rise of CLK4 and CLK4
5 and the rising edge of CLK5 and CL
There is no change point in the received data even between the rise of K6. Therefore, in the clock selection unit 20, CLK5
Are continuously selected, "1" and "0" are alternately output from the flip-flop 32, and correct data is received.

Next, it is assumed that CLK0 is initially selected as the clock CK2 input to the flip-flop 132.

In this case, the rise of CLK7 and CLK7
Since a data change point (falling edge) is detected before the rising edge of 0, it is determined that the margin of the setup time is small, and the clock selecting unit 20 selects CLK1. Then, the rise of CLK1 and C
Since a data change point (rising edge) is detected before the rising edge of LK2, it is determined that the margin of the hold time is small, and the clock selecting unit 20 selects CLK0.

As described above, CLK0 and CLK1 continue to be alternately selected in the clock selecting section 20, and 0 is always output from the flip-flop 32, and correct data is not received.

(Second Embodiment) FIG. 9 is a block diagram showing a high-speed data receiving circuit according to a second embodiment of the present invention.

In this embodiment, as shown in FIG. 9, a multi-phase clock generator 10 for delaying a reception clock stepwise by 1 / N (N ≧ 6) of one cycle thereof, and a clock selection signal input thereto A clock selection unit 220 that selects and outputs five clocks having a predetermined phase difference among the clocks that have been multi-phased by the multi-phase clock generation unit 10 based on Received five clocks, a five-point sampling unit 230 provided with a flip-flop that captures received data at the rising timing of each of the five clocks, and data captured by the five-point sampling unit 230,
And a clock selection determining unit 240 for generating and outputting a clock selection signal to be input to the clock selection unit 220 based on the comparison result. In, five clocks are selected based on the clock selection signal output from the clock selection determining unit 240.

The five-point sampling section 230 includes a flip-flop 231 for receiving received data using the clock with the most advanced phase among the five clocks output from the clock selection section 220, and a clock selection determination section for determining the clock. A buffer 236 for supplying the received data to the clock 240, a flip-flop 232 for receiving the received data using the clock whose phase is advanced second from the five clocks output from the clock selector 220, and a clock selector 2
A flip-flop 233 for receiving received data using a clock having a central phase among the five clocks output from 20, a buffer 238 for outputting the clock, and five clocks output from the clock selector 220 Among the five clocks output from the clock selection unit 220, the flip-flop 234 that fetches the received data using the clock whose phase is secondly delayed. 233 and the flip-flop 23
And buffers 237a, 237b, and 237c for respectively adjusting the load capacity of the clock input to the flip-flops 231 and 233 to be equal to the load capacity of the clock input to the flip-flops 231 and 233. Data output from the flip-flop 233 is output as output data, and a clock output from the buffer 238 is output as an output clock.

The clock selection determining section 240 receives the three data output from the flip-flops 232, 233, and 234 among the five data output from the five-point sampling section 230, and inputs the three data. , And based on the comparison result, the clock selection unit 22
A phase comparison unit 250 that determines whether to advance or delay the phase of the clock selected at 0 and outputs the determination result
And the three data output from the flip-flops 231, 233, and 235 among the five data output from the five-point sampling unit 230, and compares the three input data. Is detected in the duty deteriorating section, whereby the clock selecting section 220
The phase comparator 250 and the duty deterioration detector 27 are constituted by a duty deterioration detector 270 that determines whether to advance or delay the phase of the clock selected by the selector, and outputs the result of the determination, and an UP / DOWN counter.
A counter 260 for incrementing or decrementing the value of the counter based on the determination result output from 0 and outputting it as a clock selection signal;
The output restricting unit 28 restricts the output of the determination result in the zero and the duty deterioration detecting unit 270 to the counter unit 260.
0.

FIG. 10 is a block diagram of the clock selection unit 2 shown in FIG.
FIG. 20 is a block diagram illustrating an example of a configuration of the device 20.

As shown in FIG. 10, the clock selecting section 220 shown in this configuration example includes five selectors 221 to 225. Clock C
LK0-CLK (N-1) and clock selection determining unit 24
The clock selection signal SEL output from 0 is input. The k-th clock CLKk is supplied to the selector 22
1 (k + 2) th input and the selector 222 (k + 2)
1) -th input, k-th input of selector 223,
(K-1) th input of selector 224 and selector 2
25 (k-2) th inputs.

The clock selector 2 configured as described above
In 20, in each of the selectors 221 to 225, one of the input clocks CLK0 to CLK (N-1) is selected based on the clock selection signal SEL.

The clock selected by selector 221 is output as clock CK1, the clock selected by selector 222 is output as clock CK2, and the clock selected by selector 223 is clock CK3.
The clock selected by the selector 224 is output as a clock CK4, and the clock selected by the selector 225 is output as a clock CK5.

As a result, the five clocks CK1 to CK5 output from the clock selection unit 220 become clocks having a phase difference of 1 / N of one cycle from each other, and CK1, CK2, CK3, CK4, CK
It becomes 5.

FIG. 11 is a block diagram of the phase comparator 25 shown in FIG.
0, duty deterioration detecting section 270 and output regulating section 28
FIG. 2 is a circuit diagram illustrating a configuration example of a zero.

The phase comparison unit 250 shown in this configuration example is different from the one shown in FIG.
As shown in the figure, an XOR gate 251a that performs an exclusive OR operation on the data output from the flip-flop 232 in the five-point sampling unit 230 and the data output from the flip-flop 233, and the flip-flop in the five-point sampling unit 230 XOR gate 251b that takes an exclusive OR of the data output from flip-flop 233 and the data output from flip-flop 234, and XOR gate 25
A flip-flop 252a that takes in the signal output from the first signal generator 1a based on the clock supplied from the five-point sampling unit 230 and outputs the signal as a left change point detection signal;
A flip-flop 252b that takes in the signal output from the XOR gate 251b based on the clock supplied from the five-point sampling unit 230;
The data output from 52b is sampled by a five-point sampling unit 23.
Flip-flop 252c which takes in based on the clock supplied from 0 and outputs it as a right transition point detection signal
A NOT gate 253 for inverting the right change point detection signal output from the flip-flop 252c, a left change point detection signal output from the flip-flop 252a, the signal output from the NOT gate 253, and the duty deterioration detection unit 270 Output signal and output control unit 2
AN that takes a logical product with the output regulation signal output from 80
A D-gate 254a, and an AND gate 25 that performs a logical product of the right transition point detection signal output from the flip-flop 252c, the signal output from the duty deterioration detection unit 270, and the output restriction signal output from the output restriction unit 280.
4b and the signal output from the AND gate 254a
A flip-flop 252d that fetches based on the clock supplied from the point sampling unit 230 and outputs it as an UP signal, and a signal output from the AND gate 254b is fetched based on the clock supplied from the five-point sampling unit 230 and outputs a DOWN signal And a flip-flop 252e that outputs the data as

Further, as shown in FIG. 11, the duty deterioration detecting section 270 shown in the present configuration example excludes the data output from the flip-flop 231 and the data output from the flip-flop 233 in the 5-point sampling section 230. XOR gate 271a for performing an exclusive OR operation, and XOR gate 271b for performing an exclusive OR operation on the data output from flip-flop 233 and data output from flip-flop 235 in five-point sampling section 230
And a flip-flop 272a that takes in the signal output from the XOR gate 271a based on the clock supplied from the five-point sampling unit 230, and the data output from the flip-flop 233 in the five-point sampling unit 230 A flip-flop 272b to take in based on the clock supplied from 230;
A flip-flop 272c that takes in the signal output from the XOR gate 271b based on the clock supplied from the five-point sampling unit 230;
The data output from 72b is sampled by a five-point sampling unit 23.
A flip-flop 272d that takes in data based on the clock supplied from 0, and a flip-flop 27 that takes in data output from the flip-flop 272c based on the clock supplied from the five-point sampling unit 230.
2e, an XOR gate 271c that takes an exclusive OR of the data output from the flip-flop 272b and the data output from the flip-flop 272d, and outputs the data as a data change detection signal, and the data change output from the XOR gate 271c. A NOT gate 273a for inverting the detection signal, an AND gate 274a for taking a logical product of the data output from the flip-flop 272a and the signal output from the NOT gate 273a, and outputting the result as a left duty deterioration detection signal, and a flip-flop 272e. And the NOT gate 273a
AND gate 274b which takes the logical product with the signal output from the first and outputs it as a right duty deterioration detection signal
A NOR gate 275 that performs a logical OR operation of a left duty deterioration detection signal output from the AND gate 274a and a right duty deterioration detection signal output from the AND gate 274b, and a left duty deterioration output from the AND gate 274b. N to invert the detection signal
OT gate 273b, left duty deterioration detection signal output from AND gate 274a, and output control unit 28
AND for ANDing with the output regulation signal output from 0
A gate 274c, and an AND gate 274d that calculates the logical product of the right duty deterioration detection signal output from the AND gate 274b, the output control signal output from the output control unit 280, and the signal output from the NOT gate 273b.
And a flip-flop 272f for taking in the signal output from the AND gate 274c based on the clock supplied from the five-point sampling unit 230 and outputting the signal as a DDOWN signal, and a signal output from the AND gate 274d for the five-point sampling unit 230. And a flip-flop 272g that takes in the clock based on the clock supplied from and outputs it as a DUP signal. Note that N
The signal output from the OR gate 275 is output to the phase comparator 26.
It is input to the NAND gates 254a and 254b in 0, respectively.

Further, as shown in FIG. 11, the output restricting section 280 shown in this configuration includes an UP signal output from the flip-flop 252d, a DOWN signal output from the flip-flop 252e, and a DDOWN signal output from the flip-flop 272f. OR gate 28 which takes the logical sum of the DUP signal output from flip-flop 272g
1, a flip-flop 283a that takes in the signal output from the OR gate 281 based on the clock supplied from the five-point sampling unit 230, and a five-point sampling unit 2 that captures the data output from the flip-flop 283a.
Flip-flop 283b that takes in based on a clock supplied from clock 30 and flip-flop 2 that takes in data output from flip-flop 283b based on a clock supplied from 5-point sampling section 230
83c, a flip-flop 283d for taking in data output from the flip-flop 283c based on the clock supplied from the five-point sampling unit 230, and a clock supplied from the five-point sampling unit 230 for data output from the flip-flop 283d. 283e, which takes in data based on the clock, a flip-flop 283f, which takes in data output from the flip-flop 283e based on a clock supplied from the five-point sampling unit 230, a signal output from the OR gate 281 and the flip-flop 283a. Data output, data output from flip-flop 283b, data output from flip-flop 283c, data output from flip-flop 283d, and flip-flop 283 It takes a negative logical sum of the output data from the output data and the flip-flop 283f from, NOR gate 28 to output as an output regulation signal
And 2. Note that the output regulation signal output from the NOR gate 282 is
The signals are input to the ND gates 254a and 254b and the AND gates 274c and 274d in the duty deterioration detector 270, respectively.

The phase comparator 250 constructed as described above
In the case where the data fetched by the flip-flop 232 in the five-point sampling unit 230 is different from the data fetched by the flip-flop 233, that is, if the margin of the setup time in the flip-flop 233 is small, the flip-flop 252a Is output, and the left transition point detection signal is set to 1.

When the data fetched by the flip-flop 233 in the five-point sampling unit 230 is different from the data fetched by the flip-flop 234, that is, when the margin of the hold time in the flip-flop 233 is small, 1 is output from the loop 252c, and the right transition point detection signal is set to 1.

Further, in the duty deterioration detecting section 270 configured as described above, the XOR gate 271c
, An exclusive OR of the data output from the flip-flop 272b and the data output from the flip-flop 272d is performed, so that the data fetched by the flip-flop 233 in the five-point sampling unit 230 is clocked by one clock before. Is compared with the data fetched, and the comparison result is output as a data change detection signal. If the data fetched by the flip-flop 233 differs from the data fetched by the clock one cycle before, 1 is output as a data change detection signal.

In the AND gate 274a,
Flip-flop 231 in 5-point sampling section 230
Is different from the data captured by the flip-flop 233 and the data change detection signal is 0, that is, the data captured by the flip-flop 233 and the data captured by the clock one cycle earlier are different. In the same case, 1 is output as the left duty deterioration detection signal.

In addition, in AND gate 274b,
Flip-flop 233 in 5-point sampling section 230
Is different from the data captured by the flip-flop 235 and the data change detection signal is 0, that is, the data captured by the flip-flop 233 and the data captured by the clock one cycle earlier are different. In the same case, 1 is output as the right duty deterioration detection signal.

When the left transition point detection signal becomes 1, 1 is outputted as one pulse in the UP signal, and when the right transition point detection signal becomes 1, 1 is outputted as one pulse in the DOWN signal. , The left duty deterioration detection signal is 1
In this case, 1 is output for one pulse in the DDOWN signal, and 1 is output for one pulse in the DUP signal when the right duty deterioration detection signal is 1, but the left transition point detection signal, When a plurality of signals among the right change point detection signal, the left duty deterioration detection signal, and the right duty deterioration detection signal become 1, the NOT gates 253, 273b, the AND gates 254a, 254
b, 274c, 274d and the NOR gate 275, the left-side duty deterioration detection signal, the right-side duty deterioration detection signal, the right-side transition point detection signal, and the left-side transition point detection signal are prioritized in the order of DDOWN signal, D
Only one of the UP signal, the DOWN signal, and the UP signal is output.

In the output restricting section 280 configured as described above, the UP signal, DOWN signal, DDOW
For 7 clocks after 1 is output to one of the N signal and the DUP signal, the UP signal, the DOWN signal, the DDO
An output regulation signal that outputs 0 as the WN signal and the DUP signal is output. In the present embodiment, seven clocks are set by the six flip-flops 283a to 283f during the output control signal output time.
It can be controlled by changing the number of flip-flops.

Hereinafter, the operation of the high-speed data receiving circuit configured as described above will be described.

FIG. 12 is a timing chart for explaining the operation of the high-speed data receiving circuit shown in FIGS. 9 to 11, in which a multi-phase clock generator 10 generates an eight-phase clock and a clock selector. At 220, an operation for selecting a clock is shown.

When the received clock is input to the multi-phase clock generator 10, first, the multi-phase clock generator 10 changes the phase in steps of 1 / N (N ≧ 6) of one cycle of the received clock. N delayed clocks are generated.
In the present embodiment, eight clocks CLK0 to CLK7 are generated.

8 generated by the multi-phase clock generator 10
Clocks CLK0 to CLK7
0, and the clock selection unit 220 outputs the clock selection signal S output from the clock selection determination unit 240.
Based on EL, one of clocks CLK0-CLK7
Five clocks having a phase difference of 1 / N of the cycle are output as clocks CK1 to CK5.

Here, as shown in FIG. 12, clock selection signal SEL output from clock selection determination unit 240
Are switched at time t0, the clocks output as clocks CK1 to CK5 are also switched accordingly. When the clock selection signal SEL is 5, the clock CLK3 is selected and output as the clock CK1,
The clock CLK4 is selected and output as the clock CK2, the clock CLK5 is selected and output as the clock CK3, the clock CLK6 is selected and output as the clock CK4, and the clock CLK7 is selected and output as the clock CK5. When the clock selection signal SEL is 6, the clock CLK4 is selected and output as the clock CK1, and the clock CLK5 is output.
Are selected and output as the clock CK2, and the clock CLK6 is selected and output as the clock CK3,
The clock CLK7 is selected and output as the clock CK4, and the clock CLK0 is selected and output as the clock CK5. Thus, the numbers of the clocks CLK0 to CLK7 output as CK1 are SEL-2, and the clocks CLK0 to CLK output as CK2.
7 is SEL-1, and the numbers of clocks CLK0 to CLK7 output as CK3 are SEL.
The numbers of the clocks CLK0 to CLK7 output as K4 are SEL + 1, and the numbers of the clocks CLK0 to CLK7 output as CK5 are SEL + 2.

As described above, the clocks CK1 to CK5 output from the clock selector 220 are clocks having a phase difference of 1/8 of one cycle from each other. Note that, in this configuration example, the selector 22
The delay amount of 1 to 225 is set to 0.

The clocks CK1 to CK5 output from the clock selection unit 220 are input to the five-point sampling unit 230, and the five-point sampling unit 230
K1 to CK5 are buffers 236, 237a to 237c,
238 and the flip-flop 231
In 235, the received data is fetched at the rising timing of the clocks CK1 to CK5 and output to the clock selection determining unit 240.

In clock selection determining section 240, data D2 output from flip-flop 232 and data D3 output from flip-flop 233 are compared by XOR gate 251a in phase comparing section 250, and the comparison result is output by flip-flop. And is output as a left transition point detection signal. for that reason,
When 1 is output as the left transition point detection signal, a transition point of the received data exists between the rise of the clock CK2 and the rise of the clock CK3. In this case, it is determined that the margin of the setup time is small, and U
1 is output only for one pulse as the P signal, and the counter 2
At 60, the counter value is incremented, and a clock selection signal based on the counter value is
Is output to

As a result, the five clocks CK1 to CK5 selected by the clock selection unit 220 become clocks each incremented by one of the clocks CLK0 to CLK7, and the phases of the clocks CK1 to CK5 are delayed. Thereby, flip-flop 2
The margin of the setup time of 33 increases.

In the XOR gate 251b in the phase comparison section 250, the data D3 output from the flip-flop 233 is compared with the data D4 output from the flip-flop 234, and the comparison result is output to the flip-flops 252b and 252c. And is output as a right transition point detection signal. Therefore, when 1 is output as the right transition point detection signal, a transition point of the received data exists between the rise of the clock CK3 and the rise of the clock CK4. In this case, it is determined that the margin of the hold time is short, 1 is output as one pulse as the DOWN signal, the counter value is decremented in the counter 260, and the clock selection signal based on the decrement is sent to the clock selector 220. Is output.

As a result, the five clocks CK1 to CK5 selected by the clock selection unit 220 become decremented clocks by one of the clocks CLK0 to CLK7, respectively, and the phases of the clocks CK1 to CK5 are advanced. Thereby, the flip-flop 233
Hold time is increased.

In the XOR gate 271c in the duty deterioration detecting section 270, the flip-flop 2
The output from the flip-flop 272b, to which the data output from the flip-flop 33 is captured, is compared with the output from the flip-flop 272d, the output of which is captured at the next clock, and the comparison result is output as a data change detection signal. Is done. As a result, when the data captured by the flip-flop 233 changes, 1 is output as a data change point detection signal. This data change detection signal is used for left duty deterioration detection and right duty deterioration detection.

In the XOR gate 271a in the duty deterioration detecting section 270, the flip-flop 2
Data D1 output from 31 and flip-flop 23
3 is compared with the data D3 output, and the comparison result is taken into the flip-flop 272a. Therefore, when the output from the flip-flop 272a becomes 1, a change point of the received data exists between the rising edge of the clock CK1 and the rising edge of the clock CK3.

When the output of the flip-flop 272a is 1,
When the data change detection signal is 0, the left duty deterioration detection signal is 1. In this case, it is determined that the data D3 output from the flip-flop 233 is within the duty deterioration range, 1 is output as one pulse as the DDOWN signal, and the counter 260 outputs the data output from the flip-flop 233. The counter value is decremented by an amount necessary for D3 to come out of the duty deterioration range, and a clock selection signal based on the decrement is output to clock selection section 220.

As a result, the five clocks CK1 to CK5 selected by the clock selection unit 220 are the same as those of the flip-flops 23 of the clocks CLK0 to CLK7, respectively.
3 becomes a clock decremented as much as necessary to get out of the duty deterioration range, and the phases of the clocks CK1 to CK5 are advanced. As a result, the data D3 output from the flip-flop 233 comes out of the duty deterioration range.

In the XOR gate 271b in the duty deterioration detecting section 270, the flip-flop 2
33 and the data D3 output from the flip-flop 23
5 is compared with the data D5 output from the memory 5 and the comparison result is taken into the flip-flop 272c and further taken into the flip-flop 272e. Therefore, when the output of the flip-flop 272e becomes 1, a change point of the received data exists between the rise of the clock CK3 and the rise of the clock CK5.

When the output of the flip-flop 272e is 1,
When the data change detection signal is 0, the right duty deterioration detection signal is 1. In this case, it is determined that the data D3 output from the flip-flop 233 is within the duty deterioration range, and the DUP signal is set to 1
Only one pulse is output, and in the counter 260, the data D3 output from the flip-flop 233 is output.
The counter value is incremented as necessary to escape from the duty deterioration range, and a clock selection signal based on the counter value is output to the clock selection unit 220.

As a result, the five clocks CK1 to CK5 selected by the clock selection unit 220 are the same as the flip-flops 23 of the clocks CLK0 to CLK7, respectively.
3 becomes a clock that is incremented as necessary to get out of the duty deterioration range, and the phases of the clocks CK1 to CK5 are delayed. As a result, the data D3 output from the flip-flop 233 comes out of the duty deterioration range.

When the left change point detection signal, the right change point detection signal, the left duty deterioration detection signal, and the right duty deterioration detection signal are all 0, the margin of the setup time and the hold time is sufficiently large, and
It is determined that the data D3 output from the flip-flop 233 does not fall within the duty deterioration range,
As the signal, the DOWN signal, the DDOWN signal, and the DUP signal, all 0s are output.
The current counter value is held.

Therefore, the clocks CK1 to CK5 output from the clock selection unit 220 do not change, the margin for the setup time and the hold time is sufficiently large, and the data D3 output from the flip-flop 233
Is maintained within the duty deterioration range.

When a plurality of signals among the left change point detection signal, the right change point detection signal, the left duty deterioration detection signal, and the right duty deterioration detection signal are 1, priority must be given to the duty deterioration detection. In this case, the DDOWN signal, the DUP signal, the DOWN signal, and the UP signal are set in descending order of priority, and only one of them is set to 1.

As described above, the flip-flops 231 to 231
The output from the flip-flop 23 is compared with the data D3 output from the flip-flop 233, and if it is determined that the data D3 is within the duty deterioration range.
When the clock selected by the clock selection unit 220 is switched so that the data D3 output from No. 3 falls out of the duty deterioration range, and it is determined that the margin of the setup time or the hold time is small, The clock selected by the clock selection unit 220 is switched so as to increase the margin. However, even after the clock is switched, the above-described comparison operation is restarted, and the duty deterioration is detected again due to a change in the power supply voltage or the temperature. If the setup time or the hold time becomes short, the clock is switched again.

Here, the DDOWN signal, DUP signal, D
Several clocks are required from the output of 1 for only one pulse as the OWN signal and the UP signal to the time when the clock selected by the clock selection unit 220 is switched and the comparison is restarted. 280
OR gate 281, flip-flop 2 provided in
83a to 283f and NOR gate 282, DD
During 7 clocks after 1 is output as one pulse to any of the DOWN signal, the DUP signal, the DOWN signal, and the UP signal, the left transition point detection signal, the right transition point detection signal, the left duty deterioration detection signal, and the right side The duty deterioration detection signal is ignored. In this embodiment, 6
Although the flip-flops 283a to 283f are provided, the number of flip-flops may be increased or decreased according to the time required until the comparison is restarted.

The operation of clock selection determining section 240 based on the operation of 5-point sampling section 230 will be described below.

FIGS. 13 and 14 are timing charts for explaining the operation of the five-point sampling section 230 and the clock selection determining section 240 shown in FIGS. 9 and 11.

First, in the flip-flop 231,
The received data is captured at the rising timing of the clock CK1 and is input to the duty deterioration detection unit 270 as data D1.

In the flip-flop 232,
Received data is captured at the rising edge of the clock CK2, and is input to the phase comparison unit 250 as data D2.

In the flip-flop 233,
The received data is captured at the rising timing of the clock CK3, and is input to the phase comparison unit 250 and the duty deterioration detection unit 270 as data D3.

In the flip-flop 234,
The received data is captured at the rising timing of the clock CK4, and is input to the phase comparison unit 250 as data D4.

In the flip-flop 235,
The received data is captured at the rising timing of the clock CK5 and is input to the duty deterioration detection unit 270 as data D5.

XOR gate 251 in phase comparison section 250
In a, the exclusive OR of the data D2 output from the flip-flop 232 and the data D3 output from the flip-flop 233 is obtained, and the result is input to the flip-flop 252a. The output of the flip-flop 252a is output as a left transition point detection signal. Note that 1 is output as the left transition point detection signal only when the data D2 and the data D3 do not match.

XOR gate 251 in phase comparison section 250
In b, the exclusive OR of the data D3 output from the flip-flop 233 and the data D4 output from the flip-flop 234 is obtained, and the result is taken into the flip-flop 252b and further taken into the flip-flop 252c. . Flip-flop 252
The output of c is output as a right transition point detection signal. Note that 1 is output as the right transition point detection signal only when the data D3 and the data D4 do not match.

XOR in duty deterioration detecting section 270
The gate 271c performs an exclusive OR operation on the data D3 output from the flip-flop 233 and the data D3 output one cycle before from the flip-flop 233, and outputs the result as a data change detection signal. The data change detection signal is 1 only when the data D3 changes.

XOR in duty deterioration detecting section 270
In the gate 271a, the exclusive OR of the data D1 output from the flip-flop 231 and the data D3 output from the flip-flop 233 is obtained, and the result is taken into the flip-flop 272a. Note that the output of the flip-flop 272a becomes 1 only when the data D1 and the data D3 do not match.

XOR in duty deterioration detecting section 270
In the gate 271b, an exclusive OR of the data D3 output from the flip-flop 233 and the data D5 output from the flip-flop 235 is taken, and the result is taken into the flip-flop 272c and further taken into the flip-flop 272e. It is. The output of the flip-flop 272e becomes 1 only when the data D3 and the data D5 do not match.

AND in Duty Degradation Detection Unit 270
In the gate 274a, the flip-flop 272a
Based on the output and the data change detection signal, it is determined whether or not data D3 output from flip-flop 233 is within the duty deterioration range, and the result of the determination is output as a left duty deterioration signal. Specifically, when the output of the flip-flop 272a is 1 (that is, a change point is detected on the left side) and the data change detection signal is 0 (that is, the data captured by the flip-flop 233 does not change), It is determined that data D3 output from H.233 is within the duty deterioration range.

AND in Duty Degradation Detection Unit 270
In the gate 274b, the flip-flop 272e
Based on the output and the data change detection signal, it is determined whether or not data D3 output from flip-flop 233 is within the duty deterioration range, and the result of the determination is output as a right duty deterioration signal. Specifically, when the output of the flip-flop 272e is 1 (that is, a change point is detected on the right side) and the data change detection signal is 0 (that is, the data captured by the flip-flop 233 does not change), It is determined that data D3 output from H.233 is within the duty deterioration range.

On the other hand, in the initial state, UP output, DO
Since the WN output, the DDOWN output, and the DUP output are all 0, the output of the NOR gate 282 in the output control unit 280 is 1.

When the left duty deterioration signal becomes 1 in this state, 1 is taken in the flip-flop 272f, and 1 is output as the DDOWN signal. As a result, in the counter section 260, the counter is decremented by an amount necessary for the data D3 output from the flip-flop 233 to come out of the duty deterioration range, and the clocks CK1 to CK5 selected by the clock selection section 220 Step 23
3 is decremented by an amount necessary to escape from the duty deterioration range. Note that in this embodiment, if the counter is decremented three times, the data D output from the flip-flop 233 is output.
3 can get out of the duty deterioration range.

In the initial state, when the left duty deterioration signal becomes 0 and the right duty deterioration signal becomes 1, 1 is taken in the flip-flop 272g, and 1 is output as the DUP signal. As a result, in the counter section 260, the counter is incremented by an amount necessary for the data D3 output from the flip-flop 233 to come out of the duty deterioration range, and the clocks CK1 to CK5 selected by the clock selection section 220 The data D3 output from the loop 233 is incremented by an amount necessary to escape from the duty deterioration range. In the present embodiment, if the counter is incremented three times, the data D3 output from the flip-flop 233 can come out of the duty deterioration range.

In the initial state, when the left duty deterioration signal and the right duty deterioration signal become 0 and the right change point detection signal becomes 1, the flip-flop 252e
Is taken in, and 1 is output as a DOWN signal. As a result, in the counter 260, the counter is decremented in order to increase the margin of the hold time, and the clocks CK1 to CK5 selected by the clock selector 220 are decremented one by one.

In the initial state, when the left duty deterioration signal, the right duty deterioration signal, and the right change point detection signal become 0 and the left change point detection signal becomes 1, 1 is taken into the flip-flop 252d. 1 is output as the UP signal. As a result, in the counter section 260, the counter is incremented in order to increase the margin of the setup time, and the clocks CK1 to CK5 selected by the clock selection section 220 become 1
It is incremented by one.

FIG. 13 shows an example in which duty deterioration has occurred in the received data, and the left change point detection signal and the left duty deterioration signal become 1.

As shown in FIG. 13, 1 is output three times as the left transition point detection signal, the right transition point detection signal, and the left duty degradation signal, respectively. By DD
1 is output as the OWN signal. This DDOWN signal causes the output of NOR gate 282 to go to 0 for 7 clocks.
And the second and third pulses of the left duty deterioration signal are ignored.

The dashed line shown in FIG. 13 shows the waveform when there is no duty deterioration. In this case, the left duty deterioration signal, the right duty deterioration signal,
The right transition point detection signal and the left transition point detection signal are all 0, and the UP signal, DOWN signal, DDOWN signal, and D
All UP signals are 0.

FIG. 14 shows an example in which the received data has undergone duty deterioration, and the right change point detection signal and the right duty deterioration signal become 1.

As shown in FIG. 14, 1 is output three times as the right transition point detection signal and the right duty deterioration signal, respectively. However, the right duty deterioration signal is prioritized, and 1 is output as the DUP signal by the first pulse. Is output. With this DUP signal, the output of the NOR gate 282 becomes 0 for seven clocks, and the second and third pulses of the right duty deterioration signal are ignored.

The broken line shown in FIG. 14 shows the waveform when the duty is not deteriorated. In this case, the right transition point detection signal becomes 1, and the DOWN signal becomes 1 for one pulse.

As described above, in this embodiment, 5
Of the five data fetched by the point sampling unit 230, it is constantly monitored whether received data is within the duty deterioration range from the data fetched by the flip-flops 231, 233, and 235. If it is determined that the received data is included, the clock that is selected so as to escape from the duty deterioration range is controlled, whereby the received data can escape from the duty deterioration range.

Further, among the five data fetched by the five-point sampling section 230, the flip-flop 232,
By controlling the clock which is always selected so that the data taken in by 233 and 234 coincide, it is possible to cope with the fluctuation of the phase relationship between the data and the clock, always keep the margin of the setup time and the hold time sufficiently, and accurately Data can be received.

FIG. 15 shows the clock selection unit 2 shown in FIG.
FIG. 20 is a block diagram showing another example of the configuration of FIG.

As shown in FIG. 15, the clock selection unit 220 shown in this configuration example is output from the clocks CLK0 to CLK (N-1) multiplied by the multiphase clock generation unit 10 and the clock selection determination unit 240. Clock selection signal SE
L, the selector 226 that sets one of the clocks CLK0 to CLK (N-1) to CK1 based on the clock selection signal SEL, and the clock CK1 output from the selector 226 by a predetermined delay amount. Delay unit 22 that delays the clock signal and outputs it as clock CK2
7a and the clock CK2 output from the delay unit 227a.
Is delayed by a predetermined delay amount and the clock CK3
And a delay unit 227 that delays the clock CK3 output from the delay unit 227b by a predetermined delay amount and outputs the delayed clock CK4 as the clock CK4.
c, and a delay unit 227d that delays the clock CK4 output from the delay unit 227c by a predetermined delay amount and outputs it as the clock CK5.

The clock selector 2 configured as described above
In 20, since the delay amount in the delay units 227 a to 227 d can be set arbitrarily, the clock CK
1 to CK5 can be arbitrarily set.

FIG. 16 is a block diagram of the phase comparator 25 shown in FIG.
0, duty deterioration detecting section 270 and output regulating section 28
FIG. 10 is a circuit diagram illustrating another example of the configuration of the ０0 ’.

The phase comparison section 250 shown in this configuration example is similar to that shown in FIG.
As shown in the figure, an XOR gate 251a that takes an exclusive OR of the data D2 output from the flip-flop 232 in the five-point sampling unit 230 and the data D3 output from the flip-flop 233, An XOR gate 251b that performs an exclusive OR operation on the data D3 output from the flip-flop 233 and the data D4 output from the flip-flop 234,
A flip-flop 252a for taking in the signal output from the XOR gate 251a based on the clock supplied from the five-point sampling unit 230;
and a flip-flop 252b for taking in the signal output from the b-point based on the clock supplied from the five-point sampling unit 230 and a flip-flop for taking in the data output from the flip-flop 252b based on the clock supplied from the five-point sampling unit 230. 252c
A NOT gate 253a for inverting data output from the flip-flop 252a, a NOT gate 253b for inverting data output from the flip-flop 252c, and data output from the flip-flop 252a and data fed back from the output side An XOR gate 251c that takes the exclusive OR of the data and an XO that takes the exclusive OR of the data output from the flip-flop 252c and the data fed back from the output side
The logical product of the signal output from the R gate 251d, the signal output from the XOR gate 251c, the signal output from the NOT gate 253b, the signal output from the duty deterioration detection unit 270, and the output control signal output from the output control unit 280 is calculated. AND gate 254a and XOR gate 251d
AND gate 254b, which takes the logical product of the signal output from the inverter, the signal output from the NOT gate 253a, the signal output from the duty deterioration detection unit 270, and the output control signal output from the output control unit 280. The signal output from the 254a is sampled by a 5-point sampling unit 2
Flip-flop 252d that takes in based on the clock supplied from 30 and flip-flop 252e that takes in the signal output from AND gate 254b based on the clock supplied from 5-point sampling section 230.
AND gate of a signal output from the flip-flop 252a and a signal output from the flip-flop 252d, and outputs an AND gate 254c as a left transition point detection signal; and a signal output from the flip-flop 252c and the flip-flop 252e. AND that outputs the logical product of the signals output from
The D-gate 254d, the flip-flop 252f that fetches the left transition point detection signal output from the AND gate 254c based on the clock supplied from the five-point sampling unit 230, and outputs it as an UP signal, and the output from the AND gate 254d. And a flip-flop 252g that fetches the right transition point detection signal based on the clock supplied from the five-point sampling unit 230 and outputs it as a DOWN signal.
In (c), the exclusive OR of the data output from the flip-flop 252a and the data output from the flip-flop 252d is calculated.
At 51d, the exclusive OR of the data output from the flip-flop 252c and the data output from the flip-flop 252e is calculated.

Further, as shown in FIG. 16, the duty deterioration detecting section 270 shown in the present configuration example excludes the data output from the flip-flop 231 and the data output from the flip-flop 233 in the 5-point sampling section 230. XOR gate 271a for performing an exclusive OR operation, and XOR gate 271b for performing an exclusive OR operation on the data output from flip-flop 233 and data output from flip-flop 235 in five-point sampling section 230
A flip-flop 272a for taking in a signal output from the XOR gate 271a based on a clock supplied from the five-point sampling unit 230, and a XOR gate 2
The signal output from 71b is sampled by a 5-point sampling unit 230.
And a flip-flop 272c that takes in data output from the flip-flop 233 in the five-point sampling unit 230 based on the clock supplied from the five-point sampling unit 230. Step 2
A NOT gate 273a for inverting the data output from the 72a, a flip-flop 272d for taking in the data output from the flip-flop 272b based on the clock supplied from the five-point sampling unit 230,
A NOT gate 273b for inverting data output from the flip-flop 272d;
The data output from 2c is sampled by a five-point sampling unit 230.
XOR gate 271c that takes the exclusive OR of the data output from flip-flop 272e and the data output from flip-flop 272e, and outputs the data as a data change detection signal A NOT gate 273c for inverting a data change detection signal output from the XOR gate 271c, and AND gates 274a and 274b for performing an AND operation on a signal output from the NOT gate 273c and a signal fed back from the output side;
The signal output from flip-flop 272a and AND
O for ORing with the signal output from gate 274a
An R gate 275a, an OR gate 275b for performing a logical sum of a signal output from the flip-flop 272d and a signal output from the AND gate 274b, a signal output from the OR gate 275a, and a signal output from the NOT gate 273b AND gate 274c for ANDing the signal output from output control unit 280 and the signal output from OR gate 275b and NOT gate 273a
An AND gate 274d for calculating the logical product of the signal output from the output control unit 280 and the signal output from the output control unit 280;
A flip-flop 272f that takes in the signal output from the gate 274c based on the clock supplied from the five-point sampling unit 230, and takes in the signal output from the AND gate 274d based on the clock supplied from the five-point sampling unit 230. Flip-flop 27
2g, an OR gate 275c that performs an OR operation on the data output from the flip-flop 272d and the data output from the flip-flop 272g, and the data output from the flip-flop 272a and the OR gate 275c.
AND gate 274e that takes a logical product with the signal output from the first and outputs it as a left-side duty deterioration detection signal
AND gate 274f for taking the logical product of the data output from the flip-flop 272d and the data output from the flip-flop 272f and outputting it as a right duty deterioration detection signal, and the left duty deterioration detection output from the AND gate 274e The flip-flop 272h for taking in the signal based on the clock supplied from the five-point sampling unit 230 and outputting it as a DDOWN signal, and the right-side duty deterioration detection signal output from the AND gate 274f is output to the five-point sampling unit 23.
0 based on the clock supplied from 0, and DUP
And a flip-flop 272i that outputs the signal as a signal.
The logical product of the signal output from the T-gate 273c and the signal output from the flip-flop 272f is obtained. In the AND gate 274b, the NOT gate 2
73c and flip-flop 272g
Is ANDed with the signal output from.

The output restricting section 280 shown in this configuration has the same configuration as that shown in FIG.

Flip-flop 2 in phase comparison section 250
The result of comparing data D2 and data D3 is taken into 52a, and 1 is set when the comparison result is different.

The result of comparison between data D3 and data D4 is taken into flip-flop 252c. If the comparison result is different, 1 is set.

The data D1 and the data D1 are applied to the flip-flop 272a in the duty deterioration detecting section 270.
If the result of comparison with 3 is taken in and the comparison result is different, 1 is set.

The result obtained by comparing data D3 and data D5 is taken into flip-flop 272d. If the comparison result is different, 1 is set.

In the XOR gate 271c,
Flip-flop 233 in 5-point sampling section 230
The result obtained by comparing the data fetched in step 1 with the data fetched by the clock one cycle before is output as a data change detection signal. A 1 is output as the data change detection signal when the taken data is different from the data one cycle before.

Flip-flops 252d, 252e, 2
Assuming that the initial states of 72f and 272g are all 0, when 1 is set to flip-flop 252a, 1 is set to flip-flop 252d, and when 1 is set again to flip-flop 252a, flip-flop 252a is set to 0. At the same time as the reset, the output of the AND gate 254c becomes 1, and the flip-flop 25
1 is set to 2f, and the UP output becomes 1.

As described above, when the data D2 fetched by the flip-flop 232 and the data D3 fetched by the flip-flop 233 are mismatched twice, it is determined that the margin of the setup time is small, and
As a P signal, 1 is output for only one pulse. as a result,
In the counter section 260, the counter is incremented to increase the margin of the setup time, and the clocks CK1 to CK selected by the clock selection section 220 are increased.
5 is incremented by one.

The flip-flops 252d and 252
If all initial states of e, 272f, and 272g are set to 0,
When 1 is set in the flip-flop 252c, 1 is set in the flip-flop 252e. When 1 is set in the flip-flop 252c again, the flip-flop 252e is reset to 0 and A
The output of the ND gate 254e becomes 1, the flip-flop 252g is set to 1, and the DOWN output becomes 1.

As described above, when the data D3 fetched by the flip-flop 233 and the data D4 fetched by the flip-flop 234 do not match twice, it is determined that the margin of the hold time is small, and DOW is not performed.
One pulse is output as one N signal. as a result,
In the counter section 260, the counter is decremented to increase the margin of the hold time, and the clocks CK1 to CK5 selected by the clock selection section 220 become 1
Decremented one by one.

Also, flip-flops 252d and 252
e, 272f, 272g, if all initial states are 0,
When 1 is set to the flip-flop 272a, 1 is set to the flip-flop 272f. Next, when 1 is set to the flip-flop 272d, the flip-flop 272f is reset to 0 and at the same time, the AN is reset.
The output of the D gate 274f becomes 1, the flip-flop 272i is set to 1, and the DUP output becomes 1.

In this operation, flip-flop 27
After 1 is set to 2a, flip-flop 272d
When the data change detection signal is set to 1 before is set to 1, the flip-flop 272f is reset and returns to the initial state.

As described above, after a mismatch occurs between the data D1 fetched by the flip-flop 231 and the data D3 fetched by the flip-flop 233, the data D1 fetched by the flip-flop 233
3 and the data D captured by the flip-flop 235
If the data of the flip-flop 233 does not change before the mismatch occurs with the data No. 5, it is determined that the data fetched by the flip-flop 233 is within the duty deterioration range, and the DUP signal is set to 1
Only one pulse is output. As a result, the counter 26
At 0, the counter value is incremented by an amount necessary for the data fetched by the flip-flop 233 to come out of the duty deterioration range, and the five clocks CK1 to CK5 selected by the clock selector 220 are set.
Is increased by an amount necessary for the data fetched by the flip-flop 233 to escape from the duty deterioration range.

Also, flip-flops 252d and 252
e, 272f, 272g, if all initial states are 0,
When 1 is set to the flip-flop 272d, 1 is set to the flip-flop 272g. Next, when 1 is set to the flip-flop 272a, the flip-flop 272g is reset to 0 and at the same time, AN is set.
The output of the D gate 274a becomes 1, the flip-flop 272h is set to 1, and the DDOWN output becomes 1.

In this operation, flip-flop 27
After 1 is set to 2d, flip-flop 272a
When the data change detection signal is set to 1 before is set to 1, the flip-flop 272g is reset and returns to the initial state.

As described above, after a mismatch occurs between the data D3 captured by the flip-flop 233 and the data D5 captured by the flip-flop 235, the data D3 captured by the flip-flop 231
1 and data D captured by the flip-flop 233
In the case where the data of the flip-flop 233 does not change before the mismatch with the data No. 3 is detected, it is determined that the data fetched by the flip-flop 233 is within the duty deterioration range, and one pulse is output as the DDOWN signal. Only 1 is output. As a result, the counter section 260 decrements the counter value by an amount necessary for the data fetched by the flip-flop 233 to come out of the duty deterioration range, and the five clocks CK1 to CK selected by the clock selection section 220.
5 is decremented by an amount necessary for the data fetched by the flip-flop 233 to come out of the duty deterioration range.

FIG. 17 is a timing chart for explaining the operation of the five-point sampling section 230 and the clock selection determining section 240 shown in FIGS. 9 and 16. In FIG. An example in which the output becomes 1 is shown.

As shown in FIG. 17, flip-flop 2
After both 72a and the flip-flop 272g become 1, the DDOWN output becomes 1.

The broken line shown in FIG. 17 indicates a case where there is no duty deterioration. In this case, the data D3
The DOWN output becomes 1 after two mismatches between the data and the data D4 are detected.

In the configuration example shown in FIG. 11, the pattern of the received data from which the duty deterioration can be detected is only a pattern such as "010" or "101" which changes twice in succession. In the present configuration example, as shown by the solid line in FIG.
Duty deterioration can be detected even with a received data pattern other than 1 ".

In the present embodiment, the output of the flip-flop 231 is the D1 of the duty deterioration detecting section 270.
, The output of the flip-flop 232 is input to D2 of the phase comparison unit 250, the output of the flip-flop 234 is input to D4 of the phase comparison unit 250, and the output of the flip-flop 235 is input to D5 of the duty deterioration detection unit 270. Although input, the output of the flip-flop 231 is input to D2 of the phase comparison unit 250, and the output of the flip-flop 232 is input to D1 of the duty deterioration detection unit 270.
, The output of the flip-flop 234 may be input to D5 of the duty deterioration detection unit 270, and the output of the flip-flop 235 may be input to D4 of the phase comparison unit 250.

(Third Embodiment) The circuit configuration is simplified by sharing the data input to the phase comparator 250 and the data input to the duty deterioration detector 270 shown in FIG. be able to.

FIG. 18 is a block diagram showing a high-speed data receiving circuit according to a third embodiment of the present invention.

As shown in FIG. 18, this embodiment is different from the one shown in FIG. 9 in that the data input to the phase comparison unit 350 and the data input to the duty deterioration detection unit 370 are three data in common. Accordingly, three clocks are selected in the clock selection unit 320, and the received data is captured by the three clocks output from the clock selection unit 320 as sampling means.

As a result, in the three-point sampling section 330, it is sufficient to provide only three flip-flops and buffers, and the circuit scale is reduced, and the circuit scale of the clock selection section 320 is also reduced.

FIG. 19 is a block diagram of the phase comparator 35 shown in FIG.
0, duty deterioration detecting section 370 and output regulating section 28
FIG. 2 is a circuit diagram illustrating a configuration example of a zero.

In this configuration example, as shown in FIG. 19, the data D1 and the data D2 have one common circuit, and the data D4 and the data D
Since the number of circuits common to the circuits 5 and 5 is one, the circuit scale is reduced. Similarly, the circuit scale is reduced as compared with that shown in FIG.

[0214]

As described above, in the present invention,
Sampling means for taking in the received data with three clocks having a predetermined phase difference, and comparing the three data taken in by the sampling means with each other, and comparing the data taken in with the clock with the most advanced phase with the center. If the data captured by the clock having the phase is different from the data captured, three clocks whose phases are delayed with respect to the currently selected three clocks are selected, and the clock captured by the clock with the most delayed phase is selected. Selecting means for selecting three clocks whose phases are advanced with respect to the currently selected three clocks, when the data acquired and the data captured by the clock having the central phase are different. The received data is captured by the selected three clocks, and the clock having the central phase is the output clock. And the data captured by the output clock is output as output data. Therefore, the phase of the clock is adjusted based on the data captured by the clock actually output as the output clock. That is, it is possible to correctly receive the received data without adjusting the amount of delay in the circuit or wiring.

Since the selection means selects three clocks and the sampling means takes in the received data repeatedly in a loop, the environment such as the power supply voltage and the temperature changes slowly, and the phase relationship between the received clock and the received data changes. Even if the value fluctuates, the received data can be correctly received.

Further, the selecting means selects only one clock and outputs three clocks of the selected clock and two clocks obtained by delaying the selected clock by different delay amounts. Even in the case where the data captured by the clock with the most advanced phase and the data captured by the clock with the central phase are different, the clock delayed in phase from the currently selected clock is selected. If the data captured by the clock with the latest phase is different from the data captured by the clock having the central phase, the clock with the phase advanced from the currently selected clock is selected. In the sampling means, the clock selected by the selection means and the selected clock are delayed by different delay amounts. The received data is taken in by three clocks, two clocks delayed by a delay, a clock having a central phase is outputted as an output clock, and the data taken in by the output clock is outputted as output data. In addition to the effects similar to the above, there is an effect that the phase difference between the three clocks can be arbitrarily set.

As described above, according to the present invention, the sampling means for receiving the received data with five clocks having a predetermined phase difference, and the central phase among the five data captured by the sampling means Duty degradation by comparing data captured with a clock with data that is captured with a clock advanced in phase from the center phase and data captured with a clock that is delayed in phase from the center phase Judgment is made as to whether or not the clock has entered the duty-deteriorating section. If the clock has entered the duty-deteriorating section, five clocks or phases whose phases have advanced by as much as necessary to escape from the duty-deteriorating section with respect to the currently selected five clocks Selecting means for selecting the five delayed clocks; Received data is captured by the selected five clocks, a clock having a central phase is output as an output clock, and the data captured by the output clock is output as output data. Even when the duty is deteriorated, the reception data can be correctly received.

The five data taken in by the sampling means are compared with each other, and when the data taken in by the clock having the center phase is different from the data taken in by the clock having a phase advanced from that. Selects five clocks delayed in phase with respect to the currently selected five clocks, and selects the data captured by the clock having the center phase and the clock captured by the clock delayed in phase. When the data is different from the currently selected five clocks, five clocks whose phases are advanced with respect to the currently selected five clocks are selected, and the sampling data is received by the selected five clocks, and the central phase is changed. A clock having the output is output as an output clock,
Since the data fetched by the output clock is output as output data, it is possible to correctly receive the received data in a state where the setup time and the hold time have a sufficient margin.

Further, since the comparison by the selection means is performed based on the data taken in by the clock actually selected by the sampling means,
Received data can be correctly received without adjusting the amount of delay in a circuit or wiring.

Since the selection means selects five clocks and the sampling means fetches received data repeatedly in a loop, the environment such as the power supply voltage and temperature changes slowly, and the phase relationship between the received clock and the received data changes. Even if the value fluctuates, the received data can be correctly received.

Further, sampling means for taking in the received data with five clocks having a predetermined phase difference, and five data taken in by the sampling means are compared with each other and taken in with a clock having a central phase. If the acquired data is different from the data acquired by the clock with a phase leading it, five clocks that are delayed in phase from the currently selected five clocks are selected and have a center phase. If the data fetched by the clock is different from the data fetched by the clock delayed in phase therefrom, five clocks whose phases are advanced with respect to the currently selected five clocks are selected, and If it is detected that the data captured by the clock having the center phase is included in the duty deterioration range, There is provided a selection means for selecting five clocks such that the data comes out of the duty deterioration range. In the sampling means, received data is taken in at the selected five clocks, and a clock having a central phase is used as an output clock. In a configuration in which data that is output and captured by the output clock is output as output data, received data can be accurately received even when the reception duty is deteriorated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a high-speed data receiving circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a clock selection unit illustrated in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration example of a phase comparison section illustrated in FIG. 1;

FIG. 4 is a timing chart for explaining an operation of the high-speed data receiving circuit shown in FIGS. 1 to 3;

FIG. 5 is a timing chart for explaining operations of the three-point sampling unit and the clock selection determining unit shown in FIGS. 1 and 3;

FIG. 6 is a block diagram showing another configuration example of the clock selection unit shown in FIG. 1;

FIG. 7 is a block diagram showing another configuration example of the clock selection unit shown in FIG. 1;

8 is a timing chart for explaining an operation when the duty of the received data is deteriorated due to a delay in rising of the received data in the high-speed data receiving circuit shown in FIG. 1;

FIG. 9 is a block diagram illustrating a high-speed data receiving circuit according to a second embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration example of a clock selection unit illustrated in FIG. 9;

11 is a circuit diagram illustrating a configuration example of a phase comparison unit, a duty deterioration detection unit, and an output control unit illustrated in FIG. 9;

FIG. 12 is a timing chart for explaining the operation of the high-speed data receiving circuit shown in FIGS. 9 to 11;

FIG. 13 is a timing chart for explaining operations of the five-point sampling unit and the clock selection determining unit shown in FIGS. 9 and 11;

FIG. 14 is a timing chart for explaining operations of the five-point sampling unit and the clock selection determining unit shown in FIGS. 9 and 11;

FIG. 15 is a block diagram illustrating another configuration example of the clock selection unit illustrated in FIG. 9;

FIG. 16 is a circuit diagram illustrating another configuration example of the phase comparison unit, the duty deterioration detection unit, and the output control unit illustrated in FIG. 9;

FIG. 17 is a timing chart for explaining operations of the five-point sampling unit and the clock selection determining unit shown in FIGS. 9 and 16;

FIG. 18 is a block diagram illustrating a high-speed data receiving circuit according to a third embodiment of the present invention.

19 is a circuit diagram illustrating a configuration example of a phase comparison unit, a duty deterioration detection unit, and an output control unit illustrated in FIG. 18;

FIG. 20 is a block diagram illustrating a configuration example of a conventional data receiving circuit.

[Explanation of symbols]

Reference Signs List 10 polyphase clock generation unit 20, 220, 320 clock selection unit 21-27, 221-225, 226 selector 28, 29, 227a-227d delay unit 30, 330 three-point sampling unit 31-33, 52a, 52b, 54a, 54b, 56a
~ 56d, 231 ~ 235,252a ~ 252g, 27
2a to 272i, 283a to 283f Flip-flops 34 to 36, 236, 237a to 237c, 238
Buffers 40, 240, 340 Clock selection determination units 50, 250, 350 Phase comparison units 51a, 51b, 251a to 251d, 271a to 27
1c XOR gates 53a, 53b, 254a to 254d, 274a to 27
4f AND gate 55,281 OR gate 57,275,275a, 275b, 282 NOR
Gate 60, 260 Counter unit 230 Five-point sampling unit 253, 253a, 253b, 273a to 273c
NOT gates 270, 370 Duty deterioration detector 280 Output regulator

Claims (23)

[Claims] 1. A high-speed data receiving circuit that captures received data with a clock that satisfies a predetermined setup time and a hold time, a sampling unit that captures the received data with three clocks having a predetermined phase difference. Selecting means for comparing the three data fetched by the sampling means with each other and outputting the three clocks based on the result of the comparison; and among the three clocks inputted to the sampling means, A high-speed data receiving circuit, wherein a clock having a central phase is output as an output clock, and data captured by the output clock is output as output data. 2. The high-speed data receiving circuit according to claim 1, wherein the output of the three clocks in the selection unit and the reception of reception data in the sampling unit are performed by:
A high-speed data receiving circuit that is repeatedly performed by a loop. 3. The high-speed data receiving circuit according to claim 2, wherein said selecting means compares the three data with each other, and as a result, sets the data captured by the clock with the most advanced phase and said central phase. In the case where the data captured by the clock having a different phase, the phases of the three output clocks are respectively delayed, and the data captured by the clock with the most delayed phase and the data captured by the clock having the central phase A high-speed data receiving circuit for advancing the phases of the three clocks to be output, respectively. 4. The high-speed data receiving circuit according to claim 3, further comprising a multi-phase clock generating means for multi-phase receiving clock, wherein said selecting means generates said multi-phase clock based on said comparison result. A high-speed data receiving circuit for selecting and outputting three clocks from a plurality of clocks generated by the means. 5. The high-speed data receiving circuit according to claim 3, further comprising: a multi-phase clock generating unit configured to multi-phase a received clock, wherein the selecting unit generates the multi-phase clock based on the comparison result. A high-speed data receiving circuit which selects one clock from a plurality of clocks generated by the means, and outputs the selected one clock as three clocks with a predetermined phase difference. 6. The high-speed data receiving circuit according to claim 4, wherein said selecting means compares the three data fetched by said sampling means with each other, and fetches the data fetched by a clock having the most advanced phase. And when the data captured by the clock having the central phase is different, a selection signal for delaying the phases of the selected three clocks is output,
A clock that outputs a selection signal for advancing the phases of three clocks to be selected, respectively, when the data captured by the clock with the most delayed phase is different from the data captured by the clock having the central phase. A selection determination unit; and a clock selection unit that selects and outputs three clocks among a plurality of clocks generated by the multi-phase clock generation unit based on a selection signal output from the clock selection determination unit. A high-speed data receiving circuit, comprising: 7. The high-speed data receiving circuit according to claim 5, wherein the selecting unit compares the three data taken in by the sampling unit with each other, and the data taken in by a clock having the most advanced phase. And when the data captured by the clock having the central phase is different, a selection signal for delaying the phases of the selected three clocks is output,
A clock that outputs a selection signal for advancing the phases of three clocks to be selected, respectively, when the data captured by the clock with the most delayed phase is different from the data captured by the clock having the central phase. A selection determining unit; selecting one of the plurality of clocks generated by the multi-phase clock generating unit based on the selection signal output from the clock selection determining unit; A high-speed data receiving circuit, comprising: a clock selecting unit for providing a predetermined phase difference and outputting three clocks. 8. The high-speed data receiving circuit according to claim 7, wherein the clock selection unit generates a plurality of clocks generated by the multi-phase clock generation unit based on a selection signal output from the clock selection determination unit. And a delay unit that delays the clock selected by the selector by different delay amounts and outputs the two clocks, the selector selecting one of the clocks selected by the selector. A high-speed data receiving circuit for outputting a clock and two clocks output from the delay means as the three clocks. 9. The high-speed data receiving circuit according to claim 6, wherein the clock selection determining unit compares the three data captured by the sampling means with each other, and captures the three data with a clock having the most advanced phase. If the received data is different from the data captured by the clock having the central phase, an UP signal is output, and the data captured by the clock with the latest phase and the clock captured by the clock having the central phase are captured. If the received data is different, the phase comparator outputs a DOWN signal, and increments the count value when the UP signal is output from the phase comparator, and decrements the count value when the DOWN signal is output. And a counter unit that outputs the count value as the selection signal. Wherein when the count value is incremented, the phases of the three clocks to be selected are respectively delayed, and when the count value in the counter section is decremented, the phases of the three clocks to be selected are advanced respectively. Receiver circuit. 10. The high-speed data receiving circuit according to claim 7, wherein the clock selection determining unit compares the three data captured by the sampling unit with each other, and determines a clock having the most advanced phase. If the data fetched at is different from the data fetched by the clock having the center phase, an UP signal is output, and the data fetched by the clock with the most delayed phase has the center phase. A phase comparator that outputs a DOWN signal when the data captured by the clock is different, and increments a count value when an UP signal is output from the phase comparator and counts when a DOWN signal is output A counter section for decrementing a value and outputting the count value as the selection signal, wherein the clock selection section The high-speed data is characterized in that when the count value in the counter section is incremented, the phase of one clock to be selected is delayed, and when the count value in the counter section is decremented, the phase of one clock to be selected is advanced. Receiver circuit. 11. The high-speed data receiving circuit according to claim 9, wherein the phase comparator, when outputting the UP signal or the DOWN signal, is determined in advance after outputting the UP signal or the DOWN signal. The UP signal or the DO signal
A high-speed data receiving circuit that does not output a WN signal. 12. A high-speed data receiving circuit for receiving received data with a clock that satisfies a predetermined setup time and a hold time, a sampling means for capturing the received data with five clocks having a predetermined phase difference. The five data fetched by the sampling means are compared with each other, and it is detected whether the data fetched by the clock having the central phase among the five data is included in the duty deterioration range. Selecting means for outputting the five clocks based on the comparison result and the detection result, wherein a clock having a central phase among the five clocks input to the sampling means is output as an output clock; Data captured by the output clock is output as output data A high-speed data receiving circuit. 13. The high-speed data receiving circuit according to claim 12, wherein the output of the five clocks in the selection unit and the reception of reception data in the sampling unit are performed by:
A high-speed data receiving circuit that is repeatedly performed by a loop. 14. The high-speed data receiving circuit according to claim 13, wherein said selection means compares the five data with each other, and as a result, the data fetched by a clock having a center phase and the phase of a data fetched by a clock having a central phase If the data captured by the advanced clock is different, the phases of the five clocks to be output are respectively delayed, and the data captured by the clock having the central phase and the clock captured by the clock having a phase delayed from the clock are delayed. If the data is different, output 5
A high-speed data receiving circuit that advances the phases of two clocks. 15. The high-speed data receiving circuit according to claim 14, wherein the selecting unit detects that data taken in by the clock having the central phase is included in a duty deterioration range. A high-speed data receiving circuit for outputting a clock such that the data comes out of the duty deterioration range. 16. The high-speed data receiving circuit according to claim 15, wherein said selecting means detects that data taken in by said clock having said central phase is included in a duty deterioration range. A high-speed data receiving circuit that outputs a clock that changes the phase of five output clocks so that the data comes out of the duty deterioration range. 17. The high-speed data receiving circuit according to claim 16, further comprising a multi-phase clock generating means for multi-phase receiving clocks, wherein said selecting means generates said multi-phase clock based on said comparison result. A high-speed data receiving circuit for selecting and outputting five clocks from a plurality of clocks generated by the means. 18. The high-speed data receiving circuit according to claim 16, further comprising a multi-phase clock generating means for multi-phase receiving clocks, wherein said selecting means generates said multi-phase clock based on said comparison result. A high-speed data receiving circuit which selects one clock from a plurality of clocks generated by the means, and outputs the selected one clock as five clocks with a predetermined phase difference. 19. The high-speed data receiving circuit according to claim 17, wherein said selecting means compares the five data fetched by said sampling means with each other and fetches them with a clock having said central phase. If the data is different from the data captured by the clock with a phase leading it, a selection signal for delaying the phase of each of the selected five clocks is output, and the data is captured by the clock having the central phase. If the received data is different from the data captured by the clock delayed in phase, a selection signal for advancing the phase of each of the selected five clocks is output, and the central phase of the five data is output. Detects whether the data captured by the clock having A clock selection determining unit that outputs a selection signal for selecting a clock that causes the data to fall out of the duty deterioration range when detecting that the data fetched by the clock included in the clock falls within the duty deterioration range. And a clock selection unit that selects and outputs five clocks among a plurality of clocks generated by the multi-phase clock generation unit based on a selection signal output from the clock selection determination unit. Characterized high-speed data receiving circuit. 20. The high-speed data receiving circuit according to claim 18, wherein said selecting means compares the five data taken in by said sampling means with each other, and takes in with a clock having said central phase. If the data is different from the data captured by the clock with a phase leading it, a selection signal for delaying the phase of each of the selected five clocks is output, and the data is captured by the clock having the central phase. If the received data is different from the data captured by the clock delayed in phase, a selection signal for advancing the phase of each of the selected five clocks is output, and the central phase of the five data is output. Detects whether the data captured by the clock having A clock selection determining unit that outputs a selection signal for selecting a clock that causes the data to fall out of the duty deterioration range when detecting that the data fetched by the clock included in the clock falls within the duty deterioration range. And selecting one of the plurality of clocks generated by the multi-phase clock generating means based on the selection signal output from the clock selection determining unit, and selecting the selected one of the clocks in advance. A high-speed data receiving circuit, comprising: a clock selecting unit that provides a phase difference and outputs five clocks. 21. The high-speed data receiving circuit according to claim 19, wherein the clock selection determining unit is configured to output data captured by a clock having a central phase among five data captured by the sampling unit. And the data captured by the clock with a phase advanced from the central phase and the data captured by the clock with a phase delayed from the central phase are compared with each other, and are captured by the clock having the central phase. If the acquired data is different from the data acquired by the clock having the advanced phase, an UP signal is output, and the data acquired by the clock having the center phase and the data acquired by the clock having the delayed phase are outputted. If the data is different, DOWN
A phase comparison unit that outputs a signal, and among the five pieces of data captured by the sampling means, data captured by a clock having a central phase and captured by a clock advanced in phase from the central phase. Data and the data captured by the clock delayed in phase from the center phase are compared with each other to determine whether the data captured by the clock having the center phase is included in the duty deterioration range. Detect
A duty deterioration detection unit that outputs a DUP signal or a DDOWN signal when detecting that data taken in by the clock having the center phase is included in the duty deterioration range; and an UP signal from the phase comparison unit. When the DOWN signal is output, the count value is incremented, when the DOWN signal is output, the count value is decremented, and when the DUP signal is output from the duty deterioration detection unit, the count value is captured by the clock having the central phase. The count value is incremented so that the acquired data comes out of the duty deterioration range, and when the DDOWN signal is output, the data taken in by the clock having the central phase goes out of the duty deterioration range. Decrement the count value and change the count value And a counter section that outputs the selection signal. When the count value in the counter section is incremented, the clock selection section delays the phase of each of the selected five clocks, and decrements the count value in the counter section. A high-speed data receiving circuit for advancing the phases of five clocks to be selected, respectively. 22. The high-speed data receiving circuit according to claim 20, wherein the clock selection determining unit is configured to output the data captured by a clock having a central phase among the five data captured by the sampling unit. And the data captured by the clock with a phase advanced from the central phase and the data captured by the clock with a phase delayed from the central phase are compared with each other, and captured by the clock having the central phase. If the acquired data is different from the data acquired by the clock having the advanced phase, an UP signal is output, and the data acquired by the clock having the center phase and the data acquired by the clock having the delayed phase are outputted. If the data is different, DOWN
A phase comparison unit that outputs a signal; of the five data captured by the sampling means, data captured by a clock having a central phase and captured by a clock advanced in phase from the central phase Data and the data captured by the clock delayed in phase from the center phase are compared with each other to determine whether the data captured by the clock having the center phase is included in the duty deterioration range. Detect
A duty deterioration detection unit that outputs a DUP signal or a DDOWN signal when detecting that data taken in by the clock having the center phase is included in the duty deterioration range; and an UP signal from the phase comparison unit. When the DOWN signal is output, the count value is incremented, when the DOWN signal is output, the count value is decremented, and when the DUP signal is output from the duty deterioration detection unit, the count value is captured by the clock having the central phase. The count value is incremented so that the acquired data comes out of the duty deterioration range, and when the DDOWN signal is output, the data taken in by the clock having the central phase goes out of the duty deterioration range. Decrement the count value and change the count value A counter section that outputs the selection signal, wherein the clock selection section delays the phase of one clock to be selected when the count value in the counter section is incremented, and the count value in the counter section is decremented. A high-speed data receiving circuit for advancing the phase of one clock to be selected. 23. The high-speed data receiving circuit according to claim 21 or 22, wherein the clock selection deciding unit is configured to determine whether or not the clock signal is determined by the phase comparing unit.
When the P signal or the DOWN signal is output, or when the DUP signal or the DDOWN signal is output from the duty deterioration detection unit, a predetermined value after the output of the UP signal, the DOWN signal, the DUP signal, or the DDOWN signal. The period is the UP signal or the D signal.
OWN signal or the DUP signal or the DDOWN signal
A high-speed data receiving circuit comprising an output restricting unit that prevents a signal from being output from the phase comparing unit or the duty deterioration detecting unit.