JP2001068992A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high operating speed for a semiconductor integrated circuit with low power consumption. SOLUTION: A CMOS circuit 108 uses a power level LVDD resulting from stepping down a power level VDD by a power level drop circuit 106 for a power supply level, the power supply level VDD is given to a back gate of a PMOS 109 of a CMOS inverter circuit e.g. being a component of the CMOS circuit 108, and the impurity concentration of a base or a well layer forming the PMOS 109 receiving a bias is reduced so as to adjust a threshold voltage by taking increase in an absolute value of the threshold voltage Vtp of the PMOS 109 due to the back gate effect caused by giving the power supply level VDD to the back gate of the PMOS 109 into account. The adjusted voltage is the same as a threshold voltage of the PMOS receiving no bias for the operation of the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a P-type MOS capable of operating at high speed with low power consumption.
The present invention relates to a semiconductor integrated circuit having a CMOS circuit composed of a transistor and an N-type MOS transistor.

[0002]

2. Description of the Related Art In recent years, portable information devices such as PHS (Personal Handy Phone System) and laptop personal computers have become widespread. One of the components of the portable information device is a semiconductor integrated circuit (hereinafter, referred to as an IC). In such an IC, it is strongly required to reduce power consumption without lowering the operation speed.

A CMOS circuit is composed of a P-type MOS transistor (hereinafter, referred to as PMOS) and an N-type MOS transistor (hereinafter, referred to as NMOS), and operates these PMOS and NMOS in a complementary manner.
It is known as a circuit that operates at high speed with low power consumption. Therefore, I, which is one of the components of the portable information device described above,
CMOS circuits are widely used for C.

The power consumption of the CMOS circuit includes dynamic power consumption due to charging / discharging of a load capacitance during a switching operation and static power consumption due to a subthreshold leakage current. Among them, the dynamic power consumption consumes a large amount of power in proportion to the square of the power supply voltage VDD. Therefore, it is effective to lower the power supply voltage to reduce the power consumption. Therefore, there is an increasing demand for an IC used in a portable information device to operate at a low power supply voltage.

[0005]

On the other hand, as generally known, the operating speed of a CMOS circuit decreases as the power supply voltage decreases. For this reason, in order to prevent the operating speed of the CMOS circuit from deteriorating, it is necessary to lower the threshold voltage of the MOS transistor in conjunction with the lowering of the power supply voltage. However, when the threshold voltage is lowered, the sub-threshold leakage current increases exponentially. Since the static power consumption is proportional to the sub-threshold leakage current, if the threshold voltage of the MOS transistor is lowered in conjunction with the progress of the power supply voltage reduction, the static power due to the sub-threshold leakage current which was not so large conventionally is reduced. The increase in power consumption becomes remarkable. For this reason, it has become extremely difficult to achieve both low power consumption and high speed operation. For such issues,
For example, it is described in JP-A-11-191611.

An object of the present invention is to provide a semiconductor integrated circuit which can operate at high speed with low power consumption.

[0007]

Means for Solving the Problems To achieve the above object, a typical one of the inventions disclosed in the present application will be described. A semiconductor integrated circuit according to the present invention is supplied with a first power supply potential. A first power supply line, a first power supply potential supplied thereto, a power supply voltage lowering circuit for lowering the first power supply potential to generate a second power supply potential, and a second power supply voltage lowering circuit generated by the power supply potential lowering circuit. A second power supply line to which a third power supply potential lower than the second power supply potential is supplied; a second power supply line to which a third power supply potential lower than the second power supply potential is supplied; and a second power supply line and a third power supply line. A CMOS circuit including a P-type MOS transistor and an N-type MOS transistor, wherein a first power supply potential is supplied to a back gate of the P-type MOS transistor.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 1 shows an IC including a CMOS circuit that includes a PMOS and an NMOS and that operates the PMOS and the NMOS in a complementary manner.

In FIG. 1, an IC includes a power supply line 101 (hereinafter referred to as a VDD line) to which a power supply potential VDD is supplied and a power supply potential LVDD obtained by lowering a power supply potential VDD generated by a power supply potential lowering circuit 106. A power supply line 102 (hereinafter, referred to as an LVDD line) is supplied, and a power supply line 103 (hereinafter, referred to as a VSS line) to which a power supply potential VSS lower than the power supply potential LVDD is supplied.

Here, the pad 104 is connected to the power supply potential VDD.
The pad 105 is a terminal provided on the semiconductor substrate for supplying the power supply potential VSS from the outside of the IC.

In FIG. 1, a power supply potential lowering circuit 106 is connected between a VDD line 101 and a VSS line 103, and a reference potential V generated by a reference potential generating circuit 107.
REF has been input. The power supply potential drop circuit 106 is supplied with the power supply potential VDD from the VDD line 101,
A power supply potential VSS is supplied from the SS line 103. The power supply potential lowering circuit 106 lowers the power supply potential VDD supplied from the VDD line 101 to generate a power supply potential LVDD corresponding to the reference potential VREF. Power supply potential drop circuit 10
6, the power supply potential LVDD generated from
It is supplied to the LVDD line 102. Further, the power supply potential dropping circuit 106 is connected to the reference potential VREF and the LVDD line 102.
The power supply potential VDD is compared with the power supply potential LVDD, and the power supply potential VDD is reduced to a constant value so that the power supply potential LVDD becomes the reference potential VREF.

FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of the power supply potential lowering circuit 106. Hereinafter, the configuration and operation will be briefly described. As shown in FIG. 2, the power supply potential lowering circuit 106 is connected to the reference potential VREF and the LVDD line 1.
A power supply potential VDD, and a power supply potential adjustment circuit 220 that lowers the power supply potential VDD to a constant value based on the comparison result of the comparison circuit 200 so that the power supply potential LVDD becomes the reference potential VREF. Consists of

The comparison circuit 200 includes a PMOS 201, a PM
OS 202, NMOS 203, NMOS 204, NMO
It consists of S205. The back gate of each MOS is connected to the source.

The PMOS 201 is connected between the power supply potential VDD and the node N2, and its gate is connected to the gate of the PMOS 202. The PMOS 202 has a power supply potential VDD.
And the node N3, the gate of which is connected to P
It is connected to the MOS 201 and to the node N3.

The NMOS 203 has a node N2 and a node N4.
, And the gate thereof is supplied with the reference potential VREF.

The NMOS 204 has a node N3 and a node N4.
Is connected between. Also, the gate is LVDD
The power supply potential LVDD is supplied to the line 102.

The NMOS 205 is connected to the node N4 and the power supply potential V
The power supply potential VDD is applied to the gate of the gate.

The comparison circuit 200 includes PMOSs 201 and 20
2 is a current mirror differential amplifier having a load of 2. When the power supply potential LVDD becomes lower than the reference potential VREF, the potential of the node N2 is reduced, and the power supply potential LVDD becomes the reference potential VVDD.
This is a circuit that raises the potential of the node N3 when it becomes higher than REF.

The power supply potential adjusting circuit 220 is a PMOS 206
It is composed of The back gate of the PMOS 206 is connected to the source.

The PMOS 206 is connected between the power supply potential VDD and the power supply potential LVDD, and has its gate connected to the node N2.

The power supply potential adjusting circuit 220 includes a comparing circuit 20
0, that is, by the potential of the node N2, PM
A circuit for generating a power supply potential LVDD in which the power supply potential VDD is lowered by changing the conductivity of the OS 206. The power supply potential LVDD is set to the reference potential VREF by performing a series of feedback operations such as changing the power supply potential LVDD.

Next, referring to FIG.
07 is connected between the VDD line 101 and the VSS line 103. The reference potential generating circuit 107 has a VDD line 1
01 is supplied with the power supply potential VDD, and the VSS line 1
03 supplies a power supply potential VSS. The reference potential generation circuit 107 outputs the reference potential VREF to the power supply potential drop circuit 106.

FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of reference potential generating circuit 107. Hereinafter, the configuration and operation will be briefly described. Reference potential generation circuit 107
Are PMOS 301, PMOS 302, NMOS 30
3, NMOS 304, PMOS 305, NMOS 30
6, an NMOS 307, a resistor R1, and a resistor R2. The back gate of each MOS is connected to the source.

The PMOS 301 is connected between the power supply potential VDD and the node N5, and its gate is connected to the PMOS3.
02 is connected to the gate. The PMOS 302 is connected between the power supply potential VDD and the node N6, and its gate is connected to the gate of the PMOS 301 and the node N6.

The NMOS 303 is connected to the node N5 and the power supply potential V
SS, and the gate thereof is connected to the node N7.
It is connected to the.

The NMOS 304 includes a node N6 and a node N7.
And its gate is connected to the node N5.

The resistor R1 is connected between the node N7 and the power supply potential VSS.

The PMOS 305 is connected between the power supply potential VDD and the node N8, and its gate is connected to the node N6.
It is connected to the.

The NMOS 306 includes a node N8 and a node N9.
And its gate is connected to the node N8. The NMOS 307 is connected between the node N9 and the power supply potential VSS, and its gate is connected to the node N9.
9 is connected.

The resistor R2 is connected between the power supply potential VDD and the node N8.

The reference potential generation circuit 107 is a reference potential generation circuit of a threshold voltage reference type, and generates the reference potential VREF based on the threshold voltage Vt of the NMOS 303.

Next, referring to FIG.
Is connected between the LVDD line 102 and the VSS line 103. The CMOS circuit 108 includes the LVDD line 102
The power supply potential LVDD is supplied from the
3, the power supply potential VSS is supplied. The CMOS circuit 108 includes a PMOS and an NMOS,
This is a circuit for operating these PMOS and NMOS complementarily. As shown in FIG. 1, the CMOS circuit 108 has, for example, a CMOS inverter circuit including a PMOS 109 and an NMOS 110. Although not shown, CM
The OS circuit 108 includes other CMOS inverter circuits and CMOS NAND circuits, and various changes can be made without particular limitation as long as they have a CMOS configuration. Hereinafter, for simplification of the drawings and description,
The description will proceed with the CMOS inverter circuit shown in FIG. 1 as an example.

In FIG. 1, the source of the PMOS 109 is connected to the LVDD line 102, the power supply potential LVDD is supplied, and the source of the NMOS 110 is the VSS line 10.
3 and a power supply potential VSS is supplied. The drains of the PMOS 109 and the NMOS 110 are commonly connected, and an output signal line for outputting an output signal of the CMOS inverter circuit is connected to the node N1. Here, the output signal line is connected to, for example, an input signal wiring of another logic circuit or an external output terminal. The gates of the PMOS 109 and the NMOS 110 are commonly connected, and these gates are connected to, for example, an output signal wiring of another logic circuit or a signal wiring from an external input terminal.

In FIG. 1, the VDD line 101 is connected to a substrate or a well layer (not shown) on which the PMOS 109 is formed, and the VDD line 101 is connected to the substrate or the well layer.
01 from the power supply potential VDD,
The power supply potential VDD is supplied to the back gate of the OS 109.

In FIG. 1, a VSS line 1 is formed on a substrate or a well layer (not shown) on which the NMOS 110 is formed.
03 and VS is connected to this substrate or well layer.
When the power supply potential VSS is supplied from the S line 103, the power supply potential VSS is supplied to the back gate of the NMOS 110.

Next, the operation of the IC shown in FIG. 1 will be described below. The pad 104 has a power supply potential VD
For example, 3.3 V is applied as D, and the pad 105 is externally applied with, for example, a ground potential as the power supply potential VSS.

The reference potential generating circuit 107 supplies, for example, 2.0 V to the power supply potential dropping circuit 106 as the reference potential VREF. As described above, the power supply potential lowering circuit 106 lowers the power supply potential VDD and supplies the power supply potential LV to the LVDD line 102 so that the power supply potential LVDD becomes 2.0 V.
Supply DD.

The CMOS circuit 108 operates at a power supply potential LVDD of 2.0 V. Here, 3.3 V is supplied from the VDD line 101 to the back gate of the PMOS 109 of the CMOS circuit.

Here, it is generally known as the back gate effect that the threshold voltage Vt of the MOS changes depending on the back gate-source voltage Vbs. As a back gate effect in the case of a PMOS, the threshold voltage Vt increases in the negative direction as Vbs increases in the positive direction, for example, 0 to 3 V. In other words, since the threshold voltage of the PMOS is generally a negative value,
As Vbs increases in the positive direction, the absolute value of the threshold voltage of the PMOS increases. Further, as a back gate effect in the case of NMOS, Vbs is, for example, 0
The threshold voltage Vt increases in the positive direction as it increases in the negative direction such as -3V. In other words, since the threshold voltage of the NMOS is generally a positive value,
As bs increases in the negative direction, the absolute value of the threshold voltage of the NMOS increases.

For example, when a bias of Vbs = 1.3V is applied to a PMOS whose absolute value of the threshold voltage Vtp is 0.53V without applying a bias of Vbs = 0V, the threshold voltage Vtp of the PMOS is increased. Has an absolute value of 0.88
V. Here, the absolute value of the threshold voltage Vtp when a bias of Vbs = 1.3 V is applied is 0.5
When it is desired to set 3 V, the impurity concentration of the substrate or well layer where the PMOS is formed is higher than the impurity concentration where the PMOS whose absolute value of the threshold voltage at Vbs = 0 V is 0.53 V is formed. Adjust it by lowering it.

Therefore, in this embodiment, Vb
PMOS 109 biased such that s = 1.3 V
In order to set the absolute value of the threshold voltage Vtp to be, for example, 0.53 V, the PMOS 109 is formed in consideration of an increase in the absolute value of the threshold voltage Vtp due to the back gate effect. By setting the impurity concentration of the substrate or well layer lower than the impurity concentration of the substrate or well layer where the PMOS 109 is formed when the absolute value of the threshold voltage at Vbs = 0 V is 0.53 V, Is adjusted, and the threshold voltage Vt of the PMOS 109 is biased such that Vbs = 1.3 V.
The operation is performed by setting the absolute value of p to be 0.53 V.

In this embodiment, the NMOS 1
Reference numeral 10 denotes a state where Vbs = 0 V because both the source and the back gate are connected to the ground potential.
The operation is performed with the absolute value of the threshold voltage Vtn of 0 set to, for example, 0.45 V.

The reason why the IC of the present invention operates at high speed will be described below.

The PMOS 109 having Vbs = 1.3V and the absolute value of the threshold voltage Vtp being 0.53V, and Vbs = 0V
NMO whose absolute value of the threshold voltage Vtn is 0.45 V
S110 and a biased inverter circuit according to the present embodiment, and a threshold voltage Vt at Vbs = 0V
PMOS whose absolute value of p is 0.53 V and Vbs = 0 V
NMO whose absolute value of the threshold voltage Vtn is 0.45 V
The rising and falling characteristics of the inverter circuit which does not apply a bias consisting of S and S are compared. Here, in both the inverter circuit that applies a bias and the inverter circuit that does not apply a bias in the present embodiment, P
The channel width W of the MOS is 5.0 μm, the channel length L is 0.35 μm, and the channel width W of the NMOS is 2.0 μm.
μm and the channel length L are 0.35 μm, and other conditions are the same except that the impurity concentration of the substrate or well layer on which the PMOS is formed is different.

FIG. 4 is a diagram showing the rising characteristics of the inverter circuit to which a bias is applied and the inverter circuit to which no bias is applied. In FIG. 4, the horizontal axis represents time, and the vertical axis represents voltage. As shown in FIG. 4, it can be understood that the biased inverter circuit according to the present embodiment rises faster than the non-biased inverter circuit.

FIG. 5 is a diagram showing fall characteristics of the inverter circuit to which a bias is applied and the inverter circuit to which no bias is applied. In FIG. 5, the horizontal axis represents time, and the vertical axis represents voltage. As shown in FIG. 5, it can be understood that the biased inverter circuit according to the present embodiment rises faster than the non-biased inverter circuit.

As described above, when the threshold voltage is the same, the inverter circuit with a bias as in this embodiment becomes faster with rising and falling than the inverter circuit without a bias, It can be said that it operates at high speed. It is presumed that the reason for this is that the depletion layer is extended and the junction capacitance is reduced because a reverse bias is applied to the pn junction between the back gate and the source. In the above description, a comparison was made with respect to a single inverter circuit. However, there are countless CMOS circuits in the CMOS circuit 108, and by applying the present invention, the CMOS circuit 108 can operate at a higher speed than the conventional one. It is easy to understand.

As described above, according to the present embodiment, the power supply potential obtained by lowering the external power supply potential by the power supply potential lowering circuit 106 is used as the power supply potential of the CMOS circuit 108. In addition to the low voltage operation, an external power supply potential is applied to the back gate of the PMOS 109 of the CMOS inverter circuit constituting the CMOS circuit 108, and the absolute value of the threshold voltage Vtp of the PMOS 109 is reduced by the back gate effect. In consideration of the increase in the threshold voltage, the threshold voltage is adjusted by lowering the impurity concentration of the substrate or the well layer on which the biased PMOS 109 is formed, and the threshold voltage of the PMOS when the bias is not applied is adjusted. Since it is set and operated to be the same as the value voltage,
High speed operation is possible with low power consumption.

In this embodiment, the power supply potential of the CMOS circuit 108 is changed because the power supply potential obtained by lowering the external power supply potential by the power supply potential dropping circuit 106 is used as the power supply potential of the CMOS circuit 108. In this case, the reference potential VREF applied to the power supply potential dropping circuit 106
Therefore, there is no need to change the external power supply potential, which is extremely excellent in versatility.

Further, in the present embodiment, Vbs =
To set the absolute value of the threshold voltage Vtp of the PMOS 109 at 1.3 V to be 0.53 V, Vbs
= The impurity concentration of the substrate or the well layer absolute value PMOS109 is formed when the 0.53V threshold voltage at 0V for example, when the 8 × 10 ¹⁸ cm ^{over 3,} Vbs =
The impurity concentration of the substrate or well layer on which the PMOS 109 having the absolute value of the threshold voltage Vtp at 1.3 V of 0.53 V is formed is lower than that, for example, 4.5 × 10 ¹⁸ cm ^−3.
Becomes Therefore, since the impurity concentration becomes a low value,
At the same threshold voltage, the sub-threshold leakage current is smaller when a bias is applied at Vbs = 1.3 V than when no bias is applied at Vbs = 0 V.

FIG. 6 is a device diagram of the CMOS inverter circuit in the IC of this embodiment shown in FIG. As shown in FIG. 6, in a CMOS structure, as generally known, a parasitic transistor indicated by a broken line is formed, which may cause a problem such as latch-up and device destruction. Was. However,
In this embodiment, since a reverse bias is applied to the pn junction between the back gate and the source of the PMOS 109, latch-up does not occur.

Second Embodiment FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG. 7, the same components as those in the first embodiment are denoted by the same reference numerals. Here, description of the same matters as in the first embodiment will be omitted. Hereinafter, matters different from the first embodiment in the second embodiment will be described.

As shown in FIG. 7, the IC has a power supply line 701 (hereinafter referred to as an HVSS line) to which a power supply potential HVSS generated from a reference potential generation circuit 702 is supplied. Here, the power supply potential HVSS is equal to the power supply potential LVD.
D and a potential higher than the power supply potential VSS.

FIG. 8 is a circuit diagram showing an example of a specific circuit configuration of reference potential generation circuit 702. Hereinafter, the configuration and operation will be briefly described. Reference potential generation circuit 702
Are PMOS801, PMOS802, NMOS80
3, NMOS 804, PMOS 805, NMOS 80
6, NMOS 807, NMOS 808, resistor R1, resistor R2. The back gate of each MOS is connected to the source.

The PMOS 801 is connected between the power supply potential VDD and the node N10, and has a gate connected to the PMOS 801.
802 is connected to the gate. The PMOS 802 is connected between the power supply potential VDD and the node N11,
Its gate is the gate of the PMOS 801 and the node N11.
It is connected to the.

The NMOS 803 is connected between the node N10 and the power supply potential VSS, and has a gate connected to the node N10.
12 is connected.

The NMOS 804 includes the nodes N11 and N
12 and the gate thereof is connected to the node N1.
Connected to 0.

The resistor R1 is connected between the node N12 and the power supply potential VSS.
Is connected between.

The PMOS 805 is connected between the power supply potential VDD and the node N13, and has a gate connected to the node N13.
11 is connected.

The NMOS 806 includes a node N13 and a node N
14 and its gate is connected to the node N1.
3 is connected. NMOS 807 is connected between nodes N14 and N15, and its gate is connected to node N14. The NMOS 808 is connected between the node N15 and the power supply potential VSS, and its gate is connected to the node N15.

The resistor R2 is connected between the power supply potential VDD and the node N13.
Is connected between.

The reference potential generation circuit 702 is a reference potential generation circuit of a threshold voltage reference type, and generates the reference potential VREF and the power supply potential HVSS based on the threshold voltage Vt of the NMOS 803.

As shown in FIG. 7, the source of the NMOS 704 constituting the CMOS inverter circuit is connected to the HVSS line 70.
1 is connected, and the power supply potential HVSS is supplied. The VSS line 103 is connected to a substrate or a well layer (not shown) on which the NMOS 704 is formed, and the power supply potential VSS is supplied. That is, the second embodiment is an embodiment in which a bias is also applied to the NMOS in addition to the first embodiment.

Here, in the present embodiment, HVSS
Is, for example, 0.5 V, and the others are the same as in the first embodiment.

In this embodiment, the NMOS 7004
Is 0 V applied to the back gate and 0.5 V applied to the source, so that Vbs = −0.5 V. As a result, as described above, the absolute value of the threshold voltage Vtn of the NMOS 704 at Vbs = −0.5V is N when Vbs = 0V.
It becomes larger than the absolute value of the threshold voltage Vtn of the MOS 704.

Here, in the present embodiment, as in the first embodiment, the absolute value of the threshold voltage Vtn of the NMOS 704 biased such that Vbs = −0.5 V is, for example, 0 In order to set the threshold voltage Vtn to .45 V, the impurity concentration of the substrate or well layer on which the NMOS 704 is formed is set to Vbs = 0 V in consideration of an increase in the absolute value of the threshold voltage Vtn due to the back gate effect. NM when the absolute value of the threshold voltage becomes 0.45 V
The threshold voltage is adjusted by lowering the impurity concentration of the substrate or the well layer on which the OS 704 is formed, and a biased NM such as Vbs = −0.5 V is used.
The absolute value of the threshold voltage Vtn of OS 704 is 0.45 V
It is set to operate.

This embodiment comprises a PMOS 109 having an absolute value of the threshold voltage Vtp of 0.53 V when Vbs = 1.3 V and an NMOS 704 having an absolute value of the threshold voltage Vtn of 0.45 V when Vbs = −0.5 V. A biased inverter circuit according to the above embodiment, and a PMOS and Vb having Vbs = 0 V and an absolute value of a threshold voltage Vtp of 0.53 V
The rising and falling characteristics of a non-biased inverter circuit composed of an NMOS with s = 0 V and an absolute value of the threshold voltage Vtn of 0.45 V will be compared. here,
In any of the inverter circuit applying a bias and the inverter circuit not applying a bias in the present embodiment, the channel width W of the PMOS is 5.0 μm, the channel length L is 0.35 μm, and the channel width W of the NMOS is 2 μm. 0.0 μm, the channel length L is 0.35 μm, and PM
Other conditions are the same except that the impurity concentration of the substrate or the well layer on which the OS is formed is different.

FIG. 9 is a diagram showing rise characteristics of an inverter circuit to which a bias is applied and an inverter circuit to which no bias is applied. In FIG. 9, the horizontal axis represents time, and the vertical axis represents voltage. As shown in FIG. 9, it can be understood that the biased inverter circuit according to the present embodiment rises faster than the biased inverter circuit.

FIG. 10 is a diagram showing fall characteristics of the inverter circuit to which a bias is applied and the inverter circuit to which no bias is applied. In FIG. 10, the horizontal axis represents time, and the vertical axis represents voltage. As shown in FIG. 10, it can be understood that the biased inverter circuit according to the present embodiment rises faster than the non-biased inverter circuit.

As described above, similarly to the first embodiment, if the threshold voltages are the same, the inverter circuit to which the bias is applied as in the present embodiment is the same as the inverter circuit to which no bias is applied. It can be said that the operation becomes faster with rising and falling, and that the operation is performed at high speed. Further, as in the present embodiment, further high-speed operation is desired by applying a bias to both the PMOS 109 and the NMOS 704.

Further, in this embodiment, in addition to the first embodiment, the NMOS 7 with Vbs = −0.5 V
Substrate or well on which NMOS 704 is formed when the absolute value of the threshold voltage at Vbs = 0 V is 0.45 V, in order to set the absolute value of threshold voltage Vtn at 04 to be 0.45 V The impurity concentration of the layer is, for example, 1.2 ×
When 10 ¹⁸ cm ^-3, the impurity concentration of the substrate or the well layer absolute value of the threshold voltage Vtn in Vbs = over 0.5V is NMOS704 of 0.45V is formed lower than, for example, 4. It becomes 5 × 10 ¹⁷ cm ⁻³ . Therefore, since the impurity concentration becomes a low value, as described above,
At the same threshold voltage, the sub-threshold leakage current is smaller when a bias is applied at Vbs = −0.5 V than when no bias is applied at Vbs = 0 V.
In this embodiment, the sub-threshold leakage current of both the PMOS 109 and the NMOS 704 is reduced. Therefore, it is desired to further reduce the sub-threshold leakage current as compared with the first embodiment.

FIG. 11 shows the IC of the present embodiment shown in FIG.
3 is a device diagram of a CMOS inverter circuit in FIG.
In the present embodiment, since a reverse bias is also applied to the pn junction between the back gate and the source of the NMOS 704, a further effect on latch-up is desired.

In the above description, the example in which the PMOS is operated by applying a bias and the example in which the PMOS and NMOS are operated by applying a bias have been described.
It is needless to say that the effect of the present invention can be obtained even if only the bias is applied to the operation.

[0074]

According to the present invention, since the power supply potential obtained by lowering the external power supply potential is used as the power supply potential of the CMOS circuit, the CMOS circuit operates at a low voltage and constitutes the CMOS circuit. An external power supply potential is applied to the back gate of the PMOS of the CMOS inverter circuit, and a PMOS to which a bias is applied is formed in consideration of an increase in the absolute value of the threshold voltage Vtp of the PMOS due to the back gate effect. The threshold voltage is adjusted by lowering the impurity concentration of the substrate or the well layer.
Since the operation is performed while being set to be equal to the threshold voltage of the MOS, high-speed operation can be performed with low power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of a power supply potential lowering circuit 106.

FIG. 3 is a circuit diagram showing an example of a specific circuit configuration of a reference potential generation circuit 107.

FIG. 4 is a diagram showing rise characteristics of the inverter circuit to which a bias is applied and the inverter circuit to which no bias is applied according to the first embodiment of the present invention;

FIG. 5 is a diagram showing falling characteristics of the inverter circuit to which a bias is applied and the inverter circuit to which no bias is applied according to the first embodiment of the present invention;

FIG. 6 is a diagram showing a C in the IC according to the first embodiment shown in FIG. 1;
FIG. 3 is a device diagram of a MOS inverter circuit.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a specific circuit configuration of a reference potential generation circuit 702.

FIG. 9 is a diagram illustrating rising characteristics of an inverter circuit to which a bias is applied and an inverter circuit to which no bias is applied according to a second embodiment of the present invention;

FIG. 10 is a diagram showing falling characteristics of a biased inverter circuit and a biased inverter circuit according to a second embodiment of the present invention.

FIG. 11 is a device diagram of a CMOS inverter circuit in the IC according to the second embodiment shown in FIG. 7;

[Explanation of symbols]

 101 VDD line 102 LVDD line 103 VSS line 701 HVSS line 104, 105 Pad 106 Power supply potential drop circuit 107, 702 Reference potential generation circuit 108, 703 CMOS circuit 109 PMOS 110, 704 NMOS N1 to N15 nodes

Claims (8)

[Claims] 1. A semiconductor integrated circuit, comprising: a first power supply line to which a first power supply potential is supplied; and a second power supply line to which the first power supply potential is supplied, wherein the first power supply potential is reduced. A power supply voltage drop circuit for generating the power supply potential of the second power supply potential; a second power supply line to which the second power supply potential generated by the power supply potential reduction circuit is supplied; and a third power supply potential lower than the second power supply potential And a CMOS circuit connected between the second power supply line and the third power supply line, the CMOS circuit including a P-type MOS transistor and an N-type MOS transistor. The first gate is connected to the back gate of the P-type MOS transistor.
A semiconductor integrated circuit to which a power supply potential is supplied. 2. The semiconductor integrated circuit according to claim 1, wherein said first power supply potential is supplied from outside. 3. A comparison circuit for receiving a reference potential output from a reference potential generation circuit, comparing the second power supply potential with the reference potential, and a comparison result of the comparison circuit. 3. The semiconductor integrated circuit according to claim 1, further comprising: a power supply potential adjustment circuit that adjusts a second power supply potential to become the reference potential based on the following. 4. A semiconductor integrated circuit, comprising: a first power supply line to which a first power supply potential is supplied; and a second power supply line to which the first power supply potential is supplied, and wherein the first power supply potential is reduced. A power supply potential lowering circuit for generating the power supply potential of the second power supply potential, a second power supply line to which the second power supply potential generated by the power supply potential lowering circuit is supplied, and a third power supply potential lower than the second power supply potential And a third power supply line to which a CMOS circuit is connected between the second power supply line and the third power supply line, the CMOS circuit including a P-type MOS transistor and an N-type MOS transistor. And a fourth power supply line to which a fourth power supply potential lower than the third power supply potential is supplied.
Is supplied to the back gate of the N-type MOS transistor.
A semiconductor integrated circuit to which a power supply potential is supplied. 5. The semiconductor integrated circuit according to claim 4, wherein said first power supply potential is supplied from outside. 6. The semiconductor integrated circuit according to claim 5, wherein said fourth power supply potential is a ground potential. 7. A comparison circuit for receiving a first reference potential output from a reference potential generation circuit and comparing the second power supply potential with the first reference potential. 7. A power supply potential adjustment circuit for adjusting a second power supply potential to be the first reference potential based on a comparison result of the comparison circuit. 3. The semiconductor integrated circuit according to claim 1. 8. The semiconductor integrated circuit according to claim 7, wherein a second reference potential lower than said first reference potential is supplied from said reference potential generation circuit to said third power supply line. .