JP2001068673A - Method for forming semiconductor device - Google Patents

Abstract

(57) Abstract: A method for forming a semiconductor device including an epitaxial semiconductor layer selectively deposited is provided. A component having a side wall is formed on a semiconductor device substrate. A sidewall of the component is undercut, and a selective epitaxial semiconductor layer having a first portion and a second portion is formed on the semiconductor device substrate. A first portion of the selective epitaxial semiconductor layer is formed between the undercut sidewall and the semiconductor device substrate and has a surface covered by the sidewall portion. Second of selective epitaxial semiconductor layer
A portion is formed on the semiconductor device substrate, adjacent to the sidewall,
A surface portion exposed and substantially parallel to the main surface of the semiconductor device substrate;

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Related Application] The present application is filed on the same day as the present case, is assigned to the present assignee of the present case, and is incorporated by reference into the present specification. Attorney's document number SC90882A “Method for Forming A Sem
semiconductor device (a method for forming a semiconductor device). "

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device having an epitaxial semiconductor layer selectively deposited.

[0003]

2. Description of the Related Art The size of semiconductor device components continues to challenge the process capabilities of conventional implant and silicide processes to form very shallow source / drain structures. In order to meet the dimensional requirements of future generation devices, one possible alternative is to use elevated source / drain regions (elevat) formed using selectively deposited epitaxial silicon.
ed source / drain region). The elevated source / drain region can function both as a sacrificial silicide layer when forming the source / drain regions of the transistor and as an outdiffusion source after implantation. However, the advantages of the elevated source / drain structure may be limited by process integration issues caused by facets formed in the selectively deposited epitaxial silicon.

FIG. 1 shows an elevated source with facets.
FIG. 4 is a partial cross-sectional view of a semiconductor device having a drain region. More specifically, FIG. 1 includes a gate dielectric layer 112 and a gate electrode 114 formed on the semiconductor device substrate 10. A doped extension region 116 is formed in the semiconductor substrate 10. The extension region 116 to be doped has a lightly doped drain (LDD: li).
ghtly doped drain) region, but usually has a higher doping concentration than the LDD region.

[0005] An oxide liner layer 122 and spacers 124 are formed along the sidewalls of the gate electrode 114. After formation of the spacers 124, a selective epitaxial deposition process is used to form the elevated source / drain regions 126. Facets 1262, 1264
Are the products of the selective epitaxial deposition process, which are formed at the end of the elevated source / drain region 126 near the spacer 124. In this embodiment, facet 1262 is substantially $ 11.
Along the 1｝ crystal plane, facet 1264 is {31
The upper surface 1266 is formed along the {100} crystal plane. The {100} crystal plane is also a crystal plane of the main surface of the semiconductor substrate 10. A doped source / drain region 128 is formed in the semiconductor substrate 10. The doped source / drain regions 128 are formed using a conventional ion implantation method.

As shown in FIG. 1, the cross section of the doping junction associated with the source / drain regions 128 varies with the facets formed in the elevated source / drain regions 126. The junction doping cross section is facet 126
2,1264 high source / drain regions 126
Is affected by variations in thickness. This portion of the elevated source / drain region 126 having facets is generally uneven and thinner.
Corresponding to the part. Elevated source / drain region 126
Also correspond to regions in the substrate 10 where the junction doping cross section is non-uniform and extends deeper into the substrate 10. Deeper non-uniform junction doping cross sections are undesirable for several reasons. First,
As a result, the area between the source / drain region and the substrate increases, thereby increasing the overall capacitance of the junction. Second, the presence of a partially deep junction results in a partially reduced dopant concentration in the region between the center of source / drain region 128 and extension region 116. This may increase the resistance between the source / drain region 128 and the extension region 116. This is because the distribution of the dopant species is not optimal for the semiconductor device. Higher resistance can affect the operating speed of the device, which is generally undesirable. Finally,
Drain-induced-barrier-lowering (DIBL) when there is a partially deep junction region
May cause short channel effects. This is because the partially deep junction extends the source / drain region laterally below the spacer, moving this region closer to the gate edge, thereby reducing the effective extension.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the present invention, a component having a side wall is formed on a semiconductor device substrate. A sidewall of the component is undercut, and a selective epitaxial semiconductor layer having a first portion and a second portion is formed on the semiconductor device substrate. The first portion is formed between the undercut side wall and the semiconductor device substrate, and has a surface covered by the side wall portion. The second portion is formed adjacent to the sidewall and has an exposed surface that is substantially parallel to the main surface of the semiconductor device substrate.

Embodiments of the present invention will be described in more detail with reference to the accompanying drawings. FIG. 2 is a sectional view of the semiconductor device substrate 20. As used herein, semiconductor device substrates include single crystal semiconductor wafers, semiconductor wafers on insulators, or any other substrate used to form semiconductor devices. According to one embodiment, partially formed components 22 are formed over portions of semiconductor device substrate 20. In this embodiment, the part 22 to be partially formed is formed by sequentially forming a gate dielectric layer 24, a gate electrode layer 26, and an antireflection layer 28 on the semiconductor device substrate 20. Next, the semiconductor device substrate 20 is patterned and etched to define the partially formed part 22 shown in FIG. In this embodiment, the partially formed component 22 is a gate electrode laminated portion. Next, a thin oxide layer (not shown) is formed on the exposed surface of the substrate 20 and the partially formed component 22, and an extension region 29 is formed in the semiconductor device substrate 20 using an ion implantation process step. .

Next, the anti-reflective layer 28 is removed using a conventional hot phosphoric acid solution. A liner layer 32 is formed on substrate 20 and partially formed component 22 as shown in FIG. Typically, the liner layer is formed by thermal oxidation or using other conventional deposition processes. In some embodiments, liner layer 32 is a single layer that includes an oxide. In other embodiments, the liner layer 32 may be a plurality of layers, or a spacer 34 and a lower substrate 20 to be formed later.
It can be formed using any material or combination of materials that can be selectively etched with respect to. In this embodiment, the liner layer 32 is made of tetraethylorthosilicat (TEOS).
It is formed using a deposition process using e) as the source gas. Typically, the thickness of the liner layer is in the range of about 10 to 30 nanometers (nm).

According to one embodiment, after formation of the liner layer 32, a spacer 34 is formed to define the substantially formed component 36 shown in FIG. Typically, spacers 34 are formed of silicon nitride and have a base width dimension 38 of about 50-100 nm. The silicon nitride is typically deposited with an initial thickness of about 50-120 nm and then etched back to form spacers 34. It will be apparent to those skilled in the art that the etching process for forming the spacer is conventional and that the cross-section of the spacer is affected by the etching process used to form it.

After formation of the spacers 34, etching is performed to remove portions of the liner layer 32 and expose portions of the substrate 20. Further, the portion of the liner layer below the spacer 34 is undercut and removed by this etching. The amount of undercut is indicated by the dimension 42 shown in FIG. The amount of undercut is typically in the range of about 20 to 50 nanometers (nm). However, those skilled in the art will recognize that the amount of undercut is further determined by the spacer width at the base. In this embodiment, the amount of undercut is
75% or less of the width at the base. However, the distance between the end of the liner layer 32 and the gate electrode 26 should be at least 15 to 20 nm so that the mirror capacitance effect between the gate electrode 26 and the elevated source / drain region formed later is excessive. Must be reduced. Further, the amount of undercut is also limited by the mechanical support requirements of the spacer 34. If there are too many undercuts, there is a risk of delamination of the spacer.

In accordance with one embodiment of the present invention, liner layer 32
Prior to etching, a pre-cleaning process is performed. In the pre-cleaning process, cleaning with ammonium hydroxide and hydrogen peroxide is performed after cleaning with conventional sulfuric acid and hydrogen peroxide. Next, the liner layer 32 is etched using a deionized water / hydrofluoric acid (HF) solution. The concentration of this solution is about 100 deionized water (100:
1). Other concentrations, other etchants, and an isotropic plasma etching process may alternatively be used to etch liner layer 32 to form an undercut. For example, a 50: 1 or 10: 1 concentration of deionized water / HF solution can be used. Alternatively, a buffered oxide etch (BOE) containing hydrofluoric acid and ammonium fluoride can be used. The skilled artisan can decide which etching process and chemicals to use to moderately control the undercut.

FIG. 5 shows a graph of both the facet rate and the etching time, and the amount of undercut and the etching time when using a 100: 1 deionized water / HF solution. For the purposes of this specification, the facet ratio is not covered by the spacer (ie, between the spacer 34 and the substrate 20).
Divided by the total facet length. Therefore, $ 11
1｝ If the entire length of the facet is covered by the spacer 34,
The facet rate becomes zero. The more the {111} facet is exposed (ie, not covered by the spacer 34), the higher the facet ratio. Therefore, in FIG.
The 11 ° facet amount is about 170 seconds later, or after forming an undercut of about 30 nm in this example,
It drops to almost zero.

Prior to forming a selectively epitaxial film to be formed later on the substrate, hydrogen (H 2) or hydrogen chloride (HC
The substrate may be fired in a hydrogen environment using l) as a hydrogen source. Next, a selective epitaxial semiconductor region 62 and a selective polysilicon region 66 shown in FIG. 6 are formed by using a selective epitaxial deposition process. According to one embodiment of the present invention, selective epitaxial semiconductor region 62 is formed as a selective epitaxial silicon region. The thickness of the selective epitaxial silicon region is typically in the range of about 10 to 100 nm. According to an embodiment of the present invention, the epitaxial semiconductor region 62 may be a doped selective epitaxial layer.
It may be a silicon region or an undoped selective epitaxial silicon region. Due to the undercut already formed, the facets 64 of the selective epitaxial semiconductor region 62 are
0 is formed. Therefore, those portions of the selective epitaxial region 62 that have facets are covered with spacers and are not exposed. This is in contrast to the exposed portion of the selective epitaxial region 62. The exposed portion of selective epitaxial region 62 has a surface 68 substantially along the {100} crystal plane and is substantially parallel to main surface 69 of semiconductor device substrate 20. Further, the thickness of the selective epitaxial region in the portion associated with surface 68 is substantially uniform. Selective polycrystalline region 66 forms gate electrode 26
Formed on Region 66 generally has a polycrystalline structure and is typically in the shape of a "bread."

The parameters of the selective epitaxial deposition process are conventional. For example, trichlorosilane, dichlorosilane, silane, disilane,
A silicon source such as brominated silane can be used.
The degree of selective deposition typically depends on the silicon source chemical and the deposition temperature. Brominated silicon compounds have better selectivity than chlorinated silicon compounds. Increasing the number of halogen elements in the silicon source gas also improves selectivity. Thus, hydrogen chloride or molecular chlorine can flow during some or all of the deposition cycle. When dichlorosilane is used as the source gas, the deposition temperature is typically about 800 to 90 degrees Celsius.
It is in the range of 0 degrees. One skilled in the art will recognize that the deposition temperature can be changed by increasing or decreasing the number of halogen elements in the silicon halide source gas. For example, the deposition temperature of dichlorosilane is expected to be lower than the deposition temperature of trichlorosilane. Selectively deposited epitaxial
Selective epitaxial semiconductor region 62 using silicon
In addition to forming the selective epitaxial region 6
2 is silicon germaniu
m), other selectively deposited thin films including silicon carbide, silicon carbide / germanium, and the like. In this case, a corresponding appropriate source gas is used.

The ion implantation step indicated by arrow 72 in FIG. 7 is performed to form source / drain regions 74. The facetless deposition process described herein allows the formation of doped source / drain regions 74 without creating the non-uniform and deeper junction cross-sectional area 1282 seen in prior art FIG. . Thus, unlike the prior art, the junction formed as a result of the ion implantation step has a substantially constant overall depth parallel to the main surface of semiconductor device substrate 20. This reduced depth variation across the junction results in doped source / drain regions 74.
The amount of junction area between the substrate and the substrate 20 is further reduced, and the overall junction capacitance is correspondingly reduced. In addition, the distribution of the dopant species in the substrate after ion implantation has the same depth over the entire length of the source / drain regions and is more closely distributed in the region adjacent to extension region 29. Therefore, the resistance between the source / drain region and the extension region is reduced, and the short channel effect such as DIBL is reduced as compared with the related art. Further, because the junction depth can be more tightly controlled, the device can be made with tighter tolerances and smaller dimensions. Therefore, the reliability and performance of the entire semiconductor device can be improved. After implanting the dopant into the selectively deposited epitaxial silicon region 62 and the substrate 20, the substrate is annealed and the dopant is diffused and activated, thereby joining the source / drain region and the extension region in the substrate. Further defining the part.

Next, a self-aligned silicide process is performed to convert portions of the selective epitaxial layer to silicide regions 82 shown in FIG. In this embodiment, cobalt is deposited on the substrate and reacts to form cobalt silicide regions 82. Thereafter, unreacted cobalt is removed from the side surface of the spacer 34. with this,
The silicide region 82 can be formed without electrically shorting the source / drain region 74 to the gate electrode. The thickness of silicide region 82 may vary. In this embodiment, silicide region 82 has a thickness that approximates the thickness of selectively grown epitaxial region 62 shown in FIGS. In this way, the advantage of using the selectively grown epitaxial region 62 as a sacrificial silicide layer is obtained.

Next, the substantially completed device shown in FIG. 9 is formed. Interlevel dielectric (ILD)
electric) layer 90 is formed over silicide region 82 and patterned to form contact openings 92. Next, conductive plugs 94 and interconnects 96 are formed and make electrical contact with one of the silicide regions 82. Next, a passivation layer 98 is formed on the top layer of the interconnect. Although not shown, other electrical connections can be made to gate electrode 26 and other source / drain regions 74. Further, other ILD layers and interconnect levels can be formed as needed to form more complex semiconductor devices.

One of the advantages is that the present embodiment can be incorporated into existing process flows without using or complicating foreign matter. Using standard pre-cleaning and etching, the liner layer 32 is removed and the spacer 3 is removed.
4 can be undercut and the deposition process for forming the selective epitaxial semiconductor layer is conventional. Thus, existing processes can be used to form a facetless selective epitaxial semiconductor layer while minimizing the risk of generating extra contamination and scrap as a result of new or additional processing steps.

The present invention includes other alternative embodiments. In the embodiment described in FIGS. 1 to 9, the gate electrode is formed prior to the deposition of the selective epitaxial semiconductor layer. In an alternative embodiment, the gate electrode can be formed after forming the selective epitaxial semiconductor layer. According to this embodiment, the component becomes a dummy component of a gate electrode to be formed later, and the selective epitaxial semiconductor layer is formed after the formation of the dummy component. Dummy parts are
It has the same shape as the part 36 shown in FIG. After formation of the selective epitaxial semiconductor layer, the dummy component is removed and a suitable gate electrode material is formed instead. This embodiment allows the selective epitaxial semiconductor layer to be formed such that the facet is completely covered by the spacer (ie, formed between the spacer and the substrate). Alternatively, the selective epitaxial semiconductor layer may have a facet extending beyond the spacer (ie the facet is only partially covered by the spacer),
It can also be formed so as to be exposed. Extending the facet beyond the spacer can be done by reducing the angle of the facet. Reducing the angle of the facet is advantageous because the vertical height of the selective epitaxial semiconductor layer adjacent to the gate end is reduced, and the effect of reducing the Miller capacitance effect is obtained accordingly.

In another alternative embodiment, a deep source /
Instead of forming a shallow doping extension before forming the drain region, the doping extension can be formed later. This embodiment is advantageous because the doped extension region is not exposed to the high temperatures normally required during source / drain annealing. This is shown in FIG.
Can be performed by omitting the processing steps initially used to form the extension region 29 shown in FIG. Next, the semiconductor device substrate is processed to form gate electrodes, selective epitaxial silicon layers and source / drain regions similar to those illustrated in FIG. next,
The spacer adjacent to the gate electrode is removed and an extension implant is performed to form a doping extension in the substrate region between the selective epitaxial semiconductor layer and the gate electrode. If necessary, a short anneal is performed to properly activate and diffuse the doped extension region. Next, a spacer is formed again adjacent to the gate electrode, and processing is continued to form an appropriate semiconductor device structure.

In yet another alternative embodiment, the present invention can be used to form a bipolar transistor. In this embodiment, without forming a gate electrode, an external base that is in electrical contact with the doped region (intrinsic base) in the substrate is formed. Thereafter, a liner, spacer or other insulating component can be formed adjacent to the external base, similar to that illustrated in FIG. Next, the liner is removed and undercut as in the removal and undercut of the liner layer 32 shown in FIG. Thereafter, a facetless, selectively deposited epitaxial semiconductor layer similar to that described in FIG. 6 is formed. Finally, an ion implantation step and annealing are performed to dope the selectively deposited epitaxial semiconductor region, to form an emitter, and to be selectively deposited as shown in FIGS. Removing the dopant from the grown epitaxial semiconductor region. This embodiment has similar advantages to the embodiment described in FIGS. 1-9, except that it does not create the non-uniform, deep junction cross-sectional area seen in prior art FIG. This is because a portion can be formed. Thus, the likelihood of junction spikes penetrating the base and into the collector or collector drift region is reduced.

A further advantage of the embodiments described herein is that when the selective epitaxial silicon region is doped, it can be used as a source of dopant out-diffusion into the substrate. The portion of the selective epitaxial silicon region extending under the spacer is used as a source of dopant out-diffusion and the source /
By further doping the drain extension region,
This is particularly advantageous.

In the above description, the present invention has been disclosed with reference to specific embodiments. However, it will be apparent to one skilled in the art that various modifications and changes may be made without departing from the scope of the present invention as set forth in the claims below. Therefore,
The description and drawings are to be regarded as illustrative instead of limiting, and all such modifications are intended to be included within the scope of the present invention. Benefits, other advantages, and solutions to problems have been disclosed with respect to specific embodiments. However, the advantages, advantages, problem solutions and any elements that can be advantages, advantages or solutions, or that are more prominent, are important, essential or essential characteristics or elements of some or all of the claims. Is not considered.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a portion of a semiconductor device having an elevated source / drain region with facets (prior art).

FIG. 2 is a cross-sectional view of a part of the semiconductor device after forming a patterning portion on the semiconductor device substrate and forming a doping region in the semiconductor substrate.

3 is a cross-sectional view of the semiconductor device substrate of FIG. 2 after formation of a liner layer and a spacer.

FIG. 4 is a cross-sectional view of the semiconductor device substrate of FIG. 3 after removing a liner layer portion and undercutting a spacer portion.

FIG. 5 is a graph of the ratio of facet and undercut and etching time.

FIG. 6 is a cross-sectional view of the semiconductor device substrate of FIG. 4 after formation of the elevated source / drain regions according to the present invention.

7 is a cross-sectional view of the semiconductor device substrate of FIG. 6 after formation of a heavily doped source / drain region.

8 is a cross-sectional view of the semiconductor device substrate of FIG. 7 after formation of a silicide region.

9 is a cross-sectional view of the semiconductor device substrate of FIG. 8 after formation of a substantially completed device.

[Explanation of symbols]

 Reference Signs List 20 semiconductor device substrate 24 gate dielectric layer 26 gate electrode layer 29 extension region 32 liner layer 34 spacer 64 facet 74 source / drain region 82 cobalt silicide region 90 intermediate level dielectric layer 92 contact opening 94 conductive plug 96 interconnect 98 passivation layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Philip Jay Tobin Windermere Meadows 11410, Austin, Texas, USA Inventor Anna M. Phillips Fensrail Road 13207, 72, Manchaka, Texas, USA Inventor Anthony Dip John Blocker Drive 7221, Austin, Texas, USA

Claims (5)

[Claims] 1. A method for forming a semiconductor device, comprising: forming a gate electrode (22) on a substrate (20); forming a spacer (34) adjacent to the gate electrode (22); Forming a surface region of the exposed substrate (20), including exposing the substrate (20) surface region below the spacer (34) by undercutting (42) the spacer (34). Forming a selective epitaxial semiconductor layer (62) on a surface region of the exposed substrate (20), wherein the selective epitaxial semiconductor layer (62) includes a first portion and a second portion; A first portion having a first surface (64) covered by the spacer (34), a second portion having a second surface (68) not covered by the spacer (34), the second surface; (68 ) Is substantially parallel to a major surface (69) of the substrate (20); implanting a dopant species (72) into the selective epitaxial semiconductor layer (62); and removing the substrate (20). Annealing, diffusing the dopant species by annealing the substrate (20) to define a source / drain region (74) junction in the substrate (20) and, after annealing, the source / drain region (74) a step in which the junction has substantially the same depth along the entire portion under the selective epitaxial semiconductor layer (62), relative to the main surface (69) of the substrate (20). A method comprising: 2. A method for forming a semiconductor device, comprising: forming a gate electrode (22) having a side wall on a substrate (20); undercutting a portion of the side wall (4).
2) forming a doped selective epitaxial semiconductor layer (62) on the substrate (20), wherein the doped selective epitaxial semiconductor layer (62) comprises a first portion and a second portion; Wherein the first portion has a first surface (64) covered by the side wall, and the second portion has a second surface (6) not covered by the side wall.
8), wherein the second surface (68) is provided on the substrate (20).
Substantially parallel to the main surface (69) of the substrate; and the doped epitaxial semiconductor layer (62).
From the first portion to the substrate (2).
0) diffusing a dopant into the substrate (20) by diffusing the dopant from the first portion into the substrate (20). A method comprising: 3. A method for forming a semiconductor device, comprising: forming a gate electrode (22) on a substrate (20); and forming a gate electrode (22) along a sidewall of the gate electrode (22).
Forming an upper insulating layer (32); forming a spacer (34) on the insulating layer (32), wherein the spacer (34) is formed on the gate electrode (22).
A side wall portion adjacent to a side wall of the spacer (3).
4) having a bottom portion adjacent to the substrate (20); removing a first portion of the insulating layer (32) to expose a first portion of the substrate (20); Removing a second portion (42) of the insulating layer (32) between the substrate (20) and exposing a second portion of the substrate (20); silicon, silicon germanium,
Selective epitaxial semiconductor layer (62) selected from the group consisting of silicon carbide and silicon germanium
The first portion of the substrate (20) and the substrate (20)
Depositing on said second portion, wherein said selective epitaxial semiconductor layer (62) comprises a first selective epitaxial semiconductor layer portion and a second selective epitaxial semiconductor layer portion; A selective epitaxial semiconductor layer portion is formed on the first portion of the substrate (20) and covered by the spacer (34), and the second selective epitaxial semiconductor layer portion is formed on the substrate (2).
0) formed on the second portion, wherein the second selective epitaxial semiconductor layer portion has a surface (68) that is on the same crystal plane as a main surface (69) of the substrate (20);
The second selective epitaxial semiconductor layer portion having a surface (68) substantially parallel to the main surface (69) of the substrate (20). 4. A method for forming a semiconductor device, comprising: forming a gate electrode (22) on a substrate (20); forming a spacer (34) adjacent to the gate electrode (22); The portion of the insulating layer (32) formed prior to the formation of the spacer (34) is removed to undercut (42) the spacer (34), and the substrate (2) is removed.
0) defining the exposed surface area; said substrate (2)
0) depositing a selective epitaxial semiconductor layer (62) on the exposed surface region, said epitaxial semiconductor layer having a first portion, a second portion, and a third portion; A first portion having a first surface portion (64) covered by the spacer (34); a third portion having a third surface portion (68) not covered by the spacer (34); (20) parallel to the main surface (69) and along the same crystal plane as the main surface (69) of the substrate (20), wherein the second portion is the first portion and the third portion; Having a second surface portion, wherein the slope of the second surface portion with respect to the main surface (69) of the substrate (20) is the same as that of the substrate (3) of the third surface portion (68). 20) greater than a slope with respect to said main surface (69); Method characterized in that thus is configured. 5. A method for forming a semiconductor device, comprising: forming a dummy component on a first region of a substrate (20);
Forming an insulating layer (32) located above the dummy component and the substrate (20); a spacer (3) located above the insulating layer (32) and adjacent to a side wall of the dummy component;
4); undercutting the spacer (34) by removing a portion of the insulating layer (32) between the spacer (34) and the substrate (20); A) forming a selective epitaxial semiconductor layer (62) thereon, wherein said selective epitaxial semiconductor layer (62) comprises a first portion and a second portion, said first portion comprising said spacer (34); A first surface (64) covered by the first surface (64), the second portion has a second surface (68) not covered by the spacer (34), and the second surface (68) is Being substantially parallel to the main surface (69) of the semiconductor device; removing the portion of the dummy component; and forming a gate electrode (22) on the first region. how to.