JP2001068520A - Method of analyzing defect of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an etching method which is effective in analyzing the defects of an LSI. SOLUTION: This method is for analyzing defects of a semiconductor device, by which a defect at the interface between a gate oxide film 2 and a gate electrode 3 is analyzed in a semiconductor device, having the gate electrode 3 formed via the gate oxide film 2 on a semiconductor silicon substrate 1. The method comprises a first etching step of etching an interlayer insulating film 5 covering the gate electrode 3 by the use of CHF3 gas, to expose the surface of the gate electrode 3 and a second etching step of etching the gate electrode 3, by using an interlayer insulating film 5A left on the sidewall of the gate electrode 3 as a mask by the use of a CF4 gas to expose the surface of the gate oxide film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for analyzing a failure of a semiconductor device, and more particularly to an etching technique for inspecting and analyzing an LSI.

[0002]

2. Description of the Related Art There are many defects that are difficult to find in the current LSI failure analysis. One of the flaws is
It is presumed that dust generated during the wafer process is attached to the interface between the gate oxide film and the gate electrode made of a polysilicon film or the like.

Accordingly, in order to identify a defect, it is necessary to expose the surface of the gate oxide film without damaging the surface of the gate oxide film. As a method of exposing the interface between the gate oxide film and the gate electrode, a polishing method of polishing with a grindstone is generally used.

[0004]

However, in the above-mentioned polishing method of polishing with a grindstone, even if it succeeds, it is limited to a specific place, and there are many failures. Moreover, strictly speaking, it is impossible to uniformly cut the entire chip with a grindstone that is not perfectly flat.

Therefore, conventionally, an etching method using a chemical wet etching apparatus or a plasma etching apparatus has been studied, but desired results have not been obtained.

That is, when the interlayer insulating film made of a BPSG film or the like is removed by the conventional method, a high etching selectivity cannot be obtained between the BPSG film and the gate electrode and the gate oxide film. The gate oxide film is also removed, and defects existing at the interface between the gate oxide film and the gate electrode disappear.

As described above, in the prior art, a high etching selectivity cannot be obtained between the BPSG film and the gate electrode and the gate oxide film. Therefore, it is very difficult to etch only the BPSG film and only the gate electrode. And
The conventional selective etching method is not suitable for failure analysis of LSI.

In general, a semiconductor device having a single drain structure or a DDD (double doped drain) structure has been widely put into practical use in a process having a gate length larger than 1.5 μm in design rules.
Unlike a submicron MOS device having a doped drain structure, since there is no sidewall spacer film, there is a problem that etching damage is large on the side of the gate electrode, and the etching cannot be performed during failure analysis.

Accordingly, it is an object of the present invention to provide a semiconductor device failure analysis method using an effective etching method for performing LSI failure analysis.

[0010]

SUMMARY OF THE INVENTION Accordingly, the present invention provides an interface between a gate oxide film and a gate electrode in a semiconductor device having a gate electrode formed on a semiconductor silicon substrate via a gate oxide film. In the semiconductor device failure analysis method for analyzing failures existing in the semiconductor device, as shown in FIG. 2 (a), the interlayer insulating film 5 covering the gate electrode 3 is filled with CHF ₃ gas until the surface of the gate electrode 3 is exposed. A first etching step of etching away using
As shown in FIG. 2B and FIG. 2C, the gate electrode 3 is removed by etching using CF ₄ gas using the interlayer insulating films 5B and 5C remaining on the side walls of the gate electrode 3 as a mask. And a second etching step for exposing the surface of the gate oxide film 2.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a semiconductor device failure analysis method according to an embodiment of the present invention.

In FIG. 1, a gate electrode 3 made of a polysilicon film having a thickness of about 3000 to 4000 is formed on a semiconductor silicon substrate 1 of one conductivity type, for example, a P type via a gate oxide film 2. The gate electrode 3 is made of a polysilicon film and tungsten silicide (WS).
ix) It may be a so-called polycide gate electrode composed of a laminated film with a film. Reference numeral 4 denotes an element isolation film, and reference numeral 5 denotes an interlayer insulating film made of a BPSG film having a thickness of about 6000 °. Although not shown for convenience, an N-type source / drain region is formed on the surface layer of the silicon substrate 1 so as to be adjacent to the gate electrode 3.
By forming a metal wiring via the interlayer insulating film 5 so as to contact the drain region, for example,
A semiconductor device having a 1.6 μm rule is completed.

A method of analyzing a failure in such a semiconductor device will be described with reference to FIG.

First, as shown in FIG. 2A, the interlayer insulating film 5 is removed by etching until the surface of the gate electrode 3 is exposed. Here, the interlayer insulating film 5 is left on the element isolation film 4 and on the side wall of the gate electrode 3 to form an interlayer insulating film 5A.

The etching conditions in this step are as follows. For example, a reactive ion etching (RIE) device is used.
sccm CHF ₃ gas, vacuum degree 2.66 Pa, RF
A completely anisotropic etching method with an output of 60 W and an etching time of 40 minutes is used.

Next, as shown in FIG. 2B (during etching) and FIG. 2C, the interlayer insulating film 5A (the interlayer insulating film 5A
B, 5C. ) Is used as a mask to remove the gate electrode 3 by etching, thereby exposing the surface of the gate oxide film 2 and removing defects (for example, pin holes 6) existing at the interface between the gate electrode 3 and the gate oxide film 2. Successfully found.

The etching conditions in this step are, for example, an isotropic etching method using a RIE apparatus in which CF ₄ gas at a flow rate of 80 sccm, vacuum degree is 53.2 Pa, RF output is 40 W, and etching time is 15 minutes. I do.

As described above, according to the present invention, the completely anisotropic etching for etching the interlayer insulating film 5 to the position where the surface of the gate electrode 3 is exposed, and the use of the remaining interlayer insulating film 5A as a mask By combining with isotropic etching, the gate electrode 3 can be removed without damaging the surface of the gate oxide film 2.

In particular, in the present invention, the design rule up to the 1.6 μm rule is relatively large, and since there is no sidewall spacer film, the adhesion of the gate electrode 3 is weak.
By employing the present invention, the gate electrode 3 can be removed without damaging the surface of the gate oxide film 2 even in a device structure that cannot withstand the etching at the time of the conventional failure analysis.

The RIE apparatus used is a cathode-coupling type single-wafer apparatus. At this stage, it can be applied to the failure analysis of semiconductor devices in the miniaturization process down to the 0.35 μm rule adopted by our company. Was confirmed.

The introduction of this masking method (using the interlayer insulating film 5A left at the time of the first etching as a mask at the time of the second etching) makes it possible to use the next-generation 0.2.
The possibility that the RIE technology can be applied to failure analysis of a semiconductor device in a 5 μm rule or 0.18 μm rule miniaturization process has been expanded. That is, for example, when the level is below the 0.3 μm rule, the influence of etching damage from the side of the gate electrode increases, and the influence on the gate oxide film is concerned. Therefore, in the present invention, the influence of etching damage from the side of the gate electrode is reduced by adopting a masking method in order to improve the etching resistance of the gate oxide film 2 from the side of the gate electrode. With respect to the so-called use limit in a normal wafer process (the gate length is about 0.35 μm), the use limit can be postponed in a special use such as failure analysis.

[0022]

According to the present invention, a completely anisotropic etching method for etching an interlayer insulating film to a position where the surface of a gate electrode is exposed, and an isotropic etching using the remaining interlayer insulating film as a mask By combining with the law,
The gate electrode can be removed without damaging the surface of the gate oxide film, and defects existing on the gate oxide film can be reliably observed by SEM observation.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a failure analysis method for a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a failure analysis method for a semiconductor device according to an embodiment of the present invention.

Claims (2)

[Claims] 1. A failure analysis method for a semiconductor device, comprising: analyzing a failure at an interface between a gate oxide film and a gate electrode in a semiconductor device having a gate electrode formed on a semiconductor silicon substrate via a gate oxide film. A first etching step of etching and removing the interlayer insulating film covering the gate electrode until the surface of the gate electrode is exposed; and the gate electrode using the interlayer insulating film remaining on the side wall of the gate electrode as a mask. And a second etching step of exposing the surface of the gate oxide film by etching. 2. The semiconductor according to claim 1, wherein the etching gas used in the first etching step is CHF ₃ , and the etching gas used in the second etching step is CF _4. Equipment failure analysis method.