JP2001068559A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A mask alignment for forming a field oxide film is performed without adding a step of forming a Si step even in a state where there is no Si step. A surface step of about 850 ° is formed on a surface of a silicon nitride film, reflecting a step between a first oxide film and a second oxide film. This surface step 39
The polysilicon layer 37 and the silicon nitride film 3
8. A mask alignment for patterning 8 is performed. After that, a polysilicon layer 37 and a silicon nitride film 38 are formed.
Perform selective oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly, to a MOS transistor having a high source / drain breakdown voltage and a high gate breakdown voltage (hereinafter referred to as a high breakdown voltage transistor) and a high breakdown voltage transistor. The present invention relates to a technique for reducing the number of steps when forming a MOS transistor having a lower source / drain breakdown voltage and a lower gate breakdown voltage than a transistor (hereinafter, referred to as a low breakdown voltage transistor or a normal breakdown voltage transistor) on the same semiconductor substrate.

[0002]

2. Description of the Related Art In a driving IC such as an LCD or an LED, a driving circuit portion operating at several tens of volts or more is constituted by a high voltage transistor, and a logic portion operating at 5 volts or less is constituted by a normal voltage transistor. Therefore, it is necessary to integrate the high breakdown voltage transistor and the normal breakdown voltage transistor in one IC.

In order to manufacture such an IC, the gate oxide film of a high-breakdown-voltage transistor and the oxide film of a normal-breakdown-voltage transistor have different film thicknesses, so that it is necessary to make them separately. Further, the source layer and the drain layer of the high breakdown voltage transistor need to be diffused at a low concentration and deeply. Therefore, the number of manufacturing steps is large, and the cost is increased. Therefore, it is required to reduce the number of steps, particularly the number of mask alignment steps.

[0004]

In a conventional method of manufacturing a semiconductor device, mask alignment in a certain process step is performed by:
This has been done by using a step (Si step or the like) on the surface of the semiconductor substrate formed by a previous process step.

That is, the surface of a semiconductor substrate coated with a photoresist is irradiated with laser light or the like, the reflected light is detected, and mask alignment is performed using a detection signal generated from the step. For example, in mask alignment in a LOCOS process, it has been usual to use a step in a well region formed before that.

However, when performing mask alignment in a state where there is no such Si step, it is necessary to add a step of forming the Si step, and there is a problem that the number of steps is increased.

Accordingly, the present invention provides a method of manufacturing a semiconductor device in which a normal breakdown voltage transistor and a high breakdown voltage transistor are formed on the same semiconductor substrate, and further includes a step of forming a Si step even if there is no Si step. It is intended to enable mask alignment.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a normal breakdown voltage transistor and a high breakdown voltage transistor are formed on the same semiconductor substrate. Forming a first oxide film, forming a photoresist layer having an opening on the first oxide film, and selectively removing the first oxide film; and thermally oxidizing the entire surface. Forming a second oxide film having a smaller thickness than the first oxide film in a region where the first oxide film has been removed;
Forming an oxidation-resistant film on the second oxide film; performing a mask alignment for patterning the oxidation-resistant film using a step between the first and second oxide films; A step of patterning the oxide film and a step of performing selective oxidation using the patterned oxidation-resistant film.

According to this means, an oxide film step is generated due to the difference in the thickness of the first and second oxide films, and a mask alignment for patterning the oxidation-resistant film is performed using the step. This enables mask alignment without forming a Si step.

According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, a semiconductor layer is formed by implanting ions into the semiconductor substrate using the photoresist layer having the opening as a mask. It is characterized by having.

According to the above means, the semiconductor layer is formed so as to match the step between the first and second oxide films. Therefore, by performing mask alignment for patterning the oxidation-resistant film using the steps of the first and second oxide films, the field oxide film formed by selective oxidation later matches the semiconductor layer. Formed. For this reason, mask alignment accuracy is improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to a first embodiment will be described with reference to FIG.

As shown in FIG. 1A, the surface of a P-type silicon substrate 30 is thermally oxidized to form a first oxide film 31 serving as a gate oxide film of a high breakdown voltage transistor. The thickness of the first oxide film 31 is set according to the breakdown voltage specification of the transistor. In the case of the specification of the withstand voltage of 30 V, if the electric field of the first oxide film 31 is suppressed to 3 MV / cm 2, it is about 900 °.

Next, as shown in FIG. 1B, a photoresist layer 32 is formed on the first oxide film 31. And
Phosphorus ions are implanted into the surface of the silicon substrate 30 from the opening 32a of the photoresist layer 32 to form an N-type layer 33.

Next, as shown in FIG. 1C, the first oxide film 31 is removed by etching using the photoresist layer 32 as a mask. After removing the photoresist layer 32, thermal oxidation is performed again, and a second oxide film serving as a gate oxide film of a normal breakdown voltage transistor is formed on the region where the first oxide film 31 is removed.
Oxide film 34 is formed. The second oxide film 34 is usually set according to the characteristics of the withstand voltage transistor, but is formed thinner (about 150 °) than the first oxide film 31. As a result, a step 35 is generated between the first oxide film 31 and the second oxide film 34.

Then, as shown in FIG. 1D, a polysilicon layer 36 and a silicon nitride film 37 are deposited by LPCVD. The silicon nitride film 37 is used as an oxidation resistant film for selective oxidation, and the polysilicon layer 36 is used as a buffer film during selective oxidation. On the surface of the silicon nitride film 37, a surface step 38 of about 850 ° is formed reflecting the step 35 between the first oxide film 31 and the second oxide film 35.

Using this surface step 38, a mask alignment for patterning the polysilicon layer 37 and the silicon nitride film 37 is performed. After that, the polysilicon layer 3
6. A silicon nitride film 37 is formed and selective oxidation is performed.

Next, a method of manufacturing a semiconductor device according to the second embodiment will be described in detail with reference to the drawings. This manufacturing method relates to a method of forming an N-channel type normal breakdown voltage transistor and a high breakdown voltage transistor on the same semiconductor substrate.

As shown in FIG. 2, a first oxide film (thick oxide film) 2 having a thickness of about 1000 ° is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method. Then, a photoresist layer 3 is applied and formed on the first gate oxide film 2, and the photoresist 3 is exposed and developed to provide an opening 3a (first opening) in the photoresist 3, and through this opening 3a,
By implanting phosphorus ions ( ³¹ P +),
An N-type layer 4a (first N-type layer) to be a low-concentration source / drain layer is formed later.

The N-type layer 4a is formed at a predetermined distance from the surface of the silicon substrate 1 to form a source / drain layer. An opening 3b (second opening) is further formed in the photoresist 3. This opening 3b is formed in a region where a normal breakdown voltage transistor is formed. From the opening 3b, phosphorus ion ⁽³¹ P +) is ion-implanted at the same time, the N-type layer 4b (second N-type layer) is formed.

Then, as shown in FIG. 3, using the photoresist layer 3 as it is, etching is performed by an etchant such as diluted HF to remove the first gate oxide film 2 exposed in the openings 3a and 3b. I do.

As described above, the ion implantation mask for forming the N-type layer 4a to be a low concentration source / drain layer and the mask for forming a thin oxide film (to be formed later) are the same mask. As a result, the number of steps is reduced.

Next, as shown in FIG. 4, after removing the photoresist layer 3, the whole surface is oxidized by a thermal oxidation method to
Second oxide film (thin oxide film) 5 having a thickness of about 0 °
Is formed on the N-type layers 4a and 4b from which the first oxide film 2 has been removed. This oxidation further increases the thickness of the first oxide film 2. A step h1 occurs between the first oxide film 2 and the second oxide film 5.

Next, as shown in FIG. 5, a polysilicon layer 6 and a silicon nitride film (Si 3 N 4) 7 are
It is formed by a method. The thickness of the polysilicon layer 6 is 50
0 ° to 1000 °, the thickness of the silicon nitride film 7 is 7
It is about 00-1000 °. Here, the polysilicon layer 6 is a buffer layer at the time of LOCOS oxidation, and suppresses bird's beak. The silicon nitride film 7 is an oxidation-resistant film at the time of LOCOS oxidation. On the surface of the silicon nitride film 7, a surface step h2 reflecting the step h occurs between the first oxide film 2 and the second oxide film 5. This surface step is approximately equal to the thickness difference between the first oxide film 2 and the second oxide film 5.

In the present invention, the polysilicon layer 6, the silicon nitride film (Si3
N4) Mask alignment for patterning 7 is performed. Then, as shown in FIG. 6, a photoresist layer PR is formed so as to expose the formation region of the field oxide film.

Then, the polysilicon layer 6 / silicon nitride film 7 in the transistor formation region is removed by dry etching, and thermally oxidized (LOCO) at a temperature of about 1000 ° C.
S oxidation step), and a field oxide film (LOCOS oxide film) for separating between transistors as shown in FIG.
8 is formed.

In this manner, even when there is no Si step, mask alignment can be performed using the surface step h2, and the field oxide film (LOCOS oxide film) 8 can be formed by selective oxidation. Further, the N-type layer 4a serving as a low-concentration source / drain layer is, as apparent from the above description,
The first oxide film 2 and the second oxide film 5 are formed in alignment with the position of the step h1. Therefore, the field oxide film (LOCOS oxide film) 8 formed by masking with reference to the surface step h2 reflecting the step h1 is precisely masked with the N-type layer 4a serving as a low concentration source / drain layer. A match is made.

In FIG. 7, a region for forming a high-breakdown-voltage transistor and a region (not shown) for forming a P-channel type normal-breakdown-voltage transistor are covered with a photoresist layer 9.
Boron ions ( ¹¹ B +) are ion-implanted into the formation region of the channel type normal breakdown voltage transistor. Boron ion ( ¹¹
B +) is injected so as to overlap the N-type layer 4b. At this time, the ion implantation amount is 1.5 × 10 ¹³ / cm ² and the acceleration energy is 160 KeV.

Next, the photoresist layer 9 is removed and 110
Thermal diffusion is performed at 0 ° C. for about 3 hours. Then, as shown in FIG. 8, N-type layer 4b is compensated by boron, and P-well region 10 is formed. N-type layer 4a
Are further deeply diffused into the N-type source layer 11 and the N-type drain layer 12 of the N-channel high breakdown voltage transistor. Further, since boron ions ( ¹¹ B +) are not implanted into the formation region (not shown) of the P-channel type normal breakdown voltage transistor, the N-type layer 4 b is deeply diffused as it is,
An N-type well region (not shown) is formed.

Next, as shown in FIG. 9, a photoresist layer 13 is formed. The photoresist layer 13 has an opening 13
a is formed, and boron ions ( ¹¹
B +) ions are implanted to form a P-type implanted layer for adjusting the threshold voltage in a part of the channel region 15.

In the conventional example, the ion implantation for adjusting the threshold voltage is performed over the entire transistor forming region. In this embodiment, however, the N− type source layer 11 and the N− type drain layer 12 are formed. The implantation is limited to the center of the channel region 15 so as not to overlap. Thereby, when the N − -type source layer 11 and the N − -type drain layer 12 are diffused by the subsequent heat treatment, boron is prevented from compensating, and the diffusion of phosphorus is promoted.

Thereafter, as shown in FIG. 10, the photoresist layer 13 is removed, a polysilicon layer is deposited by an LPCVD method, and after phosphorus doping, patterning is performed to form gate electrodes 16a and 16b. The gate electrode 16a is a gate electrode of a high breakdown voltage transistor,
Is formed on the gate oxide film 2 (thick oxide film). The gate electrode 16b is a gate electrode of a normal breakdown voltage transistor, and is formed on the second gate oxide film 5 (thick oxide film). Next, high concentration source / drain layers are formed by ion implantation of arsenic ions (75As +). Thus, the N + type source layer 1 of the normal breakdown voltage transistor
7, N + type drain layer 18, N + of high breakdown voltage transistor
A source layer 19 and an N + drain layer 20 are formed.

As described above, the ion implantation is performed by the second acid
Since it is performed through the oxide film 5 (thin oxide film),
Source / drain layers for transistors and high voltage transistors
It can be formed simultaneously. The ion at this time
Injection volume is 5 × 10^Fifteen/ Cm ^Two, Acceleration energy is 70
KeV.

After the ion implantation, an annealing process for activating the source / drain layers may be performed. Thereafter, an interlayer insulating film such as BPSG is deposited by LPCVD, and BPSG flow processing is performed. By these heat treatments, the N− type source layer 11 and the N− type drain layer 12 are formed.
Redistribution occurs. In this embodiment, since the formation range of the P-type injection layer 14 for adjusting the threshold voltage is limited to a part of the channel region 15, the N- type source layer 11 and the N-type
Re-diffusion of the type drain layer 12 is promoted.

[0035]

As described above, according to the present invention,
In a method for manufacturing a semiconductor device in which a normal breakdown voltage transistor and a high breakdown voltage transistor are formed on the same semiconductor substrate, a method of manufacturing
Even when there is no i-level difference, it is possible to perform mask alignment for forming a field oxide film without adding a step of forming a Si level difference.

Further, the field oxide film formed by the selective oxidation is formed in alignment with the semiconductor layer, and the mask alignment accuracy is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shinya Enomoto 3000 Chiya Koyo, Ojiya-city, Niigata Prefecture Niigata Sanyo Electronics Co., Ltd. (72) Inventor Masaaki Cotton 3000 Chiya Ko, Ojiya-shi, Niigata Niigata Sanyo Electronics Co., Ltd. F term (reference) 4M108 AA02 AA20 AB04 AB14 AC39 AC50 AD13 5F048 AA09 AC06 BA01 BB06 BB16 BD04 BE03 BG12 DA05 DA10 DB06

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device in which a normal breakdown voltage transistor and a high breakdown voltage transistor are formed on the same semiconductor substrate, wherein a step of forming a first oxide film formed on the semiconductor substrate; Forming a photoresist layer having an opening on the film, selectively removing the first oxide film; and thermally oxidizing the entire surface to form a first oxide film in a region where the first oxide film has been removed. A step of forming a second oxide film having a smaller thickness than the oxide film; a step of forming an oxidation-resistant film on the first and second oxide films; and a step between the first and second oxide films A step of performing a mask alignment for patterning the oxidation-resistant film using: a step of patterning the oxidation-resistant film; and a step of performing selective oxidation using the patterned oxidation-resistant film. Characterized by Method of manufacturing a conductor arrangement. 2. The method according to claim 1, further comprising the step of forming a semiconductor layer by performing ion implantation on the semiconductor substrate using the photoresist layer having the opening as a mask. . 3. The method according to claim 2, wherein said semiconductor layer is thermally diffused to form a source layer and a drain layer of a high breakdown voltage transistor.