JP2001066350A - Test method for integrated circuits - Google Patents

Abstract

(57) [Problem] To easily perform a unit test of an integrated circuit connected to a peripheral circuit such as an LSI. SOLUTION: A mode selection control circuit C is provided between a core logic CL of an LSI 100 to be tested and an external connection terminal thereof, and in a test mode, a fixed value set in advance instead of data input to the LSI 100 Is output to the core logic CL, and the output signal from the core logic CL is output to the connected peripheral circuit instead of a preset fixed value. If a value is set as a fixed value that allows the LSI 100 to be maintained in a state before signal transmission / reception between the peripheral circuit and the LSI 100 after power-on to the printed circuit board, the peripheral circuit and the LSI The state is separated from the LSI 100. Then, in this state, a scan input signal is input, and a test is performed by a scan test method using the scan flip-flop of the mode selection control circuit C and the scan flip-flop FF provided in the core logic CL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (LS)
I) and the like on a printed circuit board on which a plurality of components are mounted.

[0002]

2. Description of the Related Art Conventionally, as a test method for performing a test for confirming the function of an integrated circuit or diagnosing a failure, etc.
A function test method, a scan test method, a boundary scan test method, and the like are known. In the function test method, for example, as shown in FIG. 9, a test probe is connected to an input terminal, an output terminal, and an input / output terminal of an LSI 100 to be tested, and according to a test vector prepared in advance. This is a method for performing an LSI functional test. By using this method, a function check or a failure test of the LSI is performed.

In the scan test method, for example, as shown in FIG. 10, scan flip-flops are provided in a logic circuit inside the LSI 100, and these scan flip-flops are connected to each other to operate as a shift register during a test. The serial data is written into the scan flip-flop using this shift register, and the serial data is read from the scan flip-flop.

A test vector prepared in advance for input terminals and input / output terminals used in normal operation is set, and based on these test vectors, output data of output terminals and input / output terminals, and input data and output data of serial data. Thus, a failure test of the LSI is performed.
There are test methods such as a full scan and a partial scan depending on a range in which a shift register is configured by flip-flops.

Further, the boundary scan test method is a test method standardized by IEEE1149.1. For example, as shown in FIG.
When testing alone, the LS to be tested
A boundary scan register (boundary scan cell) is arranged for each of the input terminal, output terminal, and input / output terminal of I100, and each input terminal and output of LSI 100 is input using input data consisting of serial data for this boundary scan register. Terminals and signals at input / output terminals are controlled, and a test is performed based on output data output from a boundary scan test terminal via each boundary scan register.

[0006]

The above-mentioned conventional test method is effective in a case where a test is performed by an LSI alone. However, for example, when a plurality of LSIs are mounted on a printed circuit board and a unit test of the LSIs is performed in a state where the LSIs are connected, various problems occur when the above-described conventional test method is used.

That is, when the function test method is used, in order to apply this method, a test probe is connected to each of the input terminal, the output terminal, and the input / output terminal of the LSI to be applied to apply or monitor a signal. There is a need. However, in a printed circuit board or the like where a plurality of LSIs are arranged and connected to each other, when the power is turned on,
Almost simultaneously, the connected LSIs start transmitting and receiving signals to and from each other. Therefore, an input signal from the tester device for testing the LSI to be tested or an output signal corresponding to the input signal is collided with an input signal or an output signal from the connected LSI connected to the LSI to be tested. However, there is a problem that the LSI cannot be tested.

[0008] This causes the same problem even when the scan test technique is used. In contrast, when using the boundary scan test method, unlike when using the function test method or the scan test method,
If the LSI to which the LSI is connected is an LSI compatible with the boundary scan test, the input signal to the LSI can be controlled. For example, as shown in FIG.
By connecting a boundary scan register provided for each LSI on the printed circuit board, outputting data for a scan test from a test device, and extracting a response signal, a test of the entire printed circuit board can be performed. By bypassing an LSI other than the LSI to be tested, a unit test of only the LSI to be tested can be performed.

However, the LSI to which the LSI to be connected is connected
Is an absolute condition that it supports the boundary scan test method, and since all test data must be created as serial data, the number of test patterns becomes enormous, and it is necessary for testing an LSI to be tested. There is a problem that time is enormous. Therefore, the present invention has been made in view of the above-mentioned unsolved problems of the related art. Even if the integrated circuit is connected to a peripheral circuit such as an LSI, an integrated circuit capable of easily performing a unit test is provided. It is intended to provide a method for testing a circuit.

[0010]

In order to achieve the above object, a method for testing an integrated circuit according to claim 1 of the present invention comprises:
A test method for an integrated circuit including a scan test circuit for performing a scan test and performing a test of an integrated circuit connected to a peripheral circuit, wherein a test is performed between the integrated circuit and the peripheral circuit during a test. A fixed value conversion circuit (corresponding to the logic circuit 10) for changing a signal transmitted and received by a fixed value signal for maintaining the integrated circuit in a predetermined state;
A test data input circuit (corresponding to the boundary scan cell 20) configured to include at least a scan flip-flop and for applying test data for the scan test to the integrated circuit, provided in the integrated circuit;
The scan test is performed by applying test data to the scan test circuit and the test data input circuit with the fixed value conversion circuit replacing a signal transmitted and received between the integrated circuit and the peripheral circuit with the fixed value signal. Is executed.

According to the first aspect of the present invention, at the time of test execution, a signal transmitted and received between the peripheral circuit and the integrated circuit is converted into a fixed value signal for maintaining the integrated circuit in a predetermined state by the fixed value conversion circuit. Can be replaced by That is, the fixed value signal is input to the integrated circuit instead of the signal from the peripheral circuit, and the fixed value signal is output to the peripheral circuit instead of the signal from the integrated circuit. Here, these fixed value signals are set to values that maintain the state when the integrated circuit is not connected to the peripheral circuit,
That is, for example, if the impedance is set to a high impedance or a value (a low-level or high-level value) in which the integrated circuit and the peripheral circuit are connected but the integrated circuit and the peripheral circuit do not cause a state change or a signal change, Since the integrated circuit and the peripheral circuit do not exchange signals, the core logic surrounded by the fixed value conversion circuit of the integrated circuit is separated from the peripheral circuit.

In this state, test data is applied to the test data input circuit and the scan test circuit,
A scan test is performed by the scan test circuit based on data applied to the integrated circuit by the test data input circuit and the test data, and a test of the integrated circuit is performed based on output data from the scan test circuit.
At this time, during the test, since the integrated circuit maintains a state of being separated from the peripheral circuit, a signal transmitted / received between the peripheral circuit and the integrated circuit does not collide with test data to the integrated circuit. , A scan test can be performed.

According to a second aspect of the present invention, there is provided a method of testing an integrated circuit including a scan test circuit for executing a scan test and performing a test of an integrated circuit connected to a peripheral circuit. A fixed value conversion circuit for changing a signal transmitted and received between the integrated circuit and the peripheral circuit to a fixed value signal for maintaining a preset integrated circuit in a predetermined state during a test execution; Wherein the scan test is performed with the fixed value conversion circuit replacing the signal transmitted and received between the integrated circuit and the peripheral circuit with the fixed value signal.

According to the second aspect of the present invention, the fixed value conversion circuit is provided on the peripheral circuit side, that is, between the peripheral circuit or the peripheral circuit and the integrated circuit. The signal is output to the peripheral circuit instead of the fixed value signal in the fixed value conversion circuit, and the signal from the peripheral circuit to the integrated circuit is output to the integrated circuit instead of the fixed value signal in the fixed value conversion circuit. Here, these fixed value signals are values that maintain the state when the integrated circuit is not connected to the peripheral circuit, that is, for example, high impedance, or the integrated circuit and the peripheral circuit are connected, but the integrated circuit and the peripheral circuit are connected. If the peripheral circuit and the peripheral circuit are set to a value that does not cause a state change or a signal change (low-level or high-level value), the integrated circuit and the peripheral circuit do not exchange signals.
The core logic surrounded by the fixed value conversion circuit of the integrated circuit is in a state of being separated from peripheral circuits.

In this state, test data is applied to the external connection terminals of the scan test circuit and the integrated circuit to perform a scan test, and a unit test of the integrated circuit is performed based on output data from the scan test circuit based on the test data. Done. At this time, during the test, since the integrated circuit maintains a state of being separated from the peripheral circuit, a signal transmitted and received between the integrated circuit and the peripheral circuit does not collide with the test data, and the scan test is performed. It becomes possible.

[0016]

Embodiments of the present invention will be described below. FIG. 1 is a schematic configuration diagram showing an example of a test circuit to which an integrated circuit test method according to the present invention is applied. In FIG. 1, reference numeral 100 denotes an LSI to be tested, which is an integrated circuit to be tested, and peripheral circuits such as an LSI (not shown) are connected to the LSI to be tested 100. Also, this L
The SI 100 includes a test apparatus 1 for performing this test.
10 are connected. The LSI 100 is provided with the LSI 10 in the test scan method shown in FIG.
0, a core logic C including a combinational circuit L and a scan flip-flop FF for a scan test.
L is provided, and each of the external connection terminals is
A mode selection control circuit C including a scan flip-flop is provided. The scan flip-flop of each mode selection control circuit C and the scan flip-flop FF provided in the core logic CL are connected, and the scan flip-flop of the terminal mode selection control circuit C is connected to the terminal for scan test input signal. A series of scan chains are formed by being connected to t _SIN and a scan test output signal terminal t _SOUT, and a known scan test is performed based on a scan test input signal input to the scan test input signal terminal t _SIN. It has become.

The mode selection control circuit C operates in response to a mode selection signal from the test apparatus 110 input to a mode selection control signal input terminal t _M for inputting a mode selection signal. The mode selection control circuit C for input signals for inputting signals from the external connection terminals outputs the input data input to the external connection terminals as it is, and outputs the signals to the external connection terminals. The control circuit C outputs the output from the core logic CL to the external connection terminal as it is.

On the other hand, when the test mode is designated, the mode selection control circuit C for the input signal outputs a preset fixed value in place of the input data input to the external connection terminal, and outputs the fixed value for the output signal. The mode selection control circuit C outputs a preset fixed value to the external connection terminal instead of the output from the core logic CL. In the test mode, the scan test operation is performed based on the scan test input signal input to the scan test input signal terminal t _SIN .

The test apparatus 110 switches the mode selection control circuit C between a normal mode and a test mode according to a mode selection signal. In the test mode, the test apparatus 110 converts a preset scan test input signal to a scan test input signal terminal t _SIN. Then, a scan test output signal is extracted from the scan test output signal terminal t _SOUT, and based on the scan test input signal and the scan test output signal, the function check and failure diagnosis of the LSI 100 are performed. The scan test input signal is formed by a test pattern that makes the fixed value input to the logic circuit 10 in FIG. 2 valid in the test mode.

FIG. 2 shows the configuration of the mode selection control circuit C. As shown in FIG. 2, the input terminal t _IN1, t _IN2 of the LSI 100, an output terminal t _{OU T1,} t _OUT2 is
IO buffer cells B _IN1 , B _IN2 , B _OUT1 , B
_OUT2 and mode selection control circuits C _IN1 , C _IN2 , C _OUT1 ,
These are connected to the core logic CL via C _OUT2 ,
The mode selection control circuits C _IN1 , C _IN2 , C _OUT1 , and C _OUT2 have the same configuration.

FIG. 3 shows a truth table of the mode selection control circuit C. As shown in FIG. 3, in the normal mode, the mode selection control circuit C outputs the input data input to the mode selection control circuit C to the core logic CL as it is. On the other hand, in the test mode, during a non-scan operation, a designated signal value is output regardless of the data value of input data that is input. During the scan operation, a scan test is performed according to the input scan test input signal, a signal corresponding to the scan test result is output to the core logic CL, and an output terminal of the scan test output signal is output.

The fixed value output in the test mode corresponds to a signal input to or output from the core logic CL in an initial state, which is a state before the start of signal transmission / reception with another peripheral circuit after power-on. In the test mode, the core logic CL is maintained in an initial state after power is turned on and before transmission / reception of a signal with another peripheral circuit is started.

That is, as shown in FIG. 3, with respect to the input signal to the core logic CL, when the operation of the core logic CL maintains the initial state when the signal value “0” is applied, For the signal (A), as shown in “0 output”, “0” is output as a fixed value, and when the operation of the core logic CL maintains the initial state when the signal value “1” is applied, As shown in "1 output" for input signal (B), "1" is output as a fixed value. When the signal value is “0”
Alternatively, if the processing of the core logic CL maintains the initial state even when it is “1”, it is set as a fixed value as shown in “0/1 output” for the input signal (C) according to the signal value of the input data. It is fixed to either “0” or “1”.

On the other hand, regarding the output signal to the peripheral device,
When the core logic CL outputs the signal value “0” in the initial state, “0” is output as a fixed value as shown in (A) “0 output” for the output signal, and the core logic CL is in the initial state. When outputting the signal value "1", "1" is output as a fixed value as shown in "1 output" for output signal (B).

The output from the LSI 100 is output via IO buffer cells B _OUT1 and B _OUT2 .
When high impedance is output as an output from the LSI 100, the configuration shown in FIG. 4A or 4B may be used. That is, for example, in FIG. 2, when outputting high impedance from the output terminal t _OUT1 , as shown in FIG. 4A, the IO buffer cell B _OUT1 is constituted by a three-state output buffer cell, and the mode selection control is performed. The output of the circuit C _OUT1 is output to the output terminal t _OUT1 via the three-state output buffer cell. As a control signal (output enable signal) of the three-state output buffer cell, another mode selection control circuit,
For example, the output signal of C _OUT2 is used.

Also, for example, in FIG.
_OUT1Are input / output terminals to which input / output bidirectional signals are applied
t_{IN / OUT}In the case of, as shown in FIG.
4 (a), IO buffer cell B_OUT1Threes
Mode selection control circuit
C_OUT1Output through a three-state output buffer cell
Input / output terminal t_{IN / OUT}Output to the three-state output
Buffer cell control signal (output enable signal)
As another mode selection control circuit, for example, C_OUT2No m
The output signal of the node selection control circuit is used. And the IO bag
Facel B_OUT1And input / output terminal t_{IN / OUT}Between and mode selection
Control circuit C_INBetween IO buffer cell B _IN, This
IO buffer cell B_INAnd the IO buffer cell B_OUT1
Constitutes an input / output buffer, and the input / output terminal t_{IN / OUT}Around
The signal input from the side circuit is transferred to the IO buffer cell B._IN,
Mode selection control circuit C_INOutput to core logic CL via
I do.

As shown in FIG. 2, the mode selection control circuit C includes a logic circuit 10 as a fixed value conversion circuit,
The circuit includes a boundary scan cell 20 as a test data input circuit to which an output of the logic circuit 10 is input. In the case of the mode selection control circuit C on the signal input side, the logic circuit 10 includes a mode selection signal and the LSI 100
In the case of the mode selection control circuit C on the signal output side, the mode selection signal and the LSI 100
And the output data addressed to the peripheral circuit. As shown in the truth table of FIG. 3, the input data or the output data input to the logic circuit 10 is output in the normal mode, and the fixed value is output in the test mode. You. For example, when "0" is designated as the fixed value, as shown in the truth table of FIG. 5, when the mode selection signal is "0", the output is output as "0". For example, an AND circuit Etc.

Then, the input terminal t_IN1, T_IN2Connected with
Mode selection control circuit C_IN1, C _IN2Then, the logic
The circuit 10 includes a data input signal applied to an input terminal.
IO buffer cell B_IN1, B_IN2Is entered via
In both cases, the mode selection signal input terminal t_MMode applied to
Selection signal is IO buffer cell B_MWill be entered via
Swelling.

On the other hand, the output at terminal t _OUT1, mode selection control circuit is connected to the _{t OUT2 C OUT1, C OU T2} , the logic circuits 10, the mode selection signal and the input and output signals of the boundary scan 20 The output is supplied to output terminals t _OUT1 and t _OUT1 via IO buffer cells B _OUT1 and B _OUT2.
Output to _OUT2 . The boundary scan cell 20 is a well-known device conforming to the IEEE1149.4 standard. As shown in FIG. 6, for example, a selector for switching between input data input to the boundary scan cell 20 and test data is used. A scan flip-flop for inputting a scan signal, a scan flip-flop for outputting a scan signal, and a selector for switching between input data and test data and outputting the data from the boundary scan cell 20. Is controlled based on this control signal.

Then, as shown in FIG.
Scan flip-flop in control circuit C and core logic
Scan flip-flop FF provided in the clock CL
The scan input signal connected to the LSI 100
Is the mode selection control circuit C _IN2, C_IN1, Core logic
CL, mode selection control circuit C_OUT2, C_OUT1In the order of
Scan output signal via can flip-flop FF
Output terminal t_SOUTIs output from

Next, the operation of the above embodiment will be described.
Now, as shown in FIG. 7, the LSI 100 is placed on a printed circuit board and connected to another LSI. In this state, when testing the LSI 100,
As shown in FIG. 1, each external connection terminal and the test device 110 are connected by a test probe. When the power supply to the printed circuit board is turned on, the test apparatus 110 sets the mode selection signal to “0”, and when a test mode is instructed, the mode selection control signal input to each mode selection control circuit C becomes “0”. Therefore, the mode selection control circuit C operates according to the test mode, and outputs a preset fixed value as shown in the mode selection control signal truth table of FIG. For example, the mode selection control circuit C _IN2 in FIG.
In the case of C _IN1 , C _OUT2 and C _OUT1 , a fixed value “0” is output.

At this time, when the power to the printed circuit board is turned on, each LSI starts operating, and after performing its own initial setting processing and the like, starts sending and receiving signals with other LSIs. Since the fixed value in each mode selection control circuit C of the LSI 100 is set to a value that maintains the mode selection control circuit C in a state before starting signal transmission / reception with another LSI after the power is turned on, the LSI 100 , Other LS
It operates by recognizing that it is in a state in which it does not exchange signals with I. In other LSIs, it maintains the state before the LSI 100 starts to exchange signals, and does not exchange signals. Recognizes and operates. Therefore, the LS
I100 is in a state where it does not exchange signals with other LSIs, that is, is in a state of being separated from other LSIs.

In this state, by outputting a scan test input signal from the test apparatus 110,
The scan test input signal _passes from the scan test input signal terminal t _SIN to the scan test output signal terminal t _SIN through the scan flip-flop of each mode control circuit C and the scan flip-flop FF in the core logic CL.
Output from _SOUT to test apparatus 110.

At this time, the LSI 100 is connected to another LSI.
In this state, the signal is not transmitted and received, and therefore, the transmitted / received signal transmitted / received between the LSI 100 and another LSI does not collide with the scan test signal. When the mode selection signal is switched from this state to the normal mode, the mode selection control circuit C relays the data input to the external connection terminal to the core logic CL and transfers the data output from the core logic CL to the external logic. Since relay to the connection terminal, core logic CL and other LS
Signal exchange with I is started. Therefore, in this state, by extracting the signal of each external connection terminal, it is possible to monitor the signal transmitted and received between the LSI 100 and another LSI.

As described above, even when the test is performed only on the LSI 100 while being connected to another LSI, the test using the scan test method can be performed without causing a signal collision or the like. Compared with the test method, the number of test patterns can be reduced, and the time required for the test can be reduced.

The mode selection control circuit C is connected to the LSI 1
00, it is only necessary to output a mode selection signal for controlling the mode selection control circuit C from the test apparatus 110, so that it can be easily realized. Further, only the LSI 100 and the test apparatus 110 need to be changed, and there is no need to change the LSI connected to the LSI 100.

In the above embodiment, the LS
The case where the mode selection control circuit C is provided in the I100 has been described. However, the present invention is not limited to this. The mode selection control circuit C may be provided on the side of the LSI connected to the LSI. It may be provided between an LSI and an LSI connected to the LSI. That is,
As shown in FIG. 8, LSI1 to L1 connected to the LSI to be
The external connection terminal of SI3 for transmitting and receiving signals to and from the LSI
For example, as in the logic circuit 10, there is provided a mode switching circuit for switching between a signal transmitted / received between the core logic of the LSI and the LSI and a fixed value according to a mode selection signal and outputting the fixed value. When the power is turned on, the test apparatus 110 outputs a mode selection signal (“1” in FIG. 8) for instructing a test mode to each of the LSIs 1 to 3, and
In the mode switching circuit of SI3, the signal from the core logic to the LSI is output instead of a fixed value, and the signal from the LSI to the core logic is output instead of a fixed value. Then, by setting each fixed value to a value that allows the LSI to be maintained in the initial state in the same manner as described above, the LSI to be processed becomes each of the LSIs 1 to
In this state, the scan test can be performed by outputting a scan test signal including a test pattern for validating a fixed value input to the LSI under test from the test apparatus 110 in this state. it can.

In the above embodiment, the LS
A case has been described in which I100 is set to a fixed value so as to maintain the state before signal transmission between the LSI 100 and the peripheral circuit is started after the power is turned on. However, the present invention is not limited to this. It is also possible to set a value that allows the peripheral circuit to be maintained in a specific state.

Further, in the above-described embodiment, a case has been described in which the test of the LSI 100 is performed before the transmission and reception of signals between the LSI 100 and peripheral circuits after the power is turned on, but the present invention is limited to this. Instead of controlling the mode selection control circuit C, the peripheral circuit and the LSI 100
Is fixed at a desired timing to a predetermined value at the desired timing, so that the LS
A test of I100 can be performed.

In the above embodiment, the LS
Although the case where the I100 is connected to the LSI has been described, the present invention is not limited to this, and any circuit such as an IC that is connected to the LSI can be applied. Furthermore, the case where an LSI is used as an integrated circuit to be tested has been described, but the present invention is not limited to this, and it is also possible to perform tests on ICs and the like.

[0041]

As described above, according to the first aspect of the present invention,
According to the integrated circuit test method of the present invention, the signal transmitted and received between the integrated circuit and the peripheral circuit is changed to a fixed value signal at the time of test execution. By setting a fixed value signal that keeps the integrated circuit from being performed, the integrated circuit can be separated from the peripheral circuit, and even if the integrated circuit and the peripheral circuit are connected, the integrated circuit alone A scan test can be performed in the same manner as when a test is performed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an example of a test apparatus to which an integrated circuit test method according to the present invention is applied.

FIG. 2 is a circuit diagram illustrating a schematic configuration of a mode selection control circuit.

FIG. 3 is a truth table of the mode selection control circuit.

FIG. 4 is an example of a circuit configuration when an output signal is fixed at a high impedance.

FIG. 5 is a truth table illustrating an example of a logic circuit.

FIG. 6 is a circuit diagram illustrating an example of a boundary scan cell;

FIG. 7 is an example of a printed circuit board for explaining the operation of the present invention.

FIG. 8 is a schematic configuration diagram for explaining another embodiment of the present invention.

FIG. 9 is a schematic configuration diagram for explaining an outline of a function test method.

FIG. 10 is a schematic configuration diagram for explaining an outline of a scan test method.

FIG. 11 is a schematic configuration diagram for describing an outline of a unit test by a boundary scan test method.

FIG. 12 is a schematic configuration diagram for describing an outline of a boundary scan test method.

[Explanation of symbols]

 C mode selection control circuit L combination circuit CL core logic FF flip-flop 10 logic circuit 20 boundary scan cell 100 LSI under test 110 test equipment

Claims (2)

[Claims] 1. A test method for an integrated circuit, comprising: a scan test circuit for executing a scan test and for performing a test on an integrated circuit connected to a peripheral circuit. A fixed value conversion circuit for changing a signal transmitted to and received from a peripheral circuit to a fixed value signal for maintaining the integrated circuit in a predetermined state; and test data for the scan test, comprising at least a scan flip-flop. And a test data input circuit for applying the signal to the integrated circuit, and the fixed value conversion circuit replaces a signal transmitted and received between the integrated circuit and the peripheral circuit with the fixed value signal. The scan test is performed by applying test data to the scan test circuit and the test data input circuit in a state. A method for testing an integrated circuit, comprising: 2. A test method for an integrated circuit, comprising: a scan test circuit for performing a scan test, and for performing a test on an integrated circuit connected to a peripheral circuit. A fixed value conversion circuit for changing a signal transmitted to and received from a peripheral circuit to a fixed value signal for maintaining a preset integrated circuit in a predetermined state, provided on the peripheral circuit side; A test method for an integrated circuit, wherein the scan test is performed in a state where a signal transmitted and received between the control circuit and the peripheral circuit is changed to the fixed value signal.