JP2001053761A - Testing method for atm switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test an ATM switch precisely in a short time by preset connection for test. SOLUTION: The ATM switch 1 is provided with input/output ports p1P1 to p8P8. An output port is connected with an input port of each input/output port by an external physical link 7. An internal path 8 is the logical one to reach each output port from each input port. A cell is inputted from the input port by a cell generator for test and the cell is outputted to the output port through the internal path 8 and the external physical link 7. The outputted cell is evaluated by an evaluating device 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated services digital network.
The present invention relates to a test method of an ATM switch for testing the function of an ATM switch frequently used in a transmission or switching system.

[0002]

2. Description of the Related Art An ATM switch has a switching function of receiving a cell from a multiplexed communication path and sending the cell to a specified communication path according to information indicated by a cell header. The ATM switch plays an extremely important role in the operation of the ISDN network, and maintenance and inspection and evaluation of its functions are indispensable to the network management service business. The ATM switch is provided with a number of input ports and output ports. When evaluating the function of the ATM switch, connect a tester to the port to be tested,
The cell input from this tester is received at a designated output port, and the quality of the output cell is evaluated.

[0003]

However, the above-mentioned prior art has the following problems to be solved.
In testing an ATM switch having a large number of input ports and output ports, it is necessary to prepare ATM test machines for the number of input ports, for example, and to evaluate the quality of output cells for all output ports. Become. Since the input port and the output port can be freely connected to each other through the internal link, the number of combinations is large, and the testing and evaluation of all the switching functions required enormous test time. The ATM switch has many queues (queues) and cell buffer functions for traffic control. It is desired to develop a practical means for individually evaluating these performances.

[0004]

The present invention employs the following structure to solve the above problems. <Configuration 1> An external physical link connecting the input port and the output port of the ATM switch and an internal path formed between the input port and the output port inside the ATM switch are set in advance. To realize a test connection, input a test cell from a preset input port, monitor and evaluate the test cell output from a preset output port, and test the function of the ATM switch. A test method for an ATM switch, characterized in that:

<Configuration 2> In the test method for an ATM switch described in Configuration 1, a plurality of test cells input from an input port are individually and sequentially subjected to different internal paths and external physical links once each. A test method for an ATM switch, wherein a connection is set so as to pass through and output to an output port.

<Structure 3> In the method of testing an ATM switch described in Structure 1, a plurality of test cells input from an input port are provided in a plurality of internal cells formed between any of the input ports and the output port. A method for testing an ATM switch, wherein a connection is set so as to be output to an output port via one of paths.

<Structure 4> In the test method for an ATM switch described in Structure 1, the input port and the output port are connected by an external physical link such that cells output from all output ports are input to any of the input ports. Are connected to each other, and a connection is set such that cells input from an input port pass through all external physical links and internal paths once each and are output to an output port. Test method for ATM switch.

<Structure 5> In the test method of the ATM switch described in Structure 1, the jamming route is set so that the jamming cell input from any input port passes through any internal path and external physical link. And a connection is set such that a test cell input from a preset input port passes through all or a part of the interference route and is output to an output port.
Test method for TM switch.

<Structure 6> In the test method for an ATM switch described in Structure 1, a disturbing cell input from any input port passes through any internal path and external physical link and returns to the original input port. To form a ring-shaped jamming route so that a test cell input from a preset input port passes through all or part of the jamming route and is output to an output port. A test method for an ATM switch, characterized in that:

<Structure 7> In the test method of the ATM switch described in Structure 1, the multiplicity of the internal paths is increased by increasing or decreasing the number of internal paths formed between any of the input ports and the output ports. A test method for an ATM switch, characterized in that the function of the ATM switch is tested by monitoring cells output from a preset output port while changing over time as set in advance.

<Configuration 8> In the test method for an ATM switch described in Configuration 1, the transmission capacity of an arbitrary internal path is changed with time as set in advance, and cells output from a preset output port are changed. A method for testing an ATM switch, comprising monitoring and testing the function of the ATM switch.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. <Specific Example> FIG. 1 is an explanatory view of a test method of the present invention. The ATM switch 1 tested according to the present invention has, for example, eight input ports p1 to p8 as shown in FIG.
And eight output ports P1 to P8.
The test cell generator 3 is connected to the input port p1. Further, the detector 4 is connected to the output port P8.
And the evaluation device 5 are connected. Each output port and input port are connected to each other by an external physical link 7 composed of a communication cable or the like. Therefore, in this example, the cells output from all the output ports are input to the adjacent input ports, and all the input ports and the output ports are connected to each other in series in a line.

An ATM from the test cell generator 3
A test cell for evaluating the switch 1 is output. For example, the test cell is repeatedly input to the input port p1 of the ATM switch 1 at regular time intervals. For example, a serial number is added to the cell header of each test cell in the order of output. The connection is set so that the test cell is output from the output port P8 through the ATM switch 1 and detected by the detector 4.

The detector 4 is a device for detecting a cell output from the output port P8. The evaluation device 5 is a device for analyzing a cell detected by the detector 4 and evaluating quality and the like described later. The evaluation device 5 is configured by, for example, a personal computer or the like, and can output a result of the evaluation or output an operation control signal to the test cell generator 3 or the ATM switch 1. For example, the evaluation device 5 can request the test cell generator 3 to change the type of the test cell and the configuration of the header. Further, it is possible to request the ATM switch 1 to change its internal link, change the attribute data of each port, and the like.

FIG. 2 is a diagram illustrating an example of the configuration of an ATM switch. A general ATM switch has, for example, an internal configuration as shown in FIG. That is, the cell determination unit 11 that accommodates a predetermined number of input port groups PIN, and the queue control unit 1
2 and an output port group POU connected to the queue control unit 12 to output cells.

The cell determination unit 11 recognizes a cell header of a cell input from the input port group PIN, and determines which port to output to and what band path to pass. As a result of the determination, an appropriate queue is selected. The queue control unit 12 is provided with a large number of cell buffers for forming a queue (cell queue) corresponding to the output port. The queue control unit 12 has a function of sequentially taking out cells from the head of each queue and sending out the cells to the corresponding cell port. The priority of each queue is determined, and the head cell of the queue with the higher priority is output to the output port with the highest priority. The higher the capacity of the path, the higher the priority of the queue.

In the ATM switch as shown in FIG. 2, for example, it is necessary to test a function of determining a cell in the cell determination section 11, that is, a function of correctly recognizing a cell header and transferring the cell to an appropriate cell buffer. become. In addition, it is an object of the test whether the queue control unit 12 has a function of sending out the cells held in each cell buffer to the output port without any trouble. Also, the queue control unit 12
It is an object of the test to determine whether or not there is a function of sending out the cells held in the queue control unit 12 to the output port group without causing a transmission delay exceeding a specified level without any trouble.

Further, it is necessary to perform a test on whether a cell input from any port of the input port group PIN is output to a corresponding predetermined output port without error. The method shown in FIG. 1 reliably performs such an evaluation test in detail using fewer test cell generators.

FIG. 3 is a diagram for explaining a mode of a path. FIG.
The internal path 8 provided in the ATM switch 1 shown in FIG. (A)
Shows an example in which port P1 and port P7 are connected by a large-capacity path H1, and port P1 and port P8 are connected by a small-capacity path H2. The large-capacity path H1 transfers cells at high speed. Usually, the output port of the ATM switch is, for example, 1
A path having a transmission capacity of 50 MHz and using one output port can be set to an arbitrary capacity with this transmission capacity being the maximum value.

In the example shown in FIG. 3B, the input ports p1 to p1
A large-capacity path H1 and a small-capacity path H2 are formed for the output port P8. That is, any number of paths can be freely set between the same input port and output port.

FIG. 3C shows an example in which a high quality path H3 and a low quality path H4 are set. The port P1 and the port P7 are connected by a high-quality path H3. The port P1 and the port P8 are connected by a low-quality path H4. A high quality path is a path with a sufficiently low cell loss rate and cell delay. A low-quality path is a signal path that does not cause any problem even if the cell loss rate or the cell delay is increased. When testing the ATM switch 1 shown in FIG. 1, the internal path 8 can be set by a single or a plurality of such various types.

FIG. 4 is an explanatory diagram of a ring-type connection. A specific example of the external physical link will be described with reference to FIGS. The example shown in FIG. 4 schematically illustrates the configuration of the external physical link 7 shown in FIG. Open circles indicate a pair of input ports and output ports, and dashed lines inside the white circles indicate, for example, the input port p1 and the output port P1.
This is an internal link that connects

In the example shown in FIG. 4, as shown in FIG. 1, the output port P1 is connected to the input port p2, the output port P2 is connected to the input port p3, and the output port P3 is connected to the input port p4. Each port is connected in series in that order. In addition, between each port,
Each is connected to each other using an internal path set in advance for the test. The example of the solid line is an example of a ring-shaped external physical link. In addition, the output port P8 and the input port p1 in FIG. 4 can be connected by an external physical link to form a loopback.

FIG. 5 is an explanatory view of the connection of the port facing type. In this example, for example, ports P1 and P8, ports P2 and P3, ports P4 and P5, ports P6 and P7
Are opposed to each other to form a connection different from that in FIG. This is called a port facing type. In any case, in the present invention, various complicated connections can be freely realized using the external physical link and the internal path. Various connections such as a ring shape, a mesh shape, and a port facing type are also conceivable for the internal path.

FIG. 6 is a diagram illustrating a specific example of a connection employed in the test method according to the present invention. First, FIG. 6A shows the simplest example, for example, an internal link is formed from the input port p1 to the output port P1, and an external physical link is formed from the output port P1 to the input port p2.
An internal path is formed from the input port p2 to the output port P2, and the test cells are transmitted in this order.

For example, a plurality of test cells input from the same input port separately pass through different internal paths and external physical links in order, and are output to one output port provided with a detector. By doing so,
The function test of the ATM switch can be performed for a large number of connections at a time. This can be realized by setting a plurality of connections as shown in FIG. This eliminates the need to use a large number of the test cell generators 3 and the detectors 4 or to sequentially switch the ports connecting the test cell generators 3 and the detectors 4 during the test, which is efficient. Test.

FIG. 6B shows an example in which a plurality of internal paths are formed between the input port p1 and the output port P1 and between the input port p2 and the output port P2. Here, the first port is provided between the input port p1 and the output port P1.
There are three paths, a path, a second path, and a third path.
The first port is provided between the input port p2 and the output port P2.
There are three paths, a path, a second path, and a third path.
Here, the port on the input side of the pair of input / output ports p1P1 is called an input port p1, and the port on the output side is called an output port P1.

The cell input from the input port p1 first passes through the first path of the input / output port p1P1 and the first path of the input / output port p2P2, and returns to the input port p1 again via the external physical link 7. Then, the signal is output through the second path of the input / output port p1P1 and the second path of the input / output port p2P2, and returns to the input port p1 through the external physical link 7 again. Finally, input / output port p1P
1 and the third path of the input / output port p2P2. The output is received by the detector.

By multiplexing the internal paths in this manner, the characteristics of the ATM switch according to the degree of multiplexing between specific ports and the load factor can be tested and evaluated. In order to circulate the cells in a predetermined order in this manner, the attribute data of the cell header and the input / output ports may be controlled. It is possible to change the capacity of each of the first path, the second path, and the third path, or to increase or decrease the number of paths to increase or decrease the multiplicity or load factor, and to measure the dynamic characteristics of the ATM switch. Will be possible.

For example, input port p1-output port P2-
It is assumed that a connection such as an external physical link-input port p3-output port P5 is desired. Since the cell determination unit 11 (FIG. 2) of the ATM switch has a cell header rewriting function conventionally, it utilizes this function. The cell header of the cell first input to the input port p1 includes:
Information "input port p1-output port P2" is written. This cell is connected to the input port p3 via the path of the input port p1, the output port P2 and the external physical link.
, The cell determination unit 11 rewrites the information of the cell header as “input port p3−output port P5”. Thus, the cell is sent to output port P5. By repeating such processing, a free connection can be realized. Such control can be performed by providing information indicating the procedure of rewriting the cell header of the cell when the cell is input to which input port to the cell determination unit 11 in advance.

These conditions may be fixed from the start to the end of the test, or dynamic control for sequentially changing the conditions after the start of the test may be performed. That is, the multiplicity of the internal path or the like may be changed over time as set in advance, and the output cells may be evaluated. The connection as described above makes it possible to evaluate when a cell outputs various routes inside the ATM switch. Further, in an ATM switch, when traffic is large, it is desired to evaluate whether or not cells form an appropriate queue in a cell buffer.

FIG. 6C shows an example which enables such a test. In this example, a predetermined internal path is formed between the input / output ports p1P1, and a disturbing cell is input to the input port p1 together with the test cell. The jamming cell is
After passing between the input / output ports p1 and P1, the connection returns to the input port p1 again by the connection set up separately. That is, the connection of the interfering cell is set so as to repeatedly pass between the input / output ports p1P1. On the other hand, the test cell passes between the input / output ports p1P1 and is output. Of course, another complicated connection may be set.

As described above, by passing the obstructing cell on the route through which the test cell passes, the background traffic load becomes possible. That is, the background traffic load is applied to the foreground traffic that is actually evaluated, and the transmission characteristics can be more dynamically evaluated. Thus, it is possible to evaluate the separation characteristics and the like as to whether or not the test cell has been correctly taken out.

As generators for the interfering cell, CBR (Constant Bit Rate), VBR (Variable
Bit Rate) or the like can be used. As a result, various characteristics such as burst response characteristics and dynamic load fluctuation can be evaluated. In particular, if CBR is used, performance evaluation can be performed under approximately random arrival background load conditions. As described above, the ATM switch has a VC queue, a QoS,
Many cell buffers, such as control class queues, are provided for each connection or each connection group.
The configuration shown in FIG. 6C is suitable for individually testing the suitability of the cell buffer and the cell scheduling control.

Further, by setting the connection so that the cells pass through all the queues in the ATM switch and circulating the cells, the normality of all the queues can be tested in real time.

FIG. 7 shows a specific connection diagram of the test equipment. As shown in this figure, a large number of test cells 10 are output from the test cell generator 3 connected to the input port of the ATM switch 1 at regular time intervals. The test cell is transmitted through the internal paths 81 and 82 of the ATM switch 1 and the external physical links 71 and 72, and is finally output to the detector 4. Detector 4 observes the loss rate, destruction rate, transmission delay, etc. of this cell,
The performance of the ATM switch 1 is evaluated. The contents of the cells to be output are determined by the test cell generator 3, and the cell delay and the discard rate can be logically assumed in advance by the set connection. Therefore, the estimated value is compared with the actually output cells. This will enable qualitative and quantitative evaluations.

FIG. 8 shows a connection diagram (No. 2) of the test equipment. In this example, a test cell generator 3 and a jamming cell generator 6 are connected to the ATM switch 1. The jamming cell generator 6 may be externally attached to the ATM switch 1, or may be constituted by a preset circuit or the like that outputs a fixed cell already incorporated in the ATM switch 1 at a fixed cycle. . The interfering cell output from such an interfering cell generator 6 includes an internal path 84, an external physical link 73,
Through the internal path 85, the external physical link 74, the internal path 86, and the external physical link 75, the ATM switch 1 is repeatedly circulated. Thus, a predetermined background traffic is formed.

In this state, test cells are supplied from the test cell generator 3 to the ATM switch 1. The test cell includes the internal path 84, the external physical link 73, and the internal path 8
5, sent to the detector 4 via the external physical link 74 and the internal path 86. In this manner, the cell transmission characteristics of the ATM switch in the background traffic described above can be tested.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a test method of the present invention.

FIG. 2 is an explanatory diagram of a configuration example of an ATM switch.

FIG. 3 is an explanatory diagram of a pass mode.

FIG. 4 is an explanatory diagram of a ring connection.

FIG. 5 is an explanatory diagram of a port-facing connection.

FIG. 6 is an explanatory diagram of a connection example according to the present invention.

FIG. 7 is a connection diagram (1) of a test facility.

FIG. 8 is a connection diagram (part 2) of the test equipment.

[Explanation of symbols]

 Reference Signs List 1 ATM switch 3 Test cell generator 4 Detector 5 Evaluation device 7 External physical link 8 Internal path

Claims (8)

[Claims] 1. An external physical link connecting between an input port and an output port of an ATM switch and an internal path formed between the input port and the output port inside the ATM switch. A test cell is input from a preset input port, the test cell output from a preset output port is monitored and evaluated, and the function of the ATM switch is tested. A test method for an ATM switch, characterized in that: 2. The test method for an ATM switch according to claim 1, wherein the plurality of test cells input from the input port individually and sequentially pass through different internal paths and external physical links once each. A method for testing an ATM switch, characterized in that a connection is set such that the connection is output to an output port. 3. The ATM switch test method according to claim 1, wherein the plurality of test cells input from the input port are formed between a plurality of internal paths formed between any of the input ports and the output port. A method for testing an ATM switch, wherein a connection is set so as to be output to an output port via any one of the above. 4. The test method for an ATM switch according to claim 1, wherein the input port and the output port are connected by an external physical link such that cells output from all output ports are input to any one of the input ports. ATM connection characterized in that the connection is established so that cells input from an input port pass through all external physical links and internal paths once each and are output to an output port. Switch test method. 5. The test method for an ATM switch according to claim 1, wherein the jamming route is set such that the jamming cell input from any input port passes through any internal path and external physical link. An ATM switch, wherein the connection is set so that a test cell input from a preset input port passes through all or a part of the interference route and is output to an output port. Test method. 6. The ATM switch test method according to claim 1, wherein a jamming cell input from any one of the input ports passes through any one of the internal paths and the external physical link and returns to the original input port. In order to return, a ring-shaped interference route is formed, and a connection is established so that a test cell input from a preset input port passes through all or a part of the interference route and is output to an output port. A test method of an ATM switch characterized by setting. 7. The ATM switch test method according to claim 1, wherein the number of internal paths formed between any one of the input ports and the output ports is increased or decreased, thereby preliminarily increasing the multiplicity of the internal paths. A test method for an ATM switch, characterized in that a function of the ATM switch is tested by monitoring cells output from a preset output port while changing the time as set. 8. A method for testing an ATM switch according to claim 1, wherein the transmission capacity of an arbitrary internal path is temporally changed as set in advance, and a cell output from a preset output port is monitored. And testing the function of the ATM switch.