JP2001053558A - Operational amplifier - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide an operational amplifier that can be used as an operational amplifier even when a voltage difference between a high-potential power supply and a low-potential power supply is equal to or higher than the withstand voltage of a single MOS transistor. . SOLUTION: In an operational amplifier including a differential amplifier stage, a level shift stage, and an output stage, a first voltage clamp provided between a drive transistor on a high potential power supply side and an output terminal in the output stage. Circuit and a second transistor provided between the drive transistor on the low potential power supply side and the output terminal.
And a voltage clamp circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier which is formed on an integrated circuit by CMOS (complementary MOS transistor) and is used for a comparator of an analog signal and the like.
In particular, the present invention relates to an operational amplifier that operates at a voltage higher than the withstand voltage of a transistor included in the operational amplifier.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing a conventional operational amplifier 111.

A conventional operational amplifier 111 is described in a reference (IE
EE JOURNAL OF SOLID STATE CIRCUITS, SC-17, 1982, P
AUL R. GRAY and ROBERT G. MEYER, “MOS Operational
Amplifier Design A Tutorial Overview ”p. 969-98
This is the circuit described in 1.).

A conventional operational amplifier 111 includes a differential amplifier stage 10 that amplifies differentially according to an input voltage difference between a positive-phase input terminal 11 and a negative-phase input terminal 12, and the output voltage of the differential amplifier stage 10 is set to a level. It comprises a level shift stage 20 for shifting, and an output stage 30 which is turned on / off complementarily by the output of the level shift stage 20.

The differential amplifier stage 10 has an input N-channel M
An OS transistor (hereinafter referred to as “NMOS”) 13,
14, a NMOS 15 for a constant current source, and a P-channel MOS transistor for a load (hereinafter, referred to as “PMOS”)
16 and 17.

The level shift stage 20 has a high potential power supply VDD.
NMO connected in series between the low potential power supply VSS
It is constituted by S21 and S22.

The output stage 30 includes a PMOS 31 and an NMOS 32 connected in series between a high potential power supply VDD and a low potential power supply VSS.

In the conventional operational amplifier 111, when a positive input voltage is input to the positive-phase input terminal 12 with respect to the negative-phase input terminal 11, the differential amplifying stage 10 performs differential amplification, and level-shifts its output. After stage 20 has been level shifted, the output stage 30 P
MOS 31 is turned on. This level shift stage 20
Is applied to the gates of the transistors 31 and 32, the NMOS 32 is turned off, and the PM of the output stage 30
The output terminal 33 is supplied from the high potential power supply VDD via the OS 31.
Output current flows to

FIG. 9 is a diagram showing a bias voltage generating circuit 40 in the conventional example.

The bias circuit 40 includes a voltage Vb applied to the gate potential of the constant current source NMOS 17 of the differential amplifier stage 10.
1, a PMOS 41 and an NMOS 4
2 and 43.

The source of the PMOS 41 is a high potential power supply VD
D, and the gate and drain of the PMOS 41 are
It is connected to the gate and drain of the NMOS.
The drain and gate of the NMOS 43 are commonly NMO
It is connected to the source of S42 and to the bias terminal Vb1.

[0012]

The breakdown voltage of a MOS transistor is reduced by miniaturization of an element. When an operational amplifier is formed on a silicon-on-insulator structure, the operating voltage range of the element is further limited by an abnormal current increase phenomenon called a “parasitic bipolar effect”.

On the other hand, since the power supply voltage has a standard value, the power supply voltage applied to the circuit cannot be easily reduced.

Therefore, in the above-mentioned conventional example, when the operational amplifier is constituted by fine transistors, the voltage applied to the MOS transistor constituting the amplifier is reduced by the MOS transistor.
There is a problem that it becomes larger than the withstand voltage of the transistor. Particularly, in the output stage of the operational amplifier, since the output voltage changes between the high-potential power supply and the low-potential power supply,
There is a problem that the voltage applied to the transistor exceeds the withstand voltage of the transistor.

Further, as the power supply voltage increases, not only the output stage but also the level shift stage and the voltage applied to each transistor constituting the differential amplifier stage exceed the withstand voltage.

An object of the present invention is to provide an operational amplifier that can be used as an operational amplifier even when the voltage difference between a high potential power supply and a low potential power supply is higher than the withstand voltage of a single MOS transistor.

[0017]

According to the present invention, there is provided an operational amplifier including a differential amplifier stage, a level shift stage, and an output stage, wherein a drive transistor on a high potential power supply side and an output terminal in the output stage are provided. An operational amplifier having a first voltage clamp circuit provided and a second voltage clamp circuit provided between a drive transistor on the low potential power supply side and an output terminal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
1 is a circuit diagram showing an operational amplifier 101 according to a first embodiment of the present invention.

The operational amplifier 101 is composed of CMOS, performs differential amplification according to the input voltage difference between the positive-phase input terminal 51 and the negative-phase input terminal 52, and outputs a differential amplification stage 50 to the node N1. It comprises a level shift stage 60 that shifts the voltage on node N1 and outputs it to node N2, and an output stage 70 that is driven by node N1 or N2 and outputs an output voltage to output terminal 75.

The differential amplification stage 50 includes an input NMOS (N
Channel MOS transistors) 53 and 54, an NMOS 57 for a constant current source, and a PMOS (P-channel M
OS transistors) 55 and 56. The gate of the NMOS 53 is connected to the positive-phase input terminal 51, and the gate of the NMOS 54 is connected to the negative-phase input terminal 52. The sources of the NMOSs 53 and 54 are commonly connected to the drain of the NMOS 55,
The gate of 57 is connected to the bias voltage Vb1, and its source is connected to the low potential power supply VSS. NMO
The drains of S53 and S54 are connected to the drains of the PMOSs 56 and 57, and the sources of the PMOSs 56 and 57 are connected to the high potential power supply VDD. PMOS5
The gates 6 and 57 are connected to the drain of the PMOS 56, and the drain of the PMOS 57 is connected to the node N1.

Here, the bias voltage Vb1 is generated by the bias voltage generation circuit 40 shown in FIG.
The bias voltage generation circuit 40 may be configured on the same substrate as the operational amplifier 101.

The level shift stage 60 includes an NMOS 61 and an N
A level shift circuit using the MOS 62 is provided. The NMOS 61 has a drain connected to the high potential power supply VDD, a gate connected to the node N1, and a source connected to the node N2. N
The drain of the MOS 62 is connected to the node N2, the gate is connected to the bias voltage Vb1, and the source is connected to the low potential power supply VSS.

The output stage 70 includes a PMOS 7 serving as a driver.
1, an NMOS 74 and clamp circuits 72 and 73. The source of the PMOS 71 is connected to the high potential power supply VDD, its gate is connected to the node N1, and its drain is connected to the high potential side of the clamp circuit 72.

The low potential side of the clamp circuit 72 and the high potential side of the clamp circuit 73 are commonly connected to the output terminal 75. The source of the NMOS 74 is connected to the low-potential power supply VSS, the gate is connected to the node N2, and the drain is connected to the source of the NMOS 73.

That is, the operational amplifier 101 is provided between the driving transistor on the high potential power supply side and the output terminal in the output stage in the operational amplifier including the differential amplifier stage, the level shift stage, and the output stage. An operational amplifier having a first voltage clamp circuit and a second voltage clamp circuit provided between a drive transistor on the low potential power supply side and an output terminal.

(Second Embodiment) FIG. 2 is a circuit diagram showing an operational amplifier 102 according to a second embodiment of the present invention.

The operational amplifier 102 is different from the operational amplifier 101 in that the output stage clamp circuits 72 and 73
These are circuits using PMOS and NMOS, respectively.
That is, the operational amplifier 102 is the same as the operational amplifier 101 with respect to the differential amplifier stage 50 and the level shift stage 60, and instead of the output stage 70 in the operational amplifier 101,
The output stage 70A provided with the output stage 70A includes a PMOS 71 and an NMOS 74 serving as a driver, and a PMOS 72 and an NMOS 73 serving as a clamp circuit. The source of the PMOS 71 is connected to the high potential power supply VDD, the gate is connected to the node N1, and the drain is
It is connected to the source of the MOS 72. Also, PMOS
The gate of the gate 72 receives the bias voltage Vb3 and receives the NMO
The gate of S73 receives the bias voltage Vb2, and each drain is connected to the output terminal 75. NMOS
The source of 74 is connected to the low-potential power supply VSS, the gate is connected to the node N2, and the drain is connected to the source of the NMOS 73.

Next, the operational amplifier 10 of the above embodiment is described.
1 and 102 will be described.

FIG. 6 is a diagram showing potential waveforms at each node in the operational amplifier 101.

When a positive input voltage is applied to the negative-phase input terminal 52 to the positive-phase input terminal 51, the differential amplifier stage 50 amplifies the input voltage in the opposite phase to the input voltage, and
Output to This output signal is level-shifted in the level shift stage 60 and output to the node N2. Node N
2 turns off the NMOS 74 of the output stage 70A, and the node N1 causes the PMOS 74 of the output stage 70A to turn off.
1 is turned on.

As a result, when the PMOS 71 is OFF, the source of the PMOS 72 is held at “Vb3−Vtp”.
The source of 73 is held at “Vb2−Vtn”. Here, Vtp is a threshold value of the PMOS, and Vtn is NM.
OS threshold value.

Therefore, the PMOS 71 and the PMOS 7
2. The voltages applied to the NMOS 73 and the NMOS 74 are “VDD− (Vb3-Vtp)” and “(Vb2-
Vtp) -VSS "," VDD- (Vb3-Vt)
n) "and" (Vb2-Vtn) -VSS ".

That is, the operational amplifier circuit 102 uses the first P-channel MOS transistor 72 as the first voltage clamp circuit, and uses the first voltage clamp circuit as the second voltage clamp circuit.
A first N-channel MOS transistor 73 is used,
Using the gate voltages of the first P-channel MOS transistor 72 and the first N-channel MOS transistor 73,
An operational amplifier that controls a voltage clamp.

(Third Embodiment) FIG. 3 is a circuit diagram showing an operational amplifier 103 according to a third embodiment of the present invention.

The operational amplifier 103 is different from the operational amplifier 102 in that the gate terminal of the PMOS 72 in the output stage and the NMOS
73 and a gate terminal of the bias voltage terminal Vb3.
This is the circuit from which.

The bias voltage Vb2 is the high potential power supply VDD.
And a voltage between the voltage of the low potential power supply VSS and the threshold voltage Vtp of the PMOS 72 and the NMOS 73 exceeds Vtn.

The PMOS 72, NM of the output stage 70A
A bias voltage Vb2 exceeding a threshold value is applied to each gate of the OS 73. This allows PMO
When S71 is ON, PMOS72 is also ON at the same time.
It is.

For the same reason as described above, the NMOS
When 74 is ON, NMOS 73 is also turned ON at the same time. Therefore, the amplitude at the output terminal 75 has the same magnitude as the amplitude in the conventional example.

When the PMOS 71 is OFF, the source of the PMOS 72 is connected to the bias voltage Vb2 and the P
It is held at the sum (Vb2−Vtp) with the threshold voltage of the MOS. For the same reason, when the NMOS 74 is OFF, the source of the NMOS 73 is at the bias voltage V
b2 and the sum of NMOS threshold voltage Vtn (Vb2−Vt
n).

Therefore, the voltage applied to the driving PMOS 71 is “VDD− (Vb2−Vtp)”, and the voltage applied to the NMOS 74 is “(Vb2-Vtp)”.
tn) −VSS, and the voltage applied to the PMOS 72 becomes “(Vb2−Vtp) −VSS”.
The voltage applied to the NMOS 73 is “VDD− (Vb2
−Vtn) ”. If these are lower than the withstand voltage of the transistor, they can be used as operational amplifiers even if the voltage difference between the high-potential power supply and the low-potential power supply is higher than the withstand voltage.

In the operational amplifiers 101 and 102, the voltage amplitude at the output stage is reduced by the conventional operational amplifier 11
Since it can be kept equal to 1, the gain is equal to the gain in the conventional configuration.

If these are lower than the breakdown voltage of the transistor, even if the voltage difference between the high potential power supply and the low potential power supply is higher than the breakdown voltage,
It can be used as an operational amplifier. The operational amplifier 1
According to 03, it is possible to reduce the number of terminals for the bias voltage or the circuit area for generating the bias voltage.

(Fourth Embodiment) FIG. 4 is a circuit diagram showing an operational amplifier 104 according to a fourth embodiment of the present invention. The operational amplifier 104 includes a clamp circuit 63 between the high potential power supply side and the NMOS 61 in the level shift stage 60A.
Is provided.

The operational amplifier 104 is effective when the voltage applied to the operational amplifier becomes higher than that of the operational amplifiers 101, 102 and 103.

That is, the operational amplifiers 101, 102, 10
3, the voltage applied to the source-drain of the connected NMOS 61 in the level shift stage 60 is
The voltage applied to the source and the drain of the NMOS 62 is “VDD (V2) −VS (N2)”.
S ". Note that V (N2) is a potential at the node N2. Depending on the amplitude of the potential V (N2), the voltage exceeds the withstand voltage of the transistor. Therefore, in the operational amplifier 104, separately from the clamp circuit in the output stage, the high potential power supply side and the NMO
The clamp circuit 63 is disposed between the clamp circuit 63 and S61.

FIG. 7 is a diagram showing the potential of each node in the level shift stage 60 of the operational amplifier 103.

The clamp circuit 6 is provided in the level shift stage 60A.
By providing 3, the voltage swing of the NMOS 61 reaches “VDD−Vx” on the high potential side. Therefore,
The maximum potential difference “VDD−Vx−VSS” applied between the source and the drain of the NMOS 62 may be equal to or less than the withstand voltage of the NMOS.

Here, in the level shift stage 60A of the operational amplifier 104, a MOS transistor is used as an example of the clamp circuit.
In the level shift stage 60, the high potential power supply side and the NMOS
A PMOS 63 may be provided between the NMOS 61 and the NMOS 63, and the gate and the drain of the PMOS 63 may be made common and connected to the drain of the NMOS 61. As described above, the voltage is dropped by the added diode-connected PMOS 63, and the node N
2 can be suppressed below the withstand voltage of the NMOS transistor.

In place of the PMOS 63, an NMOS
It is also possible to use a transistor. That is, in this case, the same effect as described above can be obtained by connecting the gate and the source by diode, connecting to the high potential power supply, and connecting the drain to the source of the NMOS 61.

When a level shift stage of the opposite polarity (that is, a level shift stage for shifting the potential to the higher potential side) is formed, if a clamp circuit is provided on the lower potential power source VSS side, the same reason as in the above case can be obtained. Thus, the pressure resistance problem can be solved.

(Fifth Embodiment) FIG. 5 is a circuit diagram showing an operational amplifier 105 according to a fifth embodiment of the present invention.

The operational amplifier 105 differs from the operational amplifier 102 in that the PMOS 63
And a level shift stage 60A having
Is a circuit in which a differential amplification stage 50A having a current mirror circuit CM is provided and a level shift stage 80 is provided.

The current mirror circuit CM is a circuit in which clamping circuits 58 and 59 having the same impedance are provided on the high potential power supply side to perform voltage clamping in the differential amplification stage 50A. Also, the level shift stage 80 includes the differential amplifier stage 5
To shift the output amplitude from 0A to the high potential side,
The level shift stage has a polarity opposite to that of the level shift stage 60A.

In the differential amplification stage 50A, the high potential power supply V
The sources of the PMOSs 58 and 59 are connected to DD, and
Both gates are common (connected to each other) and PMOS
58 is connected to the drain of the PMOS 56 and the source of the PMOS 56,
The drain of the PMOS 59 is connected to the source of the PMOS 55. Further, a node N1 serving as an output of the differential amplification stage 50A is connected to the gate of the NMOS 61 of the level shift stage 60A and the gate of the PMOS 81 of the level shift stage 80, and the output node N of the added level shift stage 80 is connected.
3 is connected to the gate of the PMOS 71 of the output stage 70.

By providing the current mirror circuit CM constituted by the PMOSs 58 and 59 in the differential amplifier stage 50, the voltage applied to the sources of the PMOSs 55 and 56 drops from the high potential power supply VDD by the voltage Vy.

As a result, the voltage swing of the node N1 is limited, and the voltage swing of the NMOS 55 in the differential amplification stage 50A can be suppressed from exceeding the withstand voltage.

The magnitude of the voltage Vx depends on the NMOS 74
If the voltage Vy is too large, the differential amplifier stage 50 cannot operate. If the voltage Vy is too small, the purpose cannot be achieved. The size is set to about 1V.

[0058]

According to the first aspect of the present invention, there is an effect that the operational amplifier can be used even if the voltage difference between the high potential power supply and the low potential power supply is higher than the withstand voltage of the single MOS transistor.

According to the second aspect of the present invention, all of the CMs
It can be constituted by an OS, and has an effect that integration is facilitated.

According to the third aspect of the present invention, the number of control terminals of the clamp circuit can be reduced, and the area occupied by the circuit can be reduced.

According to the fourth aspect of the invention, it is possible to operate at a higher power supply voltage than the first aspect of the invention.

According to the fifth aspect of the invention, it is possible to operate at a higher power supply voltage than the third aspect of the invention.

[Brief description of the drawings]

FIG. 1 shows an operational amplifier 101 according to a first embodiment of the present invention.
FIG.

FIG. 2 is an operational amplifier 102 according to a second embodiment of the present invention;
FIG.

FIG. 3 is an operational amplifier 103 according to a third embodiment of the present invention;
FIG.

FIG. 4 is an operational amplifier 104 according to a fourth embodiment of the present invention;
FIG.

FIG. 5 shows an operational amplifier 105 according to a fifth embodiment of the present invention.
FIG.

FIG. 6 is a diagram showing a potential waveform at each node in the operational amplifier 101.

FIG. 7 is a diagram showing potentials at respective nodes in a level shift stage 60 of the operational amplifier 103.

FIG. 8 is a circuit diagram showing a conventional operational amplifier 111.

FIG. 9 shows a bias voltage generation circuit 40 according to the conventional example.
FIG.

[Explanation of symbols]

 101 to 105: operational amplifier, 50, 50A: differential amplification stage, 60, 60A, 80: level shift stage, 63, 72, 73: clamp circuit, 70, 70A, 70B, 70C: output stage, CM: current mirror Circuits, Vb1, Vb2, Vb3: bias voltage, VSS: low potential power supply, VDD: high potential power supply, 40: bias voltage generation circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shoichi Shimaya 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term within Nippon Telegraph and Telephone Corporation (reference) 5J091 AA01 AA18 AA47 CA00 CA91 CA92 FA01 HA10 HA17 HA19 KA02 KA06 KA09 KA12 KA18 KA21 MA22 TA06

Claims (5)

[Claims] 1. An operational amplifier comprising a differential amplifier stage, a level shift stage, and an output stage, wherein the operational amplifier is provided between a drive transistor on a high potential power supply side in the output stage and an output terminal of the output stage. An operational amplifier, comprising: a first voltage clamp circuit; and a second voltage clamp circuit provided between the drive transistor on the low potential power supply side and the output terminal. 2. The method according to claim 1, wherein the first voltage clamp circuit comprises a first P-channel MO.
The second voltage clamp circuit is a first N-channel MO.
An S transistor, using the gate voltages of the first P-channel MOS transistor and the first N-channel MOS transistor,
An operational amplifier for controlling a voltage clamp. 3. The operational amplifier according to claim 2, wherein a gate terminal of said first P-channel MOS transistor and a gate terminal of said first N-channel MOS transistor are connected to each other. 4. The level shift stage according to claim 1, wherein a clamp means is provided between the high-potential power supply and the driving N-channel MOS transistor in the level shift stage. Operational amplifier. 5. The operational amplifier according to claim 1, wherein a current mirror circuit is added to a high potential power supply side in the differential amplification stage.