JP2001051868A - Data processing device with built-in debugging mechanism, host machine, and recording medium - Google Patents

Abstract

(57) [Problem] To provide a data processing device with a built-in debugging mechanism that enables software debugging and evaluation even when a part of a communication interface has a defect. SOLUTION: A data processing device with a built-in debugging mechanism is:
A plurality of communication interface circuits connected to the host machine, a plurality of communication control module programs corresponding to the plurality of communication interface circuits, a memory storing an execution program for performing debugging, and a processor. You. The processing of the execution program corresponds to the first step of receiving a digital value for selecting any one of the plurality of communication interface circuits from the host machine and taking in the processor, and the communication interface circuit selected by the digital value. And a second step in which a command for debugging and a response to the command are performed via the communication control module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data processing apparatus, a host machine, and a recording medium including a mechanism for debugging a program to be debugged.

[0002]

2. Description of the Related Art FIG. 12 shows a configuration diagram of a conventional software debug device 1. Software debug device 1 of LSI incorporating processor such as CPU or DSP
12, an evaluation board 20 on which a debug target LSI 10 is mounted and a host machine 30 such as a PC or WS, as shown in FIG.
Are connected via a communication cable 40. Debugging of the software on the evaluation board 20 by the software debug device 1 is performed as follows.

[0005] First, a debug command is transmitted from the host machine 30 to the debug target LSI 10 on the evaluation board 20 at the discretion of the designer who performs debugging. The debug target LSI 10 that has received the command
Are interpreted and executed by a debugger processing program built in the debug target LSI 10 and a processor that executes the program. The debug target LSI 10 sends the execution result of the command back to the host machine 30 so that the processing result for the command is displayed on the display of the host machine 30.
The processing for one debugging command ends.
The software is debugged by repeating these operations by the host machine 30.

[0004]

In such a current software debug device 1, an H / W for communication is used.
If there is a problem in the communication interface, for example, communication between the host machine 30 and the evaluation board becomes difficult, so that the software debug device 1 cannot be operated. As described above, there is a problem that evaluation / debugging of an LSI after chip manufacture becomes impossible due to a defect of a communication interface for performing communication.

Further, due to the limitations of the board (system) on which the LSI 10 to be debugged is mounted, the
In some cases, it may not be possible to use all of the communication means mounted on the I10. For example, LSI to be debugged
In some cases, a board (system) on which the debug target LSI 10 is mounted does not support the parallel interface even though the parallel interface is built in the device 10. At this time, if only the parallel interface is supported as the communication interface between the host machine 30 and the evaluation board 20 for debugging, there is a problem that the debugging target LSI 10 cannot be debugged.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The present invention has been made in the case where a part of a communication interface for performing communication has a defect, or the LSI 1 to be debugged has a problem.
Even if there is a restriction on the board (system) side on which 0 is mounted and all the communication interfaces prepared in the LSI 10 to be debugged cannot be prepared on the board (system) side, software debugging and evaluation can be performed. It is an object of the present invention to obtain a data processing device equipped with a debugging mechanism. It is another object of the present invention to obtain a host machine 30 that realizes the software debug device 1 integrally with a data processing device equipped with a debug mechanism that enables software debugging and evaluation.

[0007]

In the data processing device with a built-in debugging mechanism according to the first invention, a plurality of communication interface circuits respectively connected to a host machine and a plurality of communication interface circuits are respectively provided. Correspondingly includes a plurality of communication control module programs for performing communication control, a memory storing an execution program for performing debugging, and a processor for reading and executing the execution program stored in the memory. The processing instructed by the execution program includes: (1) when receiving a digital value for selecting any one of the plurality of communication interface circuits from the host machine, this digital value is A first step taken by the processor, and (2) a first step.
And a second step of transmitting and receiving a command for debugging and a response to the command via a communication control module corresponding to the communication interface circuit selected by the digital value.

In the data processing device with a built-in debugging mechanism according to the second invention, the processing instructed by the execution program is further executed by the host machine prior to the first step. And a third step in which the processor sends test response data to the host machine via the same communication interface circuit as the communication interface circuit that has received the test request when the test request is received via It is like that.

The data processing device with a built-in debugging mechanism according to the third invention further includes a communication interface circuit different from the plurality of communication interface circuits, and stores a digital value for selecting one of the communication interface circuits. The receiving is performed by the another communication interface circuit.

In the data processing device with a built-in debugging mechanism according to the fourth invention, receiving the digital value for selecting one of the communication interface circuits is as follows.
This is performed by any one of the communication interface circuits operable among the plurality of communication interface circuits.

In a data processing device with a built-in debugging mechanism according to a fifth invention, a plurality of communication interface circuits each connected to a host machine, and communication control corresponding to each of the plurality of communication interface circuits. A plurality of communication control modules, which are programs for executing, a memory storing an execution program for performing debugging, and a processor configured to read and execute the execution program stored in the memory, The processing instructed by the execution program includes a step in which, when a test request is received from a host machine, the processor sends test response data to the host machine via each of the plurality of communication interface circuits. It was done.

In a host machine according to a sixth aspect of the present invention, there is provided a control program for performing a debugging control of a data processing device having a built-in debugging mechanism, and a processing unit for performing the debugging control of the data processing device; And a plurality of communication interfaces respectively connecting between the first and second communication interfaces, and the processing instructed by the control program of the processing unit includes: (1) a first command for transmitting a command requesting a test to the data processing device; Steps and
(2) a second step of receiving a response from the data processing device to the command requesting the test in the first step, and (3) determining the response received in the second step. A communication interface establishing procedure including a third step of selecting one of the communication interfaces and transmitting a digital value corresponding to the selected communication interface, and after establishing the communication interface, A command and a response to the command are transmitted and received using an interface.

[0013] The host machine according to a seventh aspect of the present invention further comprises a communication interface different from the plurality of communication interfaces. This is performed by a communication interface.

In the host machine according to the eighth invention, the transmission of the digital value corresponding to the selected communication interface in the third step is performed by any one of the plurality of communication interfaces. It is intended to be performed.

In a host machine according to a ninth aspect of the present invention, a control program for performing a debug control of a data processing device having a built-in debug mechanism is built in, and a processing unit for performing the debug control of the data processing device; And a plurality of communication interfaces respectively connecting between the first and second processing units. The processing instructed by the control program of the processing unit includes: (1) a first command for transmitting a command requesting a test to the data processing device; Steps and
(2) receiving a response from the data processing device to the command requesting the test in the first step from each of the plurality of communication interfaces. After the communication interface is established, a command and a response to the command are transmitted and received using one of the communication interfaces.

In a recording medium according to a tenth aspect of the present invention, a control program stored in a memory of a host machine for performing a debugging control of a data processing device having a built-in debugging mechanism is stored. The instructed processing includes: (1) a first step of transmitting a command requesting a test to the data processing apparatus; and (2) the data processing apparatus responding to a command requesting a test in the first step. And (3) selecting one of the communication interfaces by judging the response received in the second step, and selecting a digital interface corresponding to the selected communication interface. A communication interface establishment procedure including a third step of transmitting a value; After the connection is established, the host computer storing the control program for controlling the host machine to transmit and receive a command and a response to the command using one of the communication interfaces may be readable. It was made.

In a recording medium according to an eleventh aspect of the present invention, a control program stored in a memory of a host machine for performing a debugging control of a data processing device having a built-in debugging mechanism is stored. The instructed processing includes: (1) a first step of transmitting a command requesting a test to the data processing apparatus; and (2) the data processing apparatus responding to a command requesting a test in the first step. And a second step of receiving a response from each of the plurality of communication interfaces from the communication interface. After the communication interface is established, a command is issued using any one of the communication interfaces. And send and receive a response to that command. Tomashin is obtained as is readable by the host machine which stores the control program for controlling.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a configuration diagram of a software debug device 1 for debugging a program such as software or firmware in an evaluation board 20 on which a debug target LSI 10 is mounted according to the first embodiment. The software debug device 1 includes an LSI 10 to be debugged, an evaluation board 20 on which the LSI 10 to be debugged is mounted, and a control unit 31 for performing debug control for debugging and evaluating a program and the like mounted on the LSI 10 to be debugged. It comprises a host machine 30 and a communication cable 40 composed of a plurality of cables connecting between the evaluation boat 20 and the host machine 30. Although not shown in FIG. 1, the control unit 31 of the host machine 30 stores a memory storing a control program for performing debugging control on the evaluation board 20 side and a control program stored in the memory. A CPU to execute is included. Also, host machine 3
0 includes a device for reading the contents of a recording medium storing a control program for performing debug control and writing the control program stored in the recording medium to a memory in the control unit 31.

FIG. 2 shows the internal configuration of the hardware of the LSI 10 to be debugged and the configuration of the evaluation board 20. The debug target LSI 10 includes a processor 101 such as a CPU or a DSP, an instruction ROM 102 storing instructions to be executed by the processor 101, and a data RAM 1 storing data to be executed by the processor 101.
03, and communication interfaces 60, 61, and 62 for communicating with the outside of the debug target LSI. The communication interface 60 includes a communication port 110 in the debug target LSI 10 and an evaluation board 2.
0 and a cable 400 connected to the host machine 30. The communication interface 61 includes a first communication interface circuit 111 in the debug target LSI 10 and a connector 2 on the evaluation board 20.
11 and a cable 401 connected to the host machine 30
And are included. The communication interface 62 is connected to the second communication interface circuit 11 in the debug target LSI 10.
2, a connector 212 on the evaluation board 20, and a cable 402 connected to the host machine 30.

Next, the connection configuration inside the debug target LSI 10 will be described. The processor 101 is connected to the instruction ROM 102 via the AD1 bus. The processor 101 is connected to the data RAM 103 via the AD2 bus.
A receiving-side output terminal of the communication port 110 in the communication interface 60, a transmitting-side input terminal and a receiving-side output terminal of the first communication interface circuit 111 in the communication interface 61, and a second communication interface circuit in the communication interface 62. 112 are connected to a transmission-side input terminal and a reception-side output terminal.

Next, a connection form of the evaluation board 20 will be described. LS to be debugged in communication interface 60
The receiving input terminal of the communication port 110 of I10 is connected to the signal line C
It is connected to P1 and a cable 400 which is one of the communication cables 40 via a connector 210. The transmission-side output terminal and the reception-side input terminal of the first communication interface circuit 111 in the communication interface 61 are connected to the signal line C1.
And a cable 401 which is one of the communication cables 40 via a connector 211. Further, the second communication interface circuit 1 in the communication interface 62
12 are connected to a signal line C2.
Is connected to a cable 402 which is one of the communication cables 40 via a connector 212. Although not shown, the host machine 30 and the evaluation board 20 are connected by a communication cable 40 including cables 400, 401, and 402.

Next, the operation will be described. Processor 1
Reference numeral 01 executes an instruction according to a program stored in an instruction ROM 102 or an instruction RAM (not shown) while referring to data stored in a data RAM 103. Further, according to the program stored in the instruction ROM 102, the communication interface 6
Data transmission / reception with the host machine 30 via 0, 61, and 62 is performed. The instruction ROM 102 stores a debugger processing program 500 for realizing a debugging function. The debug target program to be debugged is stored in the instruction ROM 102 or an instruction RAM (not shown) existing inside or outside the debug target LSI 10.

FIG. 3 shows the internal configuration of the debugger processing program 500 stored in the instruction ROM 102. The debugger processing program 500 is a debugger main routine 5
01, a command analysis routine 502 called from the debugger main routine 501, a command execution routine 503 also called from the debugger main routine 501, a command analysis routine 502 or the command execution routine 503 or the debugger main routine 5
The communication interface control routine 504 is called from step S01.

The communication interface control routine 50
Reference numeral 4 includes communication control modules CP1M, C1M, and C2M corresponding to the communication port 110, the first communication interface circuit 111, and the second communication interface circuit 112 in the debug target LSI 10, respectively. Each of the communication control modules CP1M, C1M, C2M is also called a driver, and exchanges transmission / reception data by directly controlling the H / W of the corresponding communication port 110, the first communication interface circuit 111, and the second communication interface circuit 112. Is a program that performs

Here, the communication interface 60 including the communication port 110 transmits a signal for designating a communication interface used when transmitting / receiving a debug command and data of a response to the debug command from the host machine 30. Is done. The communication interface used when transmitting and receiving the debug command and the data of the response to the debug command includes a communication interface 61 including the first communication interface circuit 111 and a communication interface including the second communication interface circuit 112. One of the interfaces 62 is used.

In order to start the host machine 30 and start debugging the debug target LSI 10 mounted on the evaluation boat 20, the host machine 30 and the evaluation board 20
Communication interface 6 as communication interface between
1 and the communication interface 62 must be selected to determine a communication path for communication. That is, it is necessary to establish a communication interface for transmitting and receiving a debug command for debugging and its response.

FIG. 4 is a flowchart showing a procedure for establishing a communication interface when viewed from the host machine 30 side. When the host machine 30 determines that it is necessary to establish a communication interface to perform debugging, first, the process of step S101 is started. In step S101, "0" is set as the initial value of the communication interface number. In step S102, a test command is transmitted using the communication interface corresponding to the communication interface number specified in step S101. Here, when the value of the communication interface number is “0”, communication is performed using the communication interface 61 including the first communication interface circuit 111, and when the value of the communication interface number is “1”, the communication is performed using the second. It is assumed that the communication is performed using the communication interface 62 including the communication interface circuit 112.

In step S103, the data RA indicates whether the expected response to the test command transmitted in step S102 has been received by the host machine 30.
Recorded in M103. In step S104, it is determined whether the designated communication interface number is the last one of the communication interface numbers. If the communication interface number is not the last number, the process of step S105 is performed. If the communication interface number is the last number, the process of step S106 is performed. In this example, the communication interface number is “0”,
Since there is only “1”, the last communication interface number indicates a value of “1”. In step S105, the value of the communication interface number is incremented, and the process returns to step S102.

In step S106, an optimum communication interface number for transmitting the debug command is selected from among the communication interface numbers that have been able to receive the expected response stored in the memory in step S103. As an optimal communication interface for transmitting the debug command, it is desirable to use a communication interface that minimizes communication overhead among communication interfaces that can transmit and receive.
In step S107, the data of the selected communication interface number is transferred to the communication port 11 of the communication interface 60.
0, and the process of establishing the communication interface ends.

Next, a procedure for establishing a communication interface as viewed from the evaluation board 20 will be described with reference to the flowchart of FIG. When the power is turned on on the evaluation board 20 side, the process of step S121 is started. Step S121 is a state of waiting for reception of the data of the command sent from the host machine 30, and the process of step S122 is performed by receiving the data from the host machine 30 side. In step S122, it is determined whether or not the data received from the host machine 30 is input from the communication port 110 of the communication interface 60.
If so, step S125 is performed. if,
Otherwise, that is, if it is received from the communication interface 61 or 62, step S123 is executed.

In step S123, the command received from the host machine 30 is a test command, and the processing specified by the test command is performed. Step S
At 124, a response to the test command is transmitted using the same communication interface as the communication interface that received the test command, and the process returns to step S121.

In step S125, the LSI 1 to be debugged
0 is the communication interface 6 including the communication port 110
0, the communication interface number data transmitted from the host machine 30 through the data RAM 103.
And the process of establishing the communication interface is completed. Here, when the value of the communication interface number is “0”, the communication is performed using the communication interface 61.
When the value of the communication interface number is “1”, the communication is performed using the communication interface 62.

The test command refers to the debug target L mounted on the evaluation board 20 from the host machine 30 side.
This is a command for determining whether or not the debugging of the SI 10 can be executed. The command is for testing whether communication between the LSI 10 to be debugged including the evaluation board 20 and the host machine 30 can be normally performed, LSI1
This is a command for performing a read / write test on the data RAM 103 in 0. The test results are output from the evaluation board 20 to the host machine 30 as a response to the test command. That is, the host machine 30
Is the debug target LSI 10 mounted on the evaluation boat 20
Executing a test command with respect to the data RAM in the test and debug target LSI 10 of each of the communication interface 61 and the communication interface 62
A test of 103 is performed.

As a result, the host machine 30 determines whether each of the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112 is available, Data RAM 10
3 can read and write. If the host machine 30 determines that the debug target LSI 10 can be debugged, the subsequent communication is controlled to communicate via one of the communication interfaces based on the test result.

That is, when performing communication using the communication interface 61, “0” is transmitted to the communication port 110 of the communication interface 60. When communication is performed using the communication interface 62, “1” is transmitted to the communication port 110 of the communication interface 60.

Next, the operation after the establishment of the communication interface will be described. Here, the description will be made on the assumption that the communication interface 61 including the first communication interface circuit 111 is selected as the communication interface for transmitting and receiving the debug command and its response in establishing the communication interface. FIG. 6 shows a processing flow of the debug command processing of the debugger processing program 500 for realizing the debug function.

First, as a pre-process for receiving a debug command, since the value of the communication interface number stored in the data RAM 103 is "0", the communication control module C1M in the debugger processing program 500 is started, and the first A command reception from the communication interface circuit 111 is waited. When in the command reception waiting state, the debug command is transmitted from the host machine 30 to the first communication interface circuit 11 of the communication interface 61.
Sent toward 1. Upon receiving the debug command, an interrupt occurs to the processor 101, the debugger processing program 500 is started, and the debug command processing is started.

In step S501, the transmitted debug command is transmitted to the processor 101 via the receiving side of the first communication interface circuit 111 by the communication module C1M of the communication interface control routine 504.
Is read in. That is, a debug command is input. The debug command read in step S502 is analyzed by the command analysis routine 502, and the command execution routine 503 executes the debug command based on the analysis result. In step S503, since the value of the communication interface number stored in the data RAM 103 is "0", the host machine 30 via the transmission side of the first communication interface circuit 111 receives the data resulting from executing the debug command as a response. Sent to. The transmission to the host machine 30 is transmitted via the first communication interface circuit 111 by activating the communication interface control routine 504 specifying the communication control module C1M.

As described above, the two communication interfaces 61 and 62 including the first communication interface circuit 111 or the second communication interface circuit 112 and the communication interfaces corresponding to the first communication interface circuit 111 and the second communication interface circuit 112, respectively. Control module C1
M and C2M, and a communication port 110. Also,
A step of testing each of the two communication interfaces 61 and 62 according to a test request by a test command from the host machine 30 as communication interface selecting means for selecting one of the two communication interfaces 61 and 62; The host machine 3
0, and a communication interface establishment procedure comprising the step of notifying the processor 101 of the communication interface used for debugging by the host machine 30 which has received the response, using the communication port 110. Two communication interfaces 6 including the first communication interface circuit 111 or the second communication interface circuit 112 depending on the establishment procedure.
Even if one of the communication interfaces 1 and 62 cannot be used, the communication interface that can be used by the processor 101 can be easily known and selected, so that a highly reliable debugging mechanism is easily incorporated. There is an effect that an evaluation board 20 on which the LSI to be debugged is mounted can be obtained.

Also, due to the limitations of the evaluation board 20, the first
Even when only one communication interface circuit of the communication interface circuit 111 or the second communication interface circuit 112 can be mounted, the host machine 30
Since the communication interface that can be used for debugging can be known by the communication interface establishment procedure, there is an effect that debugging and evaluation can be performed using the communication interface.

Further, as a result of the test, when there is a problem in both the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112 and debugging cannot be performed, the host machine Communication port 110 from 30
Sends data indicating that communication is not possible to the evaluation board 2
This can be notified to the 0 side, which is effective in improving reliability.

In the procedure for establishing the communication interface, the host machine 30 sequentially tests the communication interface number from "0" to the last number.
Instead of testing all, the test may be terminated when an expected response can be received, and the communication interface number data may be transmitted to the cable connected to the communication port 110.

The first communication interface circuit 111
The second communication interface circuit 112 includes a bit I / O, a parallel I / O, an asynchronous communication control circuit for performing general parallel / serial or serial / parallel conversion, a synchronous communication control circuit, and a JTA.
Any of G serial interface circuits may be used.

Further, here, two communication interfaces for transmitting and receiving a debug command and its response, that is, the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112 are shown. However, the number of communication interfaces may be n. “N” is a natural number of 2 or more. At this time, n communication interface circuits, n cables, and n communication control modules corresponding to the communication interface module 504 are required for each of the n communication interfaces. At this time, the communication port 110 needs a port having the number of bits that can specify the value of “n”.

Even when all of the n communication interface circuits cannot be mounted on the evaluation board 20 due to the restriction of the evaluation board 20, the host machine 30 can know the communication interface that can be used for debugging by the communication interface establishing procedure. It is possible to notify the processor 101 of the evaluation board 20 of the communication interface used for transmitting and receiving a debug command and its response among those available communication interfaces. There is an effect that evaluation can be performed.

Embodiment 2 The second embodiment has a configuration in which the communication interface 60 is removed from the internal configuration of the H / W of the debug target LSI 10 and the configuration of the evaluation board 20 of the first embodiment shown in FIG. That is, the communication port 110 in the debug target LSI 10 provided in the communication interface 60, the connector 210 on the evaluation board, the signal line CP1 connected to the connector 210, and the cable 400 in the communication cable 40 are deleted. It has a configuration. The LSI 10 to be debugged in the second embodiment
7 shows the internal configuration of the H / W and the configuration of the evaluation board 20.

A debugging system configuration diagram for debugging a program such as software or firmware in the evaluation board 20 on which the debugging target LSI 10 is mounted is the same as FIG. 1 shown in the first embodiment.
The description of that part is omitted. Further, the description of the internal configuration of the H / W of the debug target LSI 10 and the configuration of the evaluation board 20 shown in FIG. 7 will be omitted because the configuration is partially deleted from the configuration of FIG. 2 as described above.

Next, the operation of the second embodiment will be described. The processor 101 executes instructions while referring to data stored in the data RAM 103 according to an instruction ROM 102 or a program (not shown) stored in the instruction RAM. The instruction R
According to the program stored in the OM 102, data is transmitted to and received from the host machine 30 via the communication interface 61 or 62. The instruction ROM 102 stores a debugger processing program 500 for realizing a debugging function.
The debug target program to be debugged is the instruction RO
M102 or an instruction RAM (not shown) existing inside or outside the debug target LSI 10
Is stored in

The internal configuration of the debugger processing program 500 stored in the instruction ROM 102 is different from the internal configuration of the debugger processing program 500 in the first embodiment shown in FIG. That is not to do.
Other internal configurations are the same as in the first embodiment. Therefore, the debugger processing program 500 includes a debugger main routine 501, a command analysis routine 502 called from the debugger main routine 501, a command execution routine 503 also called from the debugger main routine 501, and the command analysis routine 502 or the command execution routine 503. Alternatively, it comprises a communication interface control routine 504 called from the debugger main routine 501.

The communication interface control routine 50
Reference numeral 4 denotes communication control modules C1M and C2M corresponding to the first communication interface circuit 111 and the second communication interface circuit 112 in the debug target LSI 10, respectively.
It is included. Each of the communication control modules C1M and C2M is also called a driver, and has a corresponding first communication interface circuit 111 and second communication interface circuit 1
12 is a program for directly transmitting and receiving data by directly controlling the H / W 12.

In order to start the host machine 30 and start debugging the debug target LSI 10 mounted on the evaluation boat 20, the host machine 30 and the evaluation board 20
Communication interface 6 as communication interface between
1 and the communication interface 62 must be selected to determine a communication path for communication. That is, it is necessary to establish a communication interface for transmitting and receiving a debug command for debugging and its response.

FIG. 8 is a flowchart showing a procedure for establishing a communication interface as viewed from the host machine 30 according to the second embodiment. Host machine 3
If 0 determines that the communication interface needs to be established for debugging, the process of step S201 is first started. In step S201, “0” is set as an initial value of the communication interface number. In step S202, a test command is transmitted using the communication interface corresponding to the specified communication interface number. Here, when the value of the communication interface number is “0”, communication is performed using the communication interface 61 including the communication interface circuit 111, and when the value of the communication interface number is “1”, the communication interface circuit is used. Communication interface 6 including 112
It is assumed that the communication uses the communication No. 2.

In step S203, whether or not the expected response to the test command transmitted in step S202 has been received by the host machine 30 is recorded in the memory. In step S204, it is determined whether the designated communication interface number is the last one of the communication interface numbers. If the communication interface number is not the last number, the process of step S205 is performed. If the communication interface number is the last number, the process of step S206 is performed. In this example, since there are only “0” and “1” as communication interface numbers, the last communication interface number indicates a value of “1”. In step S205,
The value of the communication interface number is incremented, and the process returns to step S202.

In step S206, an optimum communication interface number for transmitting the debug command is selected from among the communication interface numbers in which the expected response stored in the memory in step S203 has been received. As an optimal communication interface for transmitting the debug command, it is desirable to use a communication interface that minimizes communication overhead among communication interfaces that can transmit and receive.
In step S207, the data of the selected communication interface number is included in a predetermined position of the transmission data of the test command and transmitted using the communication interface determined in advance by the software debug device 1. For example,
If the communication interface 61 is the communication interface determined in advance by the software debug device 1, the test command is transmitted to the first communication interface circuit 111 of the communication interface 61.

In the procedure for establishing the communication interface, the host machine 30 sets in advance the data of the communication interface number corresponding to the communication interface used for transmitting and receiving the debug command and its response from the test result of the communication interface. The communication interface 61 is trying to send the data to the evaluation board 20, but if there is a problem with the communication interface 61 and communication is not possible, the data of the communication interface number is sent out by the communication interface 62 which is the next communication interface.

Next, a procedure for establishing a communication interface as viewed from the evaluation board 20 according to the second embodiment will be described with reference to the flowchart of FIG. When the power is supplied to the evaluation board 20, the process of step S221 is started. Step S221 is a state of waiting for reception of a test command sent from the host machine 30,
Upon receiving the test command from the host machine 30, the process of step S222 is performed. In step S222, it is determined whether or not the communication interface number data is included in the received data of the test command from the host machine 30. If the communication interface number data is included, step S225 is executed. . If not included, step S223 is executed.

In step S223, the process specified by the test command received from the host machine 30 is performed. In step S224, a response to the test command is transmitted using the same communication interface circuit as the communication interface circuit that received the test command, and the process returns to step S221.

In step S225, the communication interface number data sent from the host machine 30 is fetched, the number data is stored in the data RAM 103, and the process of establishing the communication interface is completed. here,
When the value of the communication interface number is “0”, communication is performed using the communication interface 61 including the communication interface circuit 111. When the value of the communication interface number is “1”, the communication interface circuit 112 is included. This is communication using the communication interface 62.

The test command refers to the debug target L mounted on the evaluation board 20 from the host machine 30 side.
This is a command for determining whether or not the debugging of the SI 10 can be executed. The command is for testing whether communication between the LSI 10 to be debugged including the evaluation board 20 and the host machine 30 can be normally performed, LSI1
This is a command for performing a read / write test on the data RAM 103 in 0. The test results are output from the evaluation board 20 to the host machine 30 as a response to the test command. In other words, the host machine 30 sequentially executes test commands on the debug target LSI 10 mounted on the evaluation boat 20 via the respective communication interface circuits 111 and 112, thereby testing and debugging the communication interface 61 and the communication interface 62, respectively. A test of the data RAM 103 in the target LSI 10 is performed. In the case of a test command including communication interface number data for selecting a communication interface, it is not necessary to perform a test even when the command is received.

As a result, the host machine 30 can know whether or not each of the communication interface 61 and the communication interface 62 can be used and whether or not the data can be read from and written to the data RAM 103 in the LSI 10 to be debugged. If the host machine 30 determines that debugging within the debug target LSI 10 is possible, the subsequent communication, that is, transmission and reception of the debug command and its response, is performed via one of the communication interfaces based on the test result.

The communication interface used when transmitting data of the communication interface number for selecting one of the communication interfaces based on the test result is determined in advance by the software debug device 1. Here, the communication interface 61 is set as the communication interface, and if the data of the communication interface number is “0”, the communication interface 6 is set.
"0" at a predetermined position meaning communication interface number data toward the first first communication interface circuit 111.
Is sent out. If the data of the communication interface number is “1”, a test command including “1” at a predetermined position meaning the communication interface number data is transmitted to the first communication interface circuit 111 of the communication interface 61. You.

In the procedure for establishing the communication interface, the host machine 30 sets in advance the data of the communication interface number corresponding to the communication interface used for transmitting and receiving the debug command and the response from the test result of the communication interface. The communication interface 61 is trying to send the data to the evaluation board 20, but if there is a problem with the communication interface 61 and communication is not possible, the data of the communication interface number is sent out by the communication interface 62 which is the next communication interface.

Next, the operation after the establishment of the communication interface will be described. Since the operation after the establishment of the communication interface is the same as that of the first embodiment, the description of the operation of that portion is omitted here.

As described above, the two communication interfaces 61 and 62 including the first communication interface circuit 111 or the second communication interface circuit 112 and the communication interfaces corresponding to the first communication interface circuit 111 and the second communication interface circuit 112, respectively. Control module C1
M and C2M. A step of performing a test on each of the two communication interfaces 61 and 62 in accordance with a test request from a host machine 30 as a communication interface selecting means for selecting one of the two communication interfaces 61 and 62;
A communication interface comprising: a step of responding the test result to the host machine 30; and a step of informing the processor 101 of the communication interface used for debugging by the host machine 30 that has received the response, using any one of the communication interfaces capable of communicating. Since the communication interface establishing means has one of the two communication interfaces 61 and 62 including the first communication interface circuit 111 or the second communication interface circuit 112, the communication interface establishing means cannot use the communication interface. Since the communication interface which can be used by the processor 101 can be easily known and selected, there is an effect that a highly reliable debug target LSI with a built-in debugging mechanism can be easily obtained.

Also, due to the limitations of the evaluation board 20, the first
Even when only one communication interface circuit of the communication interface circuit 111 or the second communication interface circuit 112 can be mounted, the host machine 30
Since the communication interface that can be used for debugging can be known by the communication interface establishment procedure, there is an effect that debugging and evaluation can be performed using the communication interface.

In the procedure for establishing the communication interface, the host machine 30 tests the communication interface numbers sequentially from “0” to the last number.
Instead of testing all of the communication interfaces,
The test may be terminated when the expected response can be received, and the data of the communication interface number may be transmitted to the communication interface 61 set in advance.

Further, the host machine 30 needs to select and designate a communication interface used for transmitting and receiving the debug command and its response based on the test result.
As the communication interface for transmitting the data of the communication interface number, the communication port 60 shown in the first embodiment is used.
Is not included in the communication interface, but one of the two communication interfaces 61 and 62 which may transmit and receive the debug command and its response is determined in advance by the software debug device 1, and the predetermined Since the data of the communication interface number is transmitted by using the specified communication interface, the communication port 110, the connector 210 on the evaluation board, and the cable 400 in the first embodiment can be reduced. There is an effect that the cost of the software debug device 1 can be reduced.

The first communication interface circuit 111
And the second communication interface circuit 112 are respectively a bit I / O, a parallel I / O, an asynchronous communication control circuit or a synchronous communication control circuit for performing general parallel / serial or serial / parallel conversion, and JTAG.
Any of the serial interface circuits of the specification may be used.

Also, here, two communication interfaces for transmitting and receiving a debug command and its response, that is, the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112, are shown. But
The number of communication interfaces may be n. “N” is a natural number of 2 or more. At this time, n communication interface circuits and n communication interfaces corresponding to n communication interfaces in the communication interface module 504 respectively.
Communication control modules are required.

Even if all of the n communication interface circuits cannot be mounted on the evaluation board 20 due to the restriction of the evaluation board 20, the host machine 30 can know the communication interface that can be used for debugging by the communication interface establishing procedure. It is possible to notify the processor 101 of the evaluation board 20 of the communication interface used for transmitting and receiving a debug command and its response among those available communication interfaces. There is an effect that evaluation can be performed.

Embodiment 3 In the third embodiment, the control method is changed with the same H / W configuration as in the second embodiment. Therefore, the debug system configuration diagram of the software debug device 1 when debugging programs such as software and firmware in the evaluation board 20 on which the debug target LSI 10 is mounted is the same as FIG. 1 shown in the first and second embodiments. Since they are the same, the description of those parts is omitted. Also, the H / W of the debug target LSI 10
The internal configuration and the configuration of the evaluation board are also the same as those in FIG.

Next, the operation of the third embodiment will be described. The processor 101 executes instructions while referring to data stored in the data RAM 103 according to an instruction ROM 102 or a program (not shown) stored in the instruction RAM. The instruction R
According to the program stored in the OM 102, the first
Transmission and reception are performed with the host machine 30 via the communication interface circuit 111 and the second communication interface circuit 112. The instruction ROM 102 stores a debugger processing program 500 for realizing a debugging function. The debugged program to be debugged is
The instruction is stored in the instruction ROM 102 or an instruction RAM (not shown) existing inside or outside the debug target LSI 10.

The internal configuration of the debugger processing program 500 stored in the instruction ROM 102 is the same as the internal configuration of the debugger processing program 500 in the second embodiment, and the description of the internal configuration of the debugger processing program 500 is omitted here. I do.

In order to start the host machine 30 and start debugging the debug target LSI 10 mounted on the evaluation board 20, the host machine 30 and the evaluation board 20
Communication interface 6 as communication interface between
1 and the communication interface 62 must be selected to determine a communication path for communication. That is, it is necessary to establish a communication interface for transmitting and receiving a debug command for debugging and its response.

FIG. 10 is a flowchart showing a procedure for establishing a communication interface as viewed from the host machine 30 according to the third embodiment. When the host machine 30 determines that it is necessary to establish a communication interface to perform debugging, first, the processing of step S301 is started. In step S301, any one of a plurality of communication interfaces is selected. In step S302, a test command is transmitted using the selected communication interface. Here, as the communication interface when considering the correspondence with FIG. 7, the communication interface 61 including the cable 401 and the first communication interface circuit 111 is used.
, Cable 402 and second communication interface circuit 11
2 is included. The evaluation board 20 receiving the test command in step S302 transmits a response to the test command using each of the communication interface 61 and the communication interface 62. This is the process of step S324 of the procedure for establishing the communication interface when viewed from the evaluation board 20 described later.

In step S303, it is determined whether the expected response to the test command transmitted in step S302 has been received from the communication interface selected in step S302. If the expected response can be received from the selected communication interface, the process skips to step S308.
Otherwise, step S304 is performed. In step S304, it is determined whether an expected response to the test command transmitted in step S302 has been received by a communication interface other than the communication interface selected in step S302. If the expected response can be received by a communication interface other than the selected communication interface, step S305 is executed. Otherwise, step S306 is executed.

In step S305, a communication interface having an expected response is selected.
Return to 02. In step S306, it is determined whether or not all the communication interfaces 61 and 62 have been selected. If all of the communication interfaces 61 and 62 have been selected so far, there is no point in performing further tests. Abnormal termination. If not, step S
307 is performed. If the communication is abnormally terminated, it indicates that the communication interface for debugging could not be established, and the display of the host machine 30 indicates that the communication interface is abnormal and cannot be debugged, and the process ends. In step S307, a communication interface that has never been selected is selected, and the process returns to step S302.

In step S308, the fact that the currently selected communication interface is to be used as the communication interface for transmitting and receiving the debug command and its response is stored in the memory of the host machine 30, and the process of establishing the communication interface ends. .

Next, a procedure for establishing a communication interface as viewed from the evaluation board 20 according to the third embodiment will be described with reference to the flowchart of FIG. When the power is turned on on the evaluation board 20 side, the process of step S321 is started. Step S321 is a state of waiting for the reception of the test command sent from the host machine 30, and the process of step S322 is performed by receiving the test command from the host machine 30 side. In step S322, it is determined whether the command sent from the host machine 30 is a test command. If the command is a test command, step S323 is executed. If it is not a test command, step S325 is executed. In step S323, the process specified by the test command sent from the host machine 30 is performed. In step S324, a response is sent from each of the plurality of communication interfaces as a response to the test command, with the result of the process specified by the test command, and the process returns to step S321. That is, a response to the test command is transmitted using each of the communication interface 61 and the communication interface 62.

In step S325, in the subsequent processing, the value indicating the communication interface received in step S322 is used as the value indicating the communication interface for transmitting and receiving the debug command and its response.
3 and by sending out a response to the received command using the communication interface,
The process of establishing the communication interface ends.

The test command refers to the debug target L mounted on the evaluation board 20 from the host machine 30 side.
This is a command for determining whether or not the debugging of the SI 10 can be executed. The command is for testing whether communication between the LSI 10 to be debugged including the evaluation board 20 and the host machine 30 can be normally performed, LSI1
This is a command for performing a read / write test on the data RAM 103 in 0. The test results are output from the evaluation board 20 to the host machine 30 as a response to the test command. That is, the host machine 30 executes the test command for the debug target LSI 10 mounted on the evaluation boat 20 to execute the test and debug of the data RAM 1 in the test and debug target LSI 10 of the communication interface 61 and the communication interface 62, respectively.
03 test is performed.

As a result, the host machine 30 communicates with the communication interface usable in the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112, and the communication interface in the LSI 10 to be debugged. Data RAM1
03 can be read or written. If the host machine 30 determines that it is possible to debug the LSI 10 to be debugged, the subsequent communication is performed via one of the communication interface circuits based on the test result.

Next, the operation after the establishment of the communication interface will be described. Since the operation after the establishment of the communication interface is the same as that of the first and second embodiments, the description of the operation of that portion is omitted here.

As described above, the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112
And communication control modules C1M and C2M corresponding to the first communication interface circuit 111 and the second communication interface circuit 112, respectively. In addition, as a communication interface selecting means for selecting one of the two communication interfaces 61 and 62, the host machine 3
It has a communication interface establishment procedure including a step of testing the communication interface according to a test request by a test command from 0, and a step of returning a response of the test result by each of the two communication interfaces 61 and 62. Therefore, even if a part of the upstream transmission path from the debug target LSI 10 to the host machine 30 has a failure in the two communication interfaces 61 and 62 by this communication interface establishment procedure, the host machine 30 has a failure. Since the communication interface can be immediately known, there is an effect that a defective communication interface can be detected in a short time.

Further, if there is a problem in the downstream transmission path from the host machine 30 in the communication interface to the LSI to be debugged, the host machine 30 cannot receive the expected response. In the establishment procedure, two communication interfaces 61, 6
And a step of transmitting a test command by selecting a communication interface which has not been selected before. As a result, a normally operating communication interface can be checked and selected, so that even if one of the communication interface 61 and the communication interface 62 cannot be used, it is possible to know which communication interface circuit can be used. Therefore, there is an effect that a debug target LSI having a built-in debug mechanism with high reliability can be easily obtained.

Also, due to the limitations of the evaluation board 20, the first
Even when only one communication interface circuit of the communication interface circuit 111 or the second communication interface circuit 112 can be mounted, the host machine 30
Since the communication interface that can be used for debugging can be known by the communication interface establishment procedure, there is an effect that debugging and evaluation can be performed using the communication interface.

Further, the communication interface 60 in the first embodiment can be deleted, ie, the communication interface 6
Since the number of the communication ports 110, the connectors 210 on the evaluation board, and the cables 400 included in the software debug device 1 can be reduced, the cost of the software debug device 1 can be reduced.

The first communication interface circuit 111
And the second communication interface circuit 112 are respectively a bit I / O, a parallel I / O, an asynchronous communication control circuit or a synchronous communication control circuit for performing general parallel / serial or serial / parallel conversion, and JTAG.
Any of the serial interface circuits of the specification may be used.

Here, two communication interfaces for transmitting and receiving a debug command and its response, that is, the communication interface 61 including the first communication interface circuit 111 and the communication interface 62 including the second communication interface circuit 112, are shown. But
The number of communication interfaces may be n. “N” is a natural number of 2 or more. At this time, n communication interface circuits and n communication interfaces corresponding to n communication interfaces in the communication interface module 504 respectively.
Communication control modules are required.

Even when all of the n communication interface circuits cannot be mounted on the evaluation board 20 due to the restriction of the evaluation board 20, the host machine 30 can know the communication interface that can be used for debugging by the communication interface establishing procedure. It is possible to select a communication interface to be used for transmitting and receiving a debug command and its response from those available communication interfaces, and to perform debugging and evaluation by using the selected communication interface. This has the effect.

[0091]

According to the first aspect of the present invention, there is provided a data processing device having a built-in debugging function, which includes a plurality of communication interface circuits and a plurality of communication control module programs respectively corresponding to the plurality of communication interface circuits, and performs debugging. The processing designated by the execution program is a digital value for selecting one of a plurality of communication interface circuits from the host machine. If so, a first step in which the digital value is taken into the processor, and after the first step, a command for debugging and a response thereof via the communication control module corresponding to the communication interface circuit selected by the digital value. And the second step of transmitting and receiving It was. As a result, even if there is a communication interface circuit that cannot be used among the plurality of communication interface circuits, it can be used among the plurality of communication interface circuits and can be used for transmitting and receiving a command for debugging and its response. Since the digital value for selecting one communication interface circuit can be received from the host machine, debugging can be performed via the communication control module corresponding to the communication interface circuit selected by the digital value. As a result, it is possible to obtain a data processing device with a built-in debugging mechanism with improved reliability.

In the data processing apparatus with a built-in debugging function according to the second invention, the processing specified by the execution program further includes a processor for receiving a test request from the host machine before the first and second steps. Includes a third step of transmitting the test response data to the host machine via the same communication interface circuit. As a result, even if there is an unusable communication interface circuit among the plurality of communication interface circuits, The machine can test each of the plurality of communication interface circuits based on the third step. Based on the test result, the machine can be used in the plurality of communication interface circuits, and a command for debugging can be provided. One of the communication interfaces that can be used to send and receive the response Since it is possible to receive a digital value for selecting a circuit from the host machine, debugging can be performed via the communication control module corresponding to the communication interface circuit selected by the digital value. There is an effect that a data processing device with a built-in debug mechanism with improved performance can be obtained.

In the data processing device with a built-in debugging function according to the third invention, a communication interface different from the plurality of communication interfaces is further provided, and a digital value for selecting one of the communication interfaces is received. It is performed by another communication interface. As a result, even if there is an unusable communication interface circuit among a plurality of communication interface circuits, receiving a digital value for selecting one of the communication interface circuits that can be easily operated by another communication interface circuit. In addition, when all of the plurality of communication interfaces cannot be used, this fact can be notified by another communication interface, so that a data processing device with a built-in debugging mechanism with higher reliability can be obtained.

In the data processing apparatus with a built-in debugging function according to the fourth invention, receiving a digital value for selecting one of the communication interface circuits is performed by any of the plurality of communication interface circuits operable. Since it is performed by one communication interface circuit, it can be realized without providing another communication interface circuit to receive a digital value for selecting one of the communication interface circuits, and a built-in debug mechanism There is an effect that the cost of the data processing device can be reduced.

In the data processing device with a built-in debugging function according to the fifth invention, a plurality of communication interface circuits and a plurality of communication control modules respectively corresponding to the plurality of communication interface circuits are included. The processing instructed by the execution program, which is configured by the memory in which the program is stored and the processor, when a test request is received from the host machine,
A fourth step in which the processor sends test response data to the host machine via each of the plurality of communication interface circuits is included. As a result, even if there is a communication interface circuit that cannot be used among the plurality of communication interface circuits, the fourth step is to use the communication interface circuit to transmit and receive a command for debugging and a response thereof in the plurality of communication interface circuits. A data processing device with a built-in debugging mechanism that shortens the preparation time before debugging, because it is possible to know in a short time the communication interface circuit capable of performing debugging, and it is possible to perform debugging by selecting the communication interface circuit. Is obtained.

In the host machine according to the sixth aspect of the present invention, a control program for controlling debugging of a data processing device having a built-in debugging mechanism is built in, and a processing unit for controlling debugging of the data processing device and a plurality of communication interfaces are provided. The processing instructed by the control program of the processing unit includes a first step of transmitting a command requesting a test to the data processing apparatus, and a data processing apparatus responding to the command requesting the test in the first step. A second step of receiving a response from the second step, and selecting one of the communication interfaces by determining the response received in the second step, and transmitting a digital value corresponding to the selected communication interface. 3
After the establishment of the communication interface, a command and a response to the command are transmitted and received using any one of the communication interfaces. As a result, even if there is a communication interface that cannot be used among multiple communication interfaces, it can be used among multiple communication interfaces by the communication interface establishment procedure, and it can be used to send and receive commands for debugging and its response. A digital value corresponding to any one of the communication interfaces is transmitted, and debugging can be performed by selecting the communication interface, thereby obtaining a host machine for debugging with improved reliability. It works.

In the recording medium according to the tenth aspect, the control program recorded on the recording medium is written in the memory of the host machine, and the data processing device is controlled, whereby the same processing as in the sixth aspect is achieved. The effect is obtained.

[0098] The host machine according to the seventh aspect of the present invention further comprises a communication interface different from the plurality of communication interfaces, and the transmission of the digital value corresponding to the selected communication interface in the third step is performed by another communication interface. This is performed by the interface. As a result, even if there is a communication interface that cannot be used among the plurality of communication interfaces, it is possible to transmit a digital value for selecting any one communication interface that can be easily operated by another communication interface, By selecting a communication interface based on the digital value, debugging can be performed. Further, when all of the plurality of communication interfaces cannot be used, the fact can be notified by another communication interface, so that reliability can be improved. This has the effect that a host machine for improved debugging can be obtained.

In the host machine according to the eighth aspect, the transmission of the digital value corresponding to the selected communication interface in the third step is performed by any one of the plurality of communication interfaces. Since it is performed, there is no need to provide another communication interface for transmitting a digital value for selecting one of the communication interfaces, so that the cost of the host machine for debugging can be reduced. This has the effect.

In the host machine according to the ninth aspect of the present invention, a control program for controlling debugging of a data processing device having a built-in debugging mechanism is built in, and a processing unit for controlling debugging of the data processing device and a plurality of communication interfaces are provided. The processing instructed by the control program of the processing unit includes a first step of transmitting a command requesting a test to the data processing apparatus, and a data processing apparatus responding to the command requesting the test in the first step. And a second step of receiving a response from each of the plurality of communication interfaces from the communication interface. After the communication interface is established, a command and its command are transmitted using any one of the communication interfaces. Send and receive responses to commands One in which the. As a result, even if there is an unusable communication interface among the plurality of communication interfaces, the communication interface establishment procedure can be used to transmit and receive a command for debugging among the plurality of communication interfaces and its response. The communication interface can be known in a short time, and debugging can be performed by selecting the communication interface, so that a reliable host machine with a short preparation time and improved reliability can be obtained. To play.

In the recording medium according to the eleventh invention, the control program recorded on the recording medium is written into the memory of the host machine, and the data processing device is controlled, whereby the same processing as the ninth invention is performed. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a software debug device 1 according to a first embodiment, a second embodiment, or a third embodiment of the present invention.

FIG. 2 is a debug target L according to the first embodiment of the present invention.
FIG. 2 is a configuration diagram showing an H / W internal configuration of an SI and an evaluation board 20;

FIG. 3 is an instruction ROM 10 according to the first embodiment of the present invention.
FIG. 4 is a configuration diagram of a debugger processing program 500 stored in the second embodiment.

FIG. 4 is a host machine 3 according to the first embodiment of the present invention.
9 is a flowchart illustrating a procedure for establishing a communication interface as viewed from the 0 side.

FIG. 5 is an evaluation board 20 according to the first embodiment of the present invention.
6 is a flowchart showing a procedure for establishing a communication interface as viewed from the side.

FIG. 6 is a flowchart illustrating a procedure of a debug command process according to the first embodiment of the present invention.

FIG. 7 is a debug target L according to the second embodiment of the present invention.
FIG. 2 is a configuration diagram showing an H / W internal configuration of an SI and an evaluation board 20;

FIG. 8 shows a host machine 3 according to the second embodiment of the present invention.
9 is a flowchart illustrating a procedure for establishing a communication interface as viewed from the 0 side.

FIG. 9 is an evaluation board 20 according to the second embodiment of the present invention.
6 is a flowchart showing a procedure for establishing a communication interface as viewed from the side.

FIG. 10 is a flowchart showing a procedure for establishing a communication interface as viewed from the host machine 30 according to the third embodiment of the present invention.

FIG. 11 is an evaluation board 2 according to the third embodiment of the present invention.
9 is a flowchart illustrating a procedure for establishing a communication interface as viewed from the 0 side.

FIG. 12 is a configuration diagram of a conventional software debug device.

[Explanation of symbols]

 Reference Signs 20 evaluation board 30 host machine 31 processing unit 60, 61, 62 communication interface 101 processor 102 instruction ROM 103 data RAM 110 communication port 111 first communication interface circuit 112 second communication interface circuit 400, 401, 402 cable CP1M, C1M, C2M Communication control module

Claims (11)

[Claims] 1. A plurality of communication interface circuits each connected to a host machine, and a plurality of communication control modules which are programs for performing communication control corresponding to each of the plurality of communication interface circuits are included. A memory for storing an execution program for performing debugging, and a processor for reading and executing the execution program stored in the memory. The processing instructed by the execution program includes: When a digital value for selecting any one of the plurality of communication interface circuits is received from a machine, a first step in which the digital value is taken into the processor, and (2) a first step of: Communication control corresponding to the communication interface circuit selected by the digital value later A data processing device with a built-in debugging mechanism, comprising: a second step of transmitting and receiving a command for debugging and a response to the command via a module. 2. The process instructed by the execution program further includes: when a test request is received from a host machine via one of a plurality of communication interface circuits before a first step, Thirdly, the test response data is sent to the host machine via the same communication interface circuit as the communication interface circuit that received the test request.
2. The data processing device with a built-in debugging mechanism according to claim 1, further comprising: 3. A communication interface circuit different from the plurality of communication interface circuits, wherein receiving the digital value for selecting one of the communication interface circuits is performed by the another communication interface circuit. 3. A data processing device having a built-in debugging mechanism according to claim 1. 4. Receiving a digital value for selecting one of the communication interface circuits is performed by any one of the communication interface circuits operable among the plurality of communication interface circuits. 3. The data processing device with a built-in debugging mechanism according to claim 1, wherein 5. A communication system comprising: a plurality of communication interface circuits each connected to a host machine; and a plurality of communication control modules which are programs for controlling communication corresponding to each of the plurality of communication interface circuits. A memory that stores an execution program for performing debugging, and a processor that reads and executes the execution program stored in the memory. The processing instructed by the execution program is performed by a host machine. A data processing device with a built-in debugging mechanism, characterized by including a step of, when a request is received, sending the test response data to the host machine via each of the plurality of communication interface circuits. 6. A plurality of communications, each of which includes a control program for performing a debug control of a data processing device having a built-in debug mechanism, and a processing unit for performing a debug control of the data processing device, and a connection between the processing unit and the data processing device. An interface, wherein the processing instructed by the control program of the processing unit includes: (1) a first step of transmitting a command requesting a test to the data processing device; A second step of receiving a response from the data processing device to a command requesting a test according to the step of: Selecting and transmitting a digital value corresponding to the selected communication interface. Has an interface establishment procedure after establishing the communication interface host machine, characterized by being configured to send and receive a response takes place to the command and the command by using the any one communication interface. 7. The communication system according to claim 1, further comprising a communication interface different from the plurality of communication interfaces, wherein the transmission of the digital value corresponding to the selected communication interface in the third step is performed by the another communication interface. The host machine according to claim 6, wherein 8. The transmission of a digital value corresponding to the selected communication interface in the third step is performed by any one of the plurality of communication interfaces operable. 6. The host machine according to 6. 9. A control program for performing a debug control of a data processing device having a built-in debug mechanism, a processing unit for performing the debug control of the data processing device, and a plurality of communications for respectively connecting the data processing device and the processing unit. An interface; and a process instructed by the control program of the processing unit includes: (1) a first step of transmitting a command requesting a test to the data processing device; Receiving the response from the data processing device to the command requesting the test by the steps of the above from the respective communication interfaces of the plurality of communication interfaces. After that, the command and its command are A host machine configured to transmit and receive a response to a command. 10. A control program stored in a memory of a host machine for performing a debugging control of a data processing device having a built-in debugging mechanism. The processing instructed by the control program is as follows: A first step of transmitting a command requesting a test to the data processing apparatus; and (2) a second step of receiving a response from the data processing apparatus to the command requesting a test in the first step. Steps and
(3) a communication interface including a third step of selecting one of the communication interfaces by determining the response received in the second step and transmitting a digital value corresponding to the selected communication interface; After the communication interface is established, the control program for controlling the host machine so as to transmit and receive a command and a response to the command using any one of the communication interfaces is stored. A recording medium readable by the host machine. 11. A control program stored in a memory of a host machine for performing a debugging control of a data processing device having a built-in debugging mechanism. The processing instructed by the control program is as follows: A first step of transmitting a command requesting a test to the data processing apparatus; and (2) transmitting a response from the data processing apparatus to the command requesting a test in the first step to the plurality of communication interfaces. And a second step of receiving from each of the communication interfaces. After the communication interface is established, a command and a response to the command are transmitted and received using any one of the communication interfaces. The control program for controlling the host machine to Readable recording medium by said host machine that stores grams.