JP2001045370A - Integrated video processing system having plural video source for realizing picture-in-picture by on-screen display graphics - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply simultaneous plural picture display functions by adding a P-in-P function at the minimum costs to an integrated digital video system such as a digital video set top box or a digital video disk player. SOLUTION: A 2:1 MUX 202 selects any of an extended video (1), a non- compressed video (2), and a video obtained by setting the expanded or non- compressed video in a P-in-P display support according to a pixel selection control signal from a processor, and transmits it to an OSD mixing logic 204 as a basic input. Also, as the function of (3), the arrangement and size of inserted pictures can be arbitrarily controlled. Moreover, ODS graphics can be superimposed on an OSD mixing logic, and they are integrated and transmitted to a display device. Those functions can be integrated into an integrated digital video system as one chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention is generally directed to video signal processing, and more particularly, to receiving a compressed digital video signal and an uncompressed analog video signal, With or without display graphics overlay, the picture-in-picture
e) It is directed to an integrated digital video processing system that can be merged into a display. As an example,
The integrated digital video processing system can be implemented as a digital video set top box (STB) or digital video disc (DVD) player.

[0002]

2. Description of the Related Art Today, multiple functions are commonly integrated onto a single system chip. For example, external inputs or functions may be required to increase the marketability of integrated digital video processing system chips, such as digital video system chips used in set top boxes or digital video disc players. It would be desirable to be able to couple to an integrated system chip.

In general, a picture-in-picture television system displays a picture as a main screen and places a given number of sub-screens having mutually identical image sources on the main screen. It is arranged and displayed at a predetermined place. Typically, a television system may or may not include an intra-picture module, in which case the television system will include a non-picture-in-picture system. Typically, the picture-in-picture features of a television system distinguish high-end television systems from low-end television systems. Systems that present pictures-in-picture often cost significantly more than similar televisions that do not have pictures-in-picture.

[0004]

SUMMARY OF THE INVENTION Here, digital
Ability to display multiple pictures simultaneously, adding picture-in-picture features with minimal additional product cost to an integrated digital video system such as a video decode set top box or digital video disc player Has been recognized for providing non-in-picture picture television systems.

[0005]

SUMMARY OF THE INVENTION Briefly summarized, the present invention comprises, in one aspect, a method of forming a multi-screen display for presentation to a non-picture-in-picture television system. The method includes receiving and decoding a compressed digital video signal to generate an expanded (decompressed) digital video signal, receiving an uncompressed video signal, decompressing the expanded digital video signal. And the uncompressed video signal to generate a multi-screen display signal for the television system, thereby providing the ability to simultaneously display multiple screens to a non-in-picture picture television system. Including providing.

In another aspect, a method for processing an analog video signal is provided. The method includes digitizing an analog video signal for input to a digital video processing system, and converting the digitized video signal and on-screen display (OSD) graphics within the digital video processing system. Including mixing.

In yet another aspect, a system for forming a multi-screen display for a non-picture-in-picture television system is provided. The system includes a video decoder that decodes a compressed digital video signal from a first video source to generate an expanded digital video signal. Further, the system includes an input for receiving an uncompressed video signal from the second video source to a video decoder. The video decoder uses a decompressed digital
The ability to merge a video signal and an uncompressed video signal to generate a multi-screen display signal for a television system, thereby displaying multiple screens simultaneously, is a non-picture-in-picture television system. Adapted to provide

[0008] In yet another aspect, a system for processing an analog video signal is provided. The system includes a digital video processing system and a digital multi-standard decoder.
A digital multi-standard decoder digitizes an analog video signal for input to a digital video processing system. Digital video processing systems mix digitized video signals with on-screen display (OSD) graphics,
It is adapted to output as a mixed video signal.

In a further aspect, the present invention provides an article of manufacture comprising a computer program product. This computer program product is a non-picture-in-picture
Having a computer usable medium including computer readable program code means for forming a multi-screen display for a television system. The computer readable program code means within the computer program product may be a compressed digital
Computer readable program code means for causing a computer to decode a video signal to generate an expanded digital video signal; and a computer readable program means for causing the computer to receive an uncompressed video signal. Code means for merging the decompressed digital video signal and the uncompressed video signal to generate a multi-screen display signal for the television system, thereby defeating the ability to display multiple pictures simultaneously. Computer readable program code means for causing a computer to provide to a picture-in-picture television system.

[0010] In a further aspect, the invention includes an article of manufacture including a computer program product. The computer program product has a computer usable medium including computer readable program code means for processing an analog video signal. The computer readable program code means within the computer program product includes computer readable program code means for causing a computer to digitize an analog video signal, and digitized video signal and on-screen display (OSD). Computer-readable program code means for causing a computer to mix graphics and present it to a television system.

In other words, in one embodiment,
Integrated digital that can receive compressed digital video signals and uncompressed analog video signals and merge them into a picture-in-picture display for television systems that lack picture-in-picture capabilities -A video processing system is provided here. As an enhanced system, the picture-in-picture display generated by the integrated digital video processing system can be overlaid with on-screen display (OSD) graphics. In an alternative embodiment,
An integrated digital video processing system is provided that can receive an analog video signal and overlay it with OSD graphics before presenting it to a television system for display.

An integrated digital video processing system comprises:
For example, a digital video set top box (STB) or a digital video disc (DV)
D) It can be realized as a player. In accordance with the present invention, picture-in-picture capabilities and OSD graphics overlay capabilities can be added via a set top box controller chip with minimal additional product cost. The uncompressed analog video that forms part of the resulting picture-in-picture is a video cassette recorder, camcorder, television camera, laser disk, DVD player,
It can be derived from any one of a number of sources, including a computer with a TV output, a cable television signal, a satellite analog channel, or a tuner connection antenna. Advantageously, in one embodiment of the invention presented herein, the mixing / mixing of the uncompressed video with the decompressed video is performed in the last stage of the video processing of the video decoder, and thus The logic required to provide video decompression and on-screen display is free to continue video decompression, display refresh, and video downscaling.

[0013]

DETAILED DESCRIPTION OF THE INVENTION Generally speaking, for example, for a digital video set top box (STB) or digital video disc (DVD) player, an in-picture non-picture television system An integrated digital video decoding system that provides intra-picture picture capabilities is presented herein.
In addition, on-screen display graphics can be mixed with uncompressed analog input signals from, for example, cables, satellites, video cassette recorders, or external tuners, and integrated digital video decoding An integrated digital video processing system having the ability to mix OSD graphics with the composite multi-screen display generated by the system is presented here.

The input of the analog (or secondary digital) video stream may be, for example, the aforementioned "digital video decode system chip programmable external graphics / video port".
(Programmable External Graphics / Video Port For Di
gital Video Decode System Chip) via an external graphics / video (EGV) port as described in a co-filed patent application.
Briefly summarized, the EGV port includes a programmable bi-directional port for a video decoder system chip having a video decoder and an internal digital display generator circuit. The EGV port is
A fixed number of signal inputs / outputs (I /
O) using the external graphics controller, the external digital display generator circuit, and a plurality of connection configurations for the external digital multi-standard decoder, using the video decoder or the internal digital display generator circuit of the chip; To provide. The EGV port includes a receiver / driver circuit that provides a plurality of input / output signals including a pixel data signal and a corresponding synchronization signal in parallel.

Further, for one embodiment of generating reduced size decompressed video signals for display on, for example, a conventional television system, the integrated "integrated scaling and display function" is described above. Have M
PEG Video Decoder With
Reference may be made to a patent application entitled Integrated Scaling And Display Functions). The downscaling of the decompressed video will be described in detail later with reference to FIGS. One embodiment of the OSD domain processor is a "Color Mapped And Direct Color OSD Registrar" with support for 4: 2: 2 profile decoding.
on Processor With Support For 4: 2: 2 Profile Decode
As described in detail in the application entitled Function), graphics OSD overlays are a commercially available capability that will be noted further below. In one embodiment, the capabilities described in these applications are incorporated into an integrated digital video decoding system used in accordance with the principles of the present invention. However, the teachings of these applications are incorporated by way of example only. Another approach is
It will be apparent to those skilled in the art based on the description provided herein.

As is well known, the MPEG-2 standard describes a digital video encoding method that produces substantial bandwidth reduction by essentially irreversible compression with lossless compression. The compressed and encoded digital data is subsequently decompressed and decoded in an MPEG-2 decoder. As an example, decoding of video according to the MPEG-2 standard is described in detail in the aforementioned incorporated commonly assigned U.S. Pat. No. 5,576,765 entitled "Video Decoder". I have.

In the following, the present invention is directed to US Pat.
MPEG-2 video as described in US Pat.
Although described in connection with a decoder, the present invention
It is not limited to use with two decoders, but can be used in any integrated video processing system where enhanced graphics and / or video processing implementations are desired.

By way of background, FIG. 1 shows a diagram of a conventional video decoder. The compressed data enters as signal 11 and is stored in compressed data memory 12. A variable length decoder (VLD) 14 reads the compressed data as a signal 13, sends the motion compensation information as a signal 16 to a motion compensation (MC) unit 17, and uses the quantized coefficient as a signal 15 to perform inverse quantization (IQ). Send to unit 18. The motion compensation unit reads the reference data as a signal 19 from the reference frame memory 20 and forms a predicted macroblock. The predicted macroblock is signal 2
It is sent to the adder 25 as 2. The inverse quantization unit calculates unquantized coefficients. This coefficient is sent as a signal 21 to an inverse transform (IDCT) unit 23. The inverse transform unit calculates the reconstructed difference macroblock as an inverse transform of the unquantized coefficients. The reconstructed difference macroblock is sent as a signal 24 to an adder 25, where it is added to the predicted macroblock.
The adder 25 calculates the reconstructed macroblock as the sum of the reconstructed difference macroblock and the predicted macroblock. The reconstructed macroblock is then sent as signal 26 to a demultiplexer 27, which, if the macroblock came from a reference picture, uses the reconstructed macroblock as signal 29 in a reference memory. Or externally as signal 28 (to memory or display)
send. The reference frame is sent as a signal 30 from the reference frame memory to the outside.

A partial embodiment of a decoding system chip using the concepts of the present invention is shown generally in FIG. The system 40 includes, for example, a PCI bus
An interface 44 is included which couples the decoding system 40 to the PCI bus 42. The MPEG encoded video data is fetched from the PCI bus 42 by a DMA controller 46, which transfers the data to a video first in first out (FIF)
O) Write to the buffer 48. In addition, the DMA controller fetches on-screen display (OSD) and / or audio data from the PCI bus 42 and
/ Write to audio FIFO 50. Memory controller 52 places the video data into the correct memory buffer in dynamic random access memory (DRAM) 53. Next, the MPEG compressed video data is retrieved from DRAM 53 by video decoder 54 and decoded as described above in connection with FIG. Typically, the decoded video data is stored in a frame buffer of DRAM 53 for subsequent use. When a reference frame is needed or when video data is output from the decoding system, the DRA
The stored data in M53 is retrieved by the memory controller and displayed and displayed on the OSD interface 58.
And transferred via a digital video encoder / digital-to-analog converter chip 59. Further, the audio data retrieved by the video controller 52 is output via the audio interface 60.

As noted briefly above, the present invention provides for
One aspect is directed to providing digital video decoding systems with the ability to implement picture-in-picture features. Another aspect of the invention is directed to providing a digital video decoding system with the ability to overlay graphics over an analog video signal. An analog video signal is, for example,
The integrated "Digital Video Decode"
Programmable External Graphics on System Chip "
/ Video Port For Digital Video Decode System Chip)
And input to a digital video processing system via an external graphics / video (EGV) port as described in a co-filed patent application. The present invention utilizes two features of the integrated digital video decoding system described in the originally incorporated application. In particular, the present invention relates to the aforementioned ability to mix on-screen display (OSD) graphics with analog video channels, and to extend decompressed digital video to an area containing a portion of full screen size. Use the ability to downscale. These features are described in further detail hereafter and in the incorporated application.

FIG. 3 illustrates one embodiment of a display screen 70 of a television system for displaying images generated by an integrated digital video decoding system in accordance with the principles of the present invention. As is well known, screen 70 displays an image through a plurality of pixels 71 that extend across the screen. Within screen 70, a first picture 72 is shown positioned within a larger picture 74. Thus, FIG. 3 is an example of a picture-in-picture or multi-screen display.

FIG. 4 illustrates generally at 100 one embodiment of a digital video decode system chip incorporating the principles of the present invention. The system 100
For example, a digital video signal 101 is received from a first video source, such as a cable or satellite source. The signal 101 is transferred through a network interface module (NIM) 102 and
02 outputs the MPEG transport stream to the transport logic 103, which includes a part of the integrated system 100. Transport 103 demultiplexes the transport stream and converts the compressed video stream to the video stream in the integrated system.
To the decoder 106 (see FIG. 2). The video decoder generates a decompressed MPEG video signal, which is an internal digital video encoder (DENC).
It is ultimately transferred to macro 107 and formatted for a television system (not shown). Digital-to-analog conversion of the video signal occurs prior to output 110 to the television system.

In accordance with the principles of the present invention, the size of the decompressed digital video is reduced, in one embodiment, to a partial picture display size, such that the window 72 in FIG.
The downscaling capability of video decoder 106 (described in detail below in connection with FIGS. 6-12) is used to present as a secondary window such as. Other pictures forming the picture-in-picture representation are, for example, the aforementioned "digital
Video Decode System Chip Programmable External Graphics / Video Port "(Programmable
External Graphics / Video Port For Digital Video De
code system chip) as an uncompressed video signal via an external graphics / video port described in the application. Alternatively, one of ordinary skill in the art can input an uncompressed video signal to an integrated digital processing system that includes a video decoder.
A dedicated port could be built. The uncompressed signal is received from a second video source,
Other digital or analog signals may be included.

If the analog video signal 104 is received from, for example, a cable, satellite, VCR, or tuner source, a digital multi-standard decoder (DMSD) 105 digitizes the analog signal to provide an integrated digital signal. -Input to the video decode system 100. DMSD 10 for video decoder and associated display and OSD logic 106
5 are described in the aforementioned incorporated EGV port application. DMSD 105 provides digital conversion of analog video signals and (1)
Video decoder and internal DENC)
Note that it will be the sync master to. DMSD
105 is, for example, a horizontal synchronization and vertical synchronization input port,
Display / OSD of video decoder via CCIR-656 SAV / EAV code word or similar means
Provides a synchronization signal to both the unit and the internal DENC. The latter two units are responsible for interpreting the synchronization information and correctly processing the data. The means for performing this can be, for example, a standard operation using a synchronous slave signal.

FIG. 5 illustrates a video decoder / display and OS to incorporate merge and mix capabilities in accordance with the present invention.
One embodiment of modifying the D logic 106 is shown. In this embodiment, the 2: 1 MUX 202 is controlled by a "pixel select control" signal generated by the processor.
Is decompressed digital video, ie, decompressed video derived from an MPEG stream received via transport 103, or uncompressed video, ie, analog (or digital) received via DMSD 105. Select one of the signals. In one embodiment, "pixel selection control" has three modes of operation set by the host processor. The host processor controls the pixel selection,
(1) transferring the decompressed video to a display,
(2) transfer uncompressed video to the display, or (3) set to support picture-in-picture display, allowing both decompressed and uncompressed video to be dynamically displayed for display. Can be selected. In mode (3), switching between decompressed video and uncompressed video for simultaneous display is a secondary picture 72 (see FIG. 3).
At a rate according to the desired position of

In one embodiment, the decompressed digital video is downscaled to form a window in a larger picture containing the uncompressed video. Therefore, the "pixel selection control" signal is
From the top leftmost position on the display screen, pixel information from decompressed or uncompressed video travels from left to right within the raster scan line and from top to bottom of the display screen. Command what should be used. In this regard, it should be noted that the placement of the inserted pictures, and the size of the inserted pictures, can be readily modified by those skilled in the art without departing from the teachings of the present invention. The resulting video output from the 2: 1 MUX 202 is the integrated digital video decode
It is sent as a basic input to the OSD mixing logic 204 on the system chip 100 (FIG. 4). In addition, OSD graphics mixed with the resulting video can be
And the output of logic 204 is a desired intra-picture with graphics. The function of the OSD mixing logic 204 is the same as that already known in relation to overlaying OSD graphics on decompressed digital video only.

The OSD blend function provides a weighted average of pixel luma and chroma values between video and OSD graphics sources. This average is based on a weighting factor alpha (represented here by 'a') having a range from 0 to 1. The average is calculated as follows: (Video × a) + (OSD × (1−a)) Furthermore, most implementations provide an OSD graphics area composed of one or more regions (rectangles), where the alpha coefficient is (I.e., the mixing need not be constant throughout the OSD). The OSD mixing function used with decompressed digital video is available in products in the art, such as IBM's "MPEG2CS22 Digital Audio / Video Decoder".

In summary, the co-filed and incorporated EGV Port patent application has not been compressed into an integrated digital video decoding system (such as a set top box or digital video disc player). Introduce video stream and output video /
Illustrates the ability to synchronize an audio presentation to a stream. This application presents the additional ability to mix and / or mix graphics into an output video stream. The output video stream is
Merged picture-in-picture video containing an uncompressed video stream or containing both decompressed digital video and uncompressed video
It may include a stream. The mixed stream is then output to an internal digital video encoder (DENC) macro and encoded into a television format. Thus, uncompressed (eg, analog) channels are provided with the same graphical features, functionality, and programming model capabilities as existing digital channels using an integrated digital decoding system. A typical source of uncompressed analog video is a video cassette recorder (VC
R), camcorder, television camera, laser disk, digital video disk player, T
A computer with a V output, a cable television analog channel, a satellite analog channel, a tuner connected antenna (broadcast). Any of these sources may provide a composite television or S-video signal to a digital multi-standard decoder (DMSD) chip, which digitizes the incoming video and converts the digitized video to It sends it to an integrated decoding system where it mixes video signals and mixes graphics.

As noted briefly above, downscaling of decoded digital video is further used in the preferred embodiment. In this embodiment, a stream of picture-in-picture video is generated and displayed on a normal non-picture-in-picture television system. The downscaling of decompressed digital video is incorporated above as a way to free up the television display area for graphics information that may be temporarily more interesting to the viewer when watching television. As described in the related application. The graphics information may be Internet information, program guide information, or any adjustment to an audio or video presentation. Downscaled video can be placed at various locations on the screen.

Since the mixing / mixing of the uncompressed video described herein is performed as the last step in the video processing (see FIG. 2), all that is required to provide video decompression and on-screen display The logic of
Freely decompress the video, refresh the display, and downscale the video. The present application proposes that mixing / mixing be performed between OSD graphics and decompressed digital video or uncompressed analog video. By providing control of the video source selection to dynamically switch between the decompressed digital video of the reduced picture and the uncompressed video source, a full screen uncompressed video is The presented and reduced digital video is presented in the foreground. The placement of the foreground video can be moved under software and user control so that the reduced image does not block significant portions of the full screen video image stream. OSD graphics can be mixed with both images to cover the entire display area. OS
D graphics can be used to place a border around the reduced foreground image, if desired.

As described earlier, the present invention provides an MPE
Includes a decoding system with integrated scaling capabilities that can scale the size of a G-2 video presentation by a predetermined reduction factor. As the MPEG-2 video decoder market becomes more and more competitive, providing high levels of feature integration at the lowest possible cost is a key requirement to achieve market success. The present invention addresses this by providing a scaling mode that reduces the size of the displayed picture by a predetermined factor such as 2 and / or 4 in both the horizontal and vertical axes.

FIG. 6 illustrates one embodiment of a video decoding system according to the principles of the present invention. The video decoding system includes external memory 653, which in the illustrated embodiment includes SDRAM frame buffer storage. The memory 653 interfaces with the memory control unit 652. The memory control unit 652 converts the decoded video data into video data.
Video display unit 69 received from decoder 654
0 to provide video data for display. In accordance with the principles of the present invention, a video decoding system includes a number of features that provide video scaling mode capability.

For example, the decimation unit 682
Supports the regular video decimation mode and video
Modified to include both scaling modes.
The frame buffer 653 stores the decoded video
The data is modified so that it can be stored either in full frame format or a combination of full frame format and scaled video format. Display mode switching logic 696 is provided in video display unit 690 to facilitate seamless switching between regular video mode and scaling video mode. The frame buffer pointer control 686 has been modified to provide the correct frame buffer pointer based on the new partitioning of the frame buffer when in normal video mode and when in scaling video mode. You.

In operation, the MPEG input video source is sent as encoded MPEG-2 video data via the memory control unit 652 to the input of a video decoder 654. The decoder 654 includes a Huffman decoder 672, an inverse quantizer 674, and an inverse DCT 67
6, motion compensation 678, and adder 680. These function as described above in connection with the video decoder of FIG. An internal processor 670 directs the video decoding process and, in accordance with the principles of the present invention, whenever the host desires to switch the video display between a regular video display and a scaled video display, for example. Receive a signal from the system. This signal is shown in FIG. 6 as a "Host Control Format Change" signal. In response to the host format change, control signals are sent from internal processor 670 to Huffman
Decoder 672, inverse quantizer 674, and motion compensation 67
8 and to the upsample logic 694, the display fetch unit 692, and the display mode switch logic 696 in the video display 690. Again, these control signals may be used, for example, to switch the display output between a regular video mode and a scaling video mode, in accordance with the principles of the present invention (as described below). Manage the system.

The decoded full-size macroblocks of video data are sequentially output from video decoder 654 to decimation unit 682. In a decimation unit 682, in one embodiment, a full-size macroblock is one of two types of compression.
Receive seeds. First, if full-size video is desired, decimation of B-coded pictures only
It is preferably performed. In this normal video mode, decimation is the process of reducing the amount of data by interpolating or averaging the combined values to obtain interpolated pixel values. Interpolation reduces the number of pixels,
Therefore, the required external memory in the entire system is small. In the second mode, decimation unit 682 performs picture scaling according to the principles of the present invention. As an example, the type of scaling used may reduce the overall size of the displayed picture by a factor of two or four in both the horizontal and vertical axes.

In addition to providing the decoded stream of full size macroblocks to the decimation unit 682, the video decoder further
3 on the "Motion Compensation Unit Block Complete" signal. This signal informs the decimation unit 682 when the macroblock has been completely decoded. Similarly, decimation unit 682 provides a "decimator busy" signal on line 685 going to motion compensation unit 678 of video decoder 654. This "decimator busy" signal informs the motion compensation unit when the decimation unit is busy and when the decimation unit has completed its operation. After the operation of the decimation unit is completed, the motion compensation unit can proceed to the next macroblock.

The motion compensation unit 678 of the video decoder 654 provides the read video address directly to the memory control unit 652 and the decoded video data (full size) and / or the scaled macroblock to the external memory 653. The write video address is provided to the decimation unit 682 for writing. In parallel with the read video address and the write video address, a pointer is provided by the frame buffer pointer control 686 to the memory control unit. These pointers indicate which frame buffer area in the SDRAM 653 will be given a read video address or write video address according to the partitioning of the frame buffer memory space (as described below) in accordance with the present invention. Specifies what should be accessed by address. These pointers are shown in FIG. 6 as the current pointer and the current small pointer. The current pointer contains the pointer of the full size macroblock, and the current small pointer contains the pointer of the scaled macroblock.

A decimation unit 682 receives the decoded full size macroblock, buffers the information internally, and performs scaling as described below if the scaling mode is activated. I do. In normal mode, decimation
Unit 682 converts the full size macroblock of the decoded video data into frame buffer 65
3 for output to the memory control unit 652 for storage. In the scaling mode, the decimation unit 682 scales the full size macroblock and outputs the scaled macroblock to the memory control unit 652 for storage in the frame buffer 653.

Frame buffer pointer control 686
Controls the rotation of the frame buffer, i.e., the allocation of the frame buffer when in normal video mode and video scaling mode, in accordance with the principles of the present invention (further described below). ).

As further described in the incorporated application, the decimation unit 682 further includes a video display unit 690 when retrieving data for display.
Functions as a part of Specifically, decoded video data including full-size scan lines
Retrieved from frame buffer storage 653,
Sent via decimation unit 682 for B-frame re-extension of the picture. This is done so that video consistency is maintained within the group of pictures, so the reduced resolution of any one picture is not perceptible. After re-expansion, the full size scan line is provided to the display output interface 698.

Alternatively, in video scaling mode, the decoded video containing the scaled scan lines is retrieved from frame buffer storage 653 and sent directly to scan line video buffer 684. . The scan line is split into luminance and chrominance data, and both the current scan line and the previous scan line are sent from scan line video buffer 684 to vertical and horizontal upsample logic 694. Upsample control is received from the display fetch unit 692. The display fetch unit 692 includes letterbox formatting, SIF upsampling,
Adjust upsampling from 4: 2: 0 to 4: 2: 2 and flicker reduction.

Display fetch unit 692 provides a read video address to retrieve a scan line from frame buffer storage 653. The “current pointer, current small pointer” synchronization signal for display is received by the memory control unit 652 from the display mode switching logic 696 of the video display unit 690. As previously noted, the current pointer, current small pointer signal points to the particular frame buffer area where the scan line is to be retrieved, and the read video address signal is retrieved within that frame buffer area. Specify a particular scan line to be performed.

For example, display mode switching logic 696 is provided in accordance with the principles of the present invention to ensure seamless switching between the scaled video mode and the regular video mode. Logic 69
6 receives as input a control signal from the internal processor 670 of the video decoder 654 and also receives a vertical sync (VSYNC) signal (from the display output interface 698) and a B picture “MPEG” from the Huffman decoder 672 of the video decoder 654. -2 repeated field "signal. Vertical sync is an external sync signal that indicates the start of a new display field. The output from the display mode switch logic 696 is a "display format synchronization for display" signal sent to the display fetch unit 692, in addition to the current pointer for display, current small pointer synchronization, and a decimation unit 682.
Is a "display format synchronization for decoding" signal sent to the decoding logic of FIG. Further, the display mode switching logic 696 outputs a “block video” signal to the display output interface 698. This signal is used in accordance with the principles of the present invention to block one display frame during a display mode switch to avoid noise in the display. Video data is received from the upsample logic 694 at the display output interface. The decimation unit, frame buffer partitioning, frame buffer pointer control, and display mode switching logic are all implemented in accordance with the principles of the present invention and are described in detail below with reference to FIGS. You.

First, the frame buffer will be described. The frame buffer is used to store the composed pictures for display and prediction of subsequent pictures. Since the B picture is not used for prediction, its frame buffer is available after the picture has been displayed. For I or P pictures, it is necessary to hold the frame buffer after display, especially to predict B pictures.

FIG. 7 illustrates the allocation of the frame buffer 700 for both normal and scaled video modes in accordance with the principles of the present invention. In normal mode, there are three frame buffers that support the decoding and display process. Frame buffer 0 and frame buffer 1 are allocated for I and P pictures, and frame buffer 2 is
Assigned to B picture. The frame buffer is
The buffer pointer is tagged with the current pointer from the frame buffer pointer control 686 of FIG.

In the scaling video mode, at least five frame buffers are used. Frame buffer 0 and frame buffer 1 are again used for full size I and P picture video. In the example shown, frame buffer 2, frame buffer
At least three other buffers, labeled buffer 4, frame buffer 6, are tagged with small pointers generated by the frame buffer pointer control. These small buffers are used primarily for display purposes when in the scaling video mode. The buffer is small in size to accommodate video scaling. When decoding an I or P picture, the composed pictures are stored in buffer 0 or buffer 1, depending on which is available. At the same time, the scaled down version of the same picture is
Stored in one of buffer 2, frame buffer 4, or frame buffer 6. Next, the full size video is used for prediction and the small size video in the small frame buffer is used for displaying the scaled down picture.

The frame buffer is configured by microcode during initialization of the video decoding system. A memory base address is assigned to each frame buffer, and these memory base addresses are selected by the buffer pointer generated by the frame buffer pointer control. The read and write video addresses refer to a specific address in the selected frame buffer. Unless otherwise indicated, the term "frame buffer" is used herein to include any frame buffer memory configured during initialization. "Frame buffer area" means one of the specific frame buffers shown in FIG.

The video display operates in real time, so the frame buffer pointer needs to be switched according to the vertical synchronization timing. Since decoding is always done before display, it is necessary to make the frame buffer available to store the decoded pictures. Therefore, it is necessary to switch the frame buffer pointer before decoding starts. A copy of the display buffer pointer is maintained to avoid disturbing the display frame buffer. The buffer switch time is the beginning of each picture decode. Further, the display buffer pointer is changed at that point, but it will not be used until the display pointer copy time, which is the beginning of the picture display. One embodiment of normal mode buffer pointer rotation is described below.

In the following description, there are four buffer pointers, each pointer containing two bits to indicate which of the three frame buffers (buffers 0, 1, and 2) are being accessed. Assume that • Current pointer-points to the frame buffer used for the picture being composed. Display pointer-points to the frame buffer used for display. • Future pointer-points to the frame buffer used for backward prediction. • Past pointer-points to the frame buffer used for forward prediction.

At the start, future pointers are initialized to "1" and other pointers are set to "0". I or P
At the start of the picture, the value from the past pointer is loaded into the current pointer and the value from the future pointer is loaded into the display pointer. The values of the future pointer and the past pointer are exchanged. If the picture being decoded is a B picture, the current pointer and the display pointer are set to "2". Frame buffer 2 is, in one example,
Reserved for B pictures. Future and past pointers are left unchanged. Pointer switching in the normal mode is performed by “Memory Management ForAn MPEG-2 Compl.
Cheney et al., US Patent No. 5,66, entitled iant Decoder).
No. 8,599. This U.S. Patent is incorporated herein by reference in its entirety.

In the scaling video mode, the display time of the picture is delayed by an additional field time according to the invention. The purpose of this delay is to decouple the decoding and display processes so that the decoded and scaled video can be placed anywhere on the screen. FIG.
Shows one example of delayed display timing in a scaling video mode. This display timing depends on the mode, that is, the normal mode or the scaling mode.
It is dynamically adjusted according to the video mode. In order to properly manage the buffer according to the present invention, a one-field time delay is required. In the video scaling mode, again, at least five buffers are assumed. As mentioned above, two of these five buffers include the full-size frame buffer and are shown as frame buffer 0 and frame buffer 1 in FIG. These full size frames
The buffers are the same as the corresponding buffers used in regular video mode. At least three small frame buffers, frame buffer 2, frame buffer 4, and frame buffer 6, are allocated in the same memory space occupied by frame buffer 2 used in normal video mode. It is. These three small frame buffers are controlled by a different algorithm than the one described above.

Specifically, four additional pointers are used in the scaling video mode. These pointers are as follows: • Small Current Pointer-points to a small buffer for the picture in the decimated composition. • Small Display Pointer-points to a small buffer for display. • small future pointer-points to a small buffer for future display. • Small transition pointer-points to a small buffer for the transition.

When the decoder is initialized, the small current pointer, small display pointer, future pointer, and small transition pointer are set to 0, 2, 4, and 6, respectively.
At the start of each decoding of each picture, the small current pointer is loaded from the small transition pointer and the small transition pointer is loaded from the small display pointer. If the picture being decoded is a B-picture, the small display pointer is loaded from the small transition pointer and the small future pointer is left unchanged. If the picture being decoded is an I or P picture, the small display pointer is loaded from the small future pointer, and the small future pointer is loaded from the small transition pointer. One example of switching a small frame buffer according to the present invention is shown in FIG.

The full size frame buffer, frame buffer 0 and frame buffer 1 are switched as if the decoder were operating in normal mode. These two buffers are needed for prediction, but are not needed for scaling video mode display. When an I or P picture is being decoded,
The picture is stored in both buffers pointed to by the current (full frame) pointer and the small current pointer. During decoding of a B picture, the frame buffer 2 pointed to by the current (full frame) pointer will not be used. For decimated pictures, only the small frame buffer identified by the small current pointer is used. In normal mode, the display pointer is used for display, while in scaled video mode, a small display pointer is used. The two buffer switching algorithms operate simultaneously at the start of each decoding of a picture. buffer·
The pointer is simply selected depending on which mode the decoder is in.

Referring now to FIG. 10, there is shown one embodiment of a decimation unit 682 (FIG. 6) used in accordance with the present invention.

In the previous embodiment of the decode and decimation unit, for example, the decimation unit may have a B
The operation is limited to only pictures. However, in the scaled video mode presented here, the decode and decision unit is
Handle type. This is desirable to save memory bandwidth in display time. This is because (in one embodiment) the scaled picture and the multi-plane high resolution OSD graphics may be mixed at the output.

In the embodiment shown in FIG.
The unit includes the decimation logic 800. Decimation logic 800 receives the decoded video data from the video decoder and outputs the decimated data flow to decimation buffer 820. Decimation buffer 820
Are multiplexed with the decoded and undecimated video data received from the video decoder by a multiplexer 830, which outputs the decoded video data and the scaled macroblocks for scaling. -Be stored in the frame buffers 0, 1, 2, 4, and 6 described above in the video mode. The write video address from the motion compensation unit of the video decoder is sent to the memory write control 840 in the decimation unit. Memory write control 84
0 controls the writing of data from the decimation buffer 820. Further, the write video address is output via multiplexer 850 to a memory control unit (see FIG. 6), with or without decimation scaling.

The multiplexers 830 and 850 are controlled by a decimation control signal 810. The decimation control logic receives as input a signal called "MCU_block_complete" from the motion compensation unit of the video decoder. This signal indicates when the decimator can begin writing the scaled macroblock. The decimator notifies the motion compensation unit that it is currently busy via a signal labeled "Decimeter busy".

For a given macroblock, there are two phases. One is the luminance phase and the other is the chrominance phase. Again, each phase requires writing one full size macroblock and one scaling macroblock, assuming the scaling video mode.

The decimation hardware /
Various specific changes to the process are contemplated herein. One change in the data flow of the decimation process is (in one embodiment) the addition of a 4-to-1 horizontal reduction. This reduction is realized by the horizontal decimation function of the decimation logic. This is 1 /
This is to support 16 size scaling.

Another change is in the decimation buffer
Increasing the size to 32 × 32 bits. As the I and P pictures are processed, full size macroblocks are written to memory, and the decimator simultaneously scales down the macroblocks and stores the smaller macroblocks in the decimation buffer 820. After the full-sized macroblock is written to memory, the decimator stores the scaled macroblock in another buffer location in memory (i.e., frame buffer 2, frame buffer 4, or frame buffer 4 in the example above). Write to buffer 6). A larger decimation buffer allows for the storage of small macroblocks.

Again, assuming the scaling video mode, the decimation state machine logic is further modified to allow for two modes of operation. The first mode is B picture processing, and the second mode is reference picture processing. For B picture processing, only small macroblocks are written to memory via the decimation buffer 820. Data is sent to the decimation unit at a rate that allows the motion compensation unit to deliver it. This is because the decimation buffer can hold the entire scaled macroblock. For reference picture operation, a full size macroblock is first written via multiplexer 830, and then a scaled macroblock is written. This requires that the data flow be at the pace of the memory control unit responding to write requests.

There are exceptions to the above process, as the size of the source compressed image may vary. Decimators are only needed when some type of reduction is needed to form a scaled picture. Some video sources are already small in size and one or both dimensions may not require scaling. For example, a 352 × 240 size image is common (typical MPEG-1 size). In this case, it would not be necessary to perform decimation to provide quarter scaling. For reference frames,
A motion compensation unit is needed to write a full size macroblock to a reference frame buffer in memory and then to a display frame buffer in memory. This is because the display process operates on the display frame buffer during scaling.

To reduce the same image size to 1/16 scaling, a decimation step would be required. Again, there are exceptions in this case as well.

One of the purposes of the scaling feature is to remove interlace interference. There is no interlace on a true MPEG-1 image. This is because images are exclusively frame encoded. M
PEG-2 can tolerate interlaced images of the same resolution (352 × 240), and the decimator uses only the top field pictures to create scaled macroblocks. The bottom field is discarded. Therefore, for the reference picture,
The motion compensation unit will need to write the macroblock of the top field picture to both the reference frame buffer and the display buffer. For B pictures, the motion compensation unit would only need to write the top field picture to the display frame buffer.

The video decoding system according to the present invention provides a smooth transition when entering and exiting small picture mode. Since the frame buffer 2 is used to capture and display small picture images (including reference and B pictures) when in the video scaling mode, the decoding process and the display Care must be taken to avoid interference with the process. In addition, there is a one field time latency adjustment that must occur during the transition. The regular display mode has a 1.5 frame latency between decoding and displaying the reference picture and a 0.5 frame latency for the B picture. In the small picture mode, the latency of the reference frame changes to two frames and the latency of the B frame changes to one frame.

For the display format to occur seamlessly, the display must not be in the process of displaying a B-picture when the transition occurs. Otherwise, the picture will appear disturbed. Therefore, the transition needs to occur when the reference picture is being displayed. This is forced to occur by microcode during the sequence header when the first frame of the new sequence is a reference frame and the display is operating over the last frame of the previous sequence.

During the transition to and from the small picture mode, the hardware must make latency adjustments without disrupting the decoding or display process. Frame synchronization needs to be adjusted to the new mode. In addition, field parity must be maintained. The adjustment to small picture mode introduces a one frame time delay.
This may result in a PTS comparison. after,
Skipped frames may be needed to compensate for the time difference. This only happens when entering small picture mode. Synchronization is not lost when exiting small picture mode. Further, the transition will occur when the picture has already been skipped or repeated.

Referring to FIG. 11, the display format change signal is written asynchronously by the host. The format is received as a control signal in the display format register 910, and the microcode waits until processing the sequence header before writing information to the display format register 910. Therefore, this information is stored in the synchronization generator 900 and the register stages 930, 9
40,960. "Register stage 1" 930 captures information at the next frame synchronization. The decoding process is in stage 1 register 930
And the display process uses the stage 3 register 960.

The field counter 920 simply counts down to a value of one from the start number of the field in the frame and repeats. Counter 920 is loaded by synchronization generator 900 via control signals as shown. Further, sync generator 900 receives the vertical sync signal and the output of stage 1 register 930. Sync generator 900 provides three signals: "frame sync".
Create a signal, a "new picture" signal, and a "block video" signal. The "frame sync" signal indicates to the decoding process when to start decoding a new frame. The "new picture" signal indicates to the display process when to start displaying a new frame. "Block video" is used to selectively suppress one frame of a video image while the video decoding system transitions from a normal frame to a scaling frame. The frame sync and "new picture" signals are pulses that are created once every two field times. In normal mode, the signal has 180 degrees out of phase, while in scaling mode, the signal is phased according to the present invention. This is further below,
This will be described with reference to the flowchart of FIG.

In all cases related to switching to scaling picture mode, there are repetitive frames that are blocked from being displayed on the display. A block is needed due to a collision between the current reference frame and the currently displayed reference frame. When the video is blocked, the output of the decoder can be forced to a background color such as black.

The adjustment of the waiting time is performed as soon as the stage 1 register changes. The absence of frame synchronization occurs, which allows the current display frame to be scheduled for repetition. Thus, the sync generator adjusts the frame synchronization to occur in phase with the new picture, resulting in a latency adjustment. During repeated reference frames, the video is blocked for one frame time.

FIG. 12 is a flowchart of one embodiment of the processing realized by the synchronization generator 900 (FIG. 11).

With initialization (1000), the process waits for a vertical sync signal representing the start of a new field (10).
10). Upon receiving the vertical sync signal, the process generates a "new picture" sync signal and queries whether the field is repeated based on the received MPEG-2 syntax (1030). The initial field counter (FC) value depends on whether the field is repeated. If 3: 2 pulldown is used, the initial value of the field counter is 3 (1040); otherwise, normal interlacing is desired and the field counter is loaded with a value of 2. .

Once the field counter is set, the process queries whether scaling should be implemented (1050 and 1070). If no, the decoding system is in non-scaling or regular video mode. In this case, the process waits for the next vertical sync signal (1080) and then queries whether the field count is equal to 2 (1090). If no (eg, because the field counter was loaded with the value 3), the field counter is decremented (11
10), the process waits for the next vertical synchronization signal (1080).
Once the field count equals 2, a "frame sync" signal is generated (1100). after,
The field count is decremented (1110) and the process determines whether the field count value is now equal to one (1120). If the value is equal to one, the process waits for a new vertical sync (1010) before generating a "new picture" signal (1020).

Assuming that the scaling mode is desired, processing proceeds from query 1050 or 1070 to wait for the next vertical synchronization (1130), after which a determination is made whether the field count is equal to one. (1140). If no, the field counter is decremented and processing returns and waits for the next vertical sync (1
130). If the field count value is 1,
A new picture sync signal is generated (1150). Thereafter, the field counter is loaded with a value of 2 and a block video signal is generated (1160). Again, the block video signal is output from the sync generator to the display output interface (see FIG. 6) to block the next frame of video.

After sending the block video signal, processing enters a steady state and the video scaling sub-process begins by waiting for the next vertical sync signal (118).
0). After 1180, processing determines whether the field count is equal to 1 (1190). If no, the process queries whether the field count is equal to 2 (1240), and if no again, the process decrements the field counter (126).
0), and return to wait for the next vertical synchronization signal (118)
0). Otherwise, a determination is made whether the scaling command has now been turned off by the host system (1250). If no, the field counter is decremented and processing waits for the next vertical sync signal (1180). If the scaling mode is switched off, the field counter is decremented at instruction 1110 of the non-scaling process described above.

If the field count is question 1190
, The process generates both a "new picture" signal and a "frame sync" signal with the same phase. Again, to achieve scaling, the latency between the decoding and display processes is changed from 1.5 frame times to 2 frame times for the reference picture, and the new picture signal and frame synchronization are changed. It is necessary to match the phases of the signals. Then, depending on whether regular interlacing or 3: 2 pulldown is desired, the processing is performed by the MPEG-to determine the loading of the field counter with a value of 2 (1230) or 3 (1220). A determination is made as to whether the duplicate field is set (1210). This is necessary even if latency adjustments have been made to provide any type of frame rate conversion. After setting the field counter, the process returns and waits for the next vertical synchronization signal (1180).

The invention can be included, for example, in an article of manufacture having computer usable media (eg, one or more computer program products). This medium embodies, for example, computer readable program code means for providing and promoting the capabilities of the present invention. The product may be included as part of a computer system or sold separately.

Further, to implement the capabilities of the present invention, at least one machine readable program storage device tangibly embodied at least one program of machine executable instructions may be provided.

The flowchart shown here is provided as an example. Variations may exist on these figures or on the steps (or operations) described herein without departing from the spirit of the invention. For example,
In some cases, the steps may be performed in a different order,
Steps may be added, deleted, or modified. All of these variations are considered to constitute part of the present invention as recited in the dependent claims.

Although the present invention has been described in detail herein according to certain preferred embodiments, many modifications and variations may be made by those skilled in the art. Accordingly, it is intended by the dependent claims to cover all such modifications and changes as falling within the true spirit and scope of the present invention.

In summary, the following items are disclosed regarding the configuration of the present invention. (1) A method for forming a multi-screen display for a non-in-picture picture television system, comprising: receiving and decoding a compressed digital video signal to generate an expanded digital video signal; Receiving an uncompressed video signal and merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system, thereby providing multiple Providing the ability to simultaneously display multiple pictures to the non-picture-in-picture television system. (2) down-scaling the expanded digital video signal before merging it with the uncompressed video signal, wherein the expanded and down-scaled digital video signal is The method according to (1) above, comprising at least one screen. (3) The method according to (2), wherein the uncompressed video signal includes an uncompressed analog video signal. (4) the merging comprises switching between the decompressed digital video signal and the uncompressed analog video signal to create at least some video frames for display on the television system. The method of claim 1, wherein the switching comprises creating the multi-screen display. (5) further comprising mixing on-screen display (OSD) graphics with at least one of the decompressed digital video signal and the uncompressed video signal, wherein the multi-screen display includes the decompressed video signal. The method of claim 1, including a digital video signal and the uncompressed video signal. (6) The method of (1) above, comprising implementing the method in at least one of a digital video set top box (STB) or a digital video disc player. (7) the compressed digital video signal is received from a first video source, and the uncompressed video signal is received from a second video source;
The method according to the above (1). (8) A method for processing an analog video signal,
A method of digitizing an analog video signal for input to a digital video processing system and mixing the digitized video signal with on-screen display (OSD) graphics in the digital video processing system. (9) The method of (8) above, wherein said digitizing is performed in a digital multi-standard decoder and said digital video processing system comprises an integrated digital video decoding system. (10) The method of (9), further comprising formatting the digitized mixed video signal and OSD graphics for display on an analog television system. (11) implementing the method in at least one of a digital video set top box (STB) or a digital video disc player, wherein the digitized video is displayed for display on an analog television system. (8). The method of (8) above, further comprising formatting the mixed video signal and OSD graphics. (12) A system for forming a multi-screen display for a non-picture-in-picture television system, comprising: decoding a compressed digital video signal from a first video source; A video decoder for generating a video signal; and an input for receiving an uncompressed video signal from a second video source into the video decoder, the video decoder comprising: The video signal and the uncompressed video signal are merged and adapted to generate a multi-screen display signal for the television system, thereby increasing the ability to simultaneously display multiple pictures. A system for providing a picture-in-picture television system. (13) The video decoder is further adapted to downscale the decompressed digital video signal before merging with the uncompressed video signal, and wherein the decompressed and downscaled digital signal is The signal is at least one of the multi-screen displays.
The method according to (12), comprising two screens. (14) the uncompressed video signal includes an uncompressed analog video signal, and the system digitizes the uncompressed analog video signal before inputting to the video decoder; The system according to (13), further comprising a digital multi-standard decoder. (15) The video decoder is configured to output the expanded digital video signal and the uncompressed analog video signal.
The system of claim 12, further adapted to switch between a video signal and create at least some video frames for display by the television system in a picture-in-picture format. . The video decoder is further adapted to mix on-screen display (OSD) graphics with the multi-screen display signal prior to presentation to the television system. System. (17) The above (1), wherein the system includes one of a digital video set top box (STB) or a digital video disc (DVD) player.
The system according to 2). (18) A system for forming a multi-screen display for a non-picture-in-picture television system, comprising means for receiving and decoding a compressed digital video signal to generate a decompressed digital video signal. Means for receiving an uncompressed video signal; and merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system. Means for providing to a non-picture-in-picture television system the ability to simultaneously display a plurality of pictures. (19) A system for processing an analog video signal, comprising: a digital video processing system;
Digital multi-multiplexer for digitizing video signals for input to the digital video processing system
A standard decoder, wherein the digital video processing system is adapted to mix the digitized video signal with on-screen display (OSD) graphics and output as a mixed video signal. System. (20) The digital video processing system includes a video decoder, wherein the video decoder is adapted to perform the mixing of the digitized video signal and the OSD graphics. The system according to (19). (21) The system according to (20), wherein the system includes at least one of a digital video set top box (STB) or a digital video disc (DVD) player. (22) The digital video processing system is adapted to format the digitized mixed video signal and OSD graphics for display on an analog television system. The system according to (19). (23) A system for processing an analog video signal, the means for digitizing the analog video signal for input to a digital video processing system;
Means for mixing the digitized video signal with on-screen display (OSD) graphics in a digital video processing system. (24) An article of manufacture comprising a computer program product, the computer program product including a computer usable medium having computer readable program code means, wherein the computer readable program code means comprises a non-picture Forming a multi-screen display for a picture-in-television system, wherein the computer readable program code means in the computer program product causes a computer to decode and decompress a compressed digital video signal. Computer readable program code means for generating a compressed digital video signal, and a computer readable program means for causing a computer to receive an uncompressed video signal. And code means, computer,
Merging the decompressed digital video signal and the uncompressed video signal to generate a multi-screen display signal for the television system, thereby increasing the ability to display multiple pictures simultaneously. Computer readable program code means for providing to a non-in-picture picture television system. (25) An article of manufacture comprising a computer program product, the computer program product including a computer usable medium having computer readable program code means, wherein the computer readable program code means comprises an analog The computer readable program code means for processing a video signal, wherein the computer readable program code means in the computer program product cause the computer to digitize an analog video signal; and Computer readable program code means for mixing the encoded video signal and on-screen display (OSD) graphics for presentation to a television system. Thing.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a video decode unit.

FIG. 2 illustrates an on-screen display (O) according to the principles of the present invention.
FIG. 2 is a block diagram illustrating a video decoding system that implements picture-in-picture with SD) graphics capabilities.

FIG. 3 is a block diagram illustrating a multi-screen display (ie, a picture-in-picture) implemented in accordance with the principles of the present invention.

FIG. 4 illustrates an integrated video decoding system having a first digital video source and a second analog video source for inputting a video signal for merging within an integrated system in accordance with the present invention. FIG. 2 is a block diagram illustrating one embodiment.

FIG. 5 illustrates one technique for merging decompressed digital video and uncompressed analog video into a multi-screen display, in accordance with the principles of the present invention, by combining the resulting video with on-screen display (OSD) graphics. FIG. 3 is a detailed view shown with the ability to mix.

FIG. 6 illustrates a detailed embodiment of a video decoding system in accordance with the principles of the present invention.

FIG. 7 is a diagram illustrating division of a frame buffer in a normal mode and a video scaling mode according to the present invention;

FIG. 8 illustrates a video scaling scheme according to the principles of the present invention.
FIG. 5 is a timing chart showing delayed display timing in a mode.

FIG. 9 is a diagram illustrating one example of switching between the small frame buffers 2, 4, and 6 of FIG. 7 according to the present invention.

FIG. 10 is a block diagram illustrating one embodiment of a decimation unit in accordance with the principles of the present invention for the video decoding system of FIG.

FIG. 11 is a block diagram illustrating one embodiment of display mode switching logic according to the principles of the present invention for the video decoding system of FIG.

FIG. 12 is a flowchart illustrating one embodiment of a process implemented by the synchronization generator of FIG. 11 in accordance with the principles of the present invention.

[Explanation of symbols]

Reference Signs List 11 signal 12 compressed data memory 13 signal 14 variable length decoder (VLD) 15, 16 signal 17 motion compensation (MC) unit 18 inverse quantization (IQ) unit 19 signal 20 reference frame memory 21, 22 signal 23 inverse transform ( IDCT) unit 24 signal 25 adder 26 signal 27 demultiplexer 28, 29, 30 signal 40 decoding system chip 42 PCI bus 44 PCI bus interface 46 DMA controller 48 video first in first out (FIFO) buffer 50 OSD / audio FIFO 52 memory -Controller 52 53 Dynamic random access memory (D
RAM) 54 Video decoder 58 Display and OSD interface 59 Digital video encoder (DENC) /
Digital to analog converter chip 60 Audio interface 70 Display screen 71 Pixel 72, 74 picture 100 Digital video decode system chip 101 Digital video signal 102 Network interface module (NIM) 103 Transport logic 104 Analog -Video signal 105 Digital multi-standard decoder (DMSD) 106 Video decoder 107 Internal digital video encoder (DEN)
C) Macro 110 Output 202 2: 1 MUX 204 OSD Mixed Logic 652 Memory Control Unit 653 External Memory 654 Video Decoder 670 Internal Processor 672 Huffman Decoder 674 Inverse Quantizer 676 Inverse DCT 678 Motion Compensation Unit 680 Adder 682 Decimation Unit 684 scan line video buffer 686 frame buffer pointer control 690 video display unit 692 display fetch unit 694 upsample logic 696 display mode switching logic 698 display output interface 700 frame buffer 800 decimation logic 810 decimation control signal 820 Decimation buffer 830 Multiplexer 840 Write memory Control 850 multiplexer 900 sync generator 910 display format register 920 field counter 930, 940, 960 register stage

 ──────────────────────────────────────────────────の Continuing on the front page (72) Dennis P. Cheney, USA 13850 Vestal, New York, Country Club Road 4860 (72) Inventor Lawrence D. Curly United States 13760 Endwell, NY Country Club Road 3637 (72) Inventor William Earl Leigh United States 27502 North Carolina, Apex, Teverly Coat 1224 (72) Inventor Leland Dee Richardson United States 27502 North Carolina, Apex, Winding O Rookie 4113 (72) Inventor Ronald Es Sbek United States 13736 Kushea, Route 38 12493

Claims (25)

[Claims] 1. A method for forming a multi-screen display for a non-picture-in-picture television system, comprising: receiving and decoding a compressed digital video signal to generate an expanded digital video signal. Receiving an uncompressed video signal, merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system;
A method for providing the ability to simultaneously display a plurality of pictures to said non-picture-in-picture television system. 2. The method of claim 1, further comprising downscaling the decompressed digital video signal prior to merging with the uncompressed video signal, wherein the decompressed and downscaled digital video signal comprises the multi-screen. The method of claim 1 including at least one screen of a display. 3. The method of claim 2, wherein said uncompressed video signal comprises an uncompressed analog video signal. 4. The merging switches between the decompressed digital video signal and the uncompressed analog video signal to create at least some video frames for display on the television system. The method of claim 1, wherein the switching creates the multi-screen display. 5. The method of claim 1, further comprising: mixing on-screen display (OSD) graphics with at least one of the decompressed digital video signal and the uncompressed video signal; 2. The method of claim 1, including a compressed digital video signal and the uncompressed video signal. 6. A digital video set top box (STB) or digital video disk
The method of claim 1, comprising implementing the method in at least one of the players. 7. The method of claim 1, wherein said compressed digital video signal is received from a first video source and said uncompressed video signal is received from a second video source. 8. A method for processing an analog video signal, the method comprising: digitizing an analog video signal for input to a digital video processing system; And mixing on-screen display (OSD) graphics. 9. The method according to claim 8, wherein the digitization is a digital multi-mode.
9. The method of claim 8, executed in a standard decoder, wherein said digital video processing system comprises an integrated digital video decoding system. 10. The method of claim 9, further comprising formatting said digitized mixed video signal and OSD graphics for display on an analog television system. 11. A digital video set top.
Implementing said method in at least one of a box (STB) or a digital video disc player;
Digitized mixed video signal and OSD for display on an analog television system
9. The method of claim 8, further comprising formatting the graphics. 12. A non-picture-in-picture television.
A system for forming a multi-screen display for a system, comprising: a video decoder for decoding a compressed digital video signal from a first video source to generate an expanded digital video signal; An input for receiving an uncompressed video signal from a second video source into the video decoder, the video decoder providing the decompressed digital video signal and the uncompressed video signal; To provide a multi-screen display signal for the television system, thereby providing the ability to simultaneously display multiple pictures to the non-in-picture picture television system. system. 13. The video decoder is further adapted to downscale the decompressed digital video signal before merging it with the uncompressed video signal, and wherein the decompression and downscaling is performed. The method of claim 12, wherein the digital signal comprises at least one screen of the multi-screen display. 14. The uncompressed video signal comprises an uncompressed analog video signal, and wherein the system outputs the uncompressed analog video signal to a digital signal prior to input to the video decoder. 14. The system of claim 13, further comprising a digital multi-standard decoder for encrypting. 15. The television decoder, wherein the video decoder switches between the expanded digital video signal and the uncompressed analog video signal.
13. The system of claim 12, further adapted to create at least some video frames for display in a picture-in-picture format by the system. 16. The video decoder further adapted to mix on-screen display (OSD) graphics with the multi-screen display signal prior to presenting the video to the television system. 1
3. The system according to 2. 17. The system according to claim 17, wherein said system is a digital video
Set top box (STB) or digital
The system of claim 12, comprising one of a video disk (DVD) player. 18. A non-picture-in-picture television.
A system for forming a multi-screen display for a system, comprising: means for receiving and decoding a compressed digital video signal to generate an expanded digital video signal; and means for receiving an uncompressed video signal. And means for merging the decompressed digital video signal and the uncompressed video signal to generate a single multi-screen display signal for the television system, thereby providing a plurality of pictures. For providing the ability to simultaneously display to a non-picture in-picture television system. 19. A system for processing an analog video signal, comprising: a digital video processing system; and a digital multi-standard system for digitizing the analog video signal for input to the digital video processing system. A digital video processing system, wherein the digital video processing system is adapted to mix the digitized video signal with on-screen display (OSD) graphics and output as a mixed video signal. . 20. The digital video processing system includes a video decoder, wherein the video decoder is adapted to perform the mixing of the digitized video signal and the OSD graphics. 20. The system of claim 19. 21. The system as claimed in claim 21, wherein the digital video
Set top box (STB) or digital
21. The system of claim 20, comprising at least one of a video disk (DVD) player. 22. The digital video processing system comprising:
20. The system of claim 19, wherein the system is adapted to format SD graphics for display on an analog television system. 23. A system for processing an analog video signal, wherein the means for digitizing the analog video signal for input to a digital video processing system; Means for mixing the displayed video signal with on-screen display (OSD) graphics. 24. An article of manufacture comprising a computer program product, said computer program product comprising a computer usable medium having computer readable program code means, said computer readable program code means comprising: Forming a multi-screen display for a non-picture-in-picture television system, the computer readable program code means in the computer program product comprising: a computer for decoding a compressed digital video signal; Computer readable program code means for producing an expanded digital video signal, and computer readable means for causing a computer to receive an uncompressed video signal Program code means and a computer for merging the decompressed digital video signal and the uncompressed video signal to generate a multi-screen display signal for the television system, thereby Computer readable program code means for providing the ability to simultaneously display the same picture to the non-picture-in-picture television system. 25. An article of manufacture comprising a computer program product, said computer program product comprising:
A computer readable medium having computer readable program code means, wherein the computer readable program code means comprises an analog
The computer readable program code means for processing a video signal and within the computer program product comprises a computer readable program code for causing a computer to digitize an analog video signal.
Code means, and the computer mixes the digitized video signal with an on-screen display (OSD) graphic,
Computer readable program code means for presentation to a television system.