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JP2001044499A - ZnO COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE USING SILICON SUBSTRATE AND MANUFACTURING METHOD THEREFOR - Google Patents

ZnO COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE USING SILICON SUBSTRATE AND MANUFACTURING METHOD THEREFOR

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Publication number
JP2001044499A
JP2001044499A JP21122299A JP21122299A JP2001044499A JP 2001044499 A JP2001044499 A JP 2001044499A JP 21122299 A JP21122299 A JP 21122299A JP 21122299 A JP21122299 A JP 21122299A JP 2001044499 A JP2001044499 A JP 2001044499A
Authority
JP
Japan
Prior art keywords
semiconductor
nitride film
silicon nitride
layer
zno
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21122299A
Other languages
Japanese (ja)
Other versions
JP4425376B2 (en
Inventor
Sakae Niki
栄 仁木
Hiroya Iwata
拡也 岩田
Fonsu Paul
ポール・フォンス
Tetsuhiro Tanabe
哲弘 田辺
Hideshi Takasu
秀視 高須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP21122299A priority Critical patent/JP4425376B2/en
Application filed by Agency of Industrial Science and Technology, Rohm Co Ltd filed Critical Agency of Industrial Science and Technology
Priority to TW089114903A priority patent/TW469511B/en
Priority to PCT/JP2000/004998 priority patent/WO2001008229A1/en
Priority to EP07123034A priority patent/EP1912298A1/en
Priority to KR1020027001072A priority patent/KR100694928B1/en
Priority to EP00949916A priority patent/EP1199755A4/en
Priority to US10/031,931 priority patent/US6674098B1/en
Publication of JP2001044499A publication Critical patent/JP2001044499A/en
Priority to US10/713,205 priority patent/US6987029B2/en
Priority to US11/166,254 priority patent/US7605012B2/en
Application granted granted Critical
Publication of JP4425376B2 publication Critical patent/JP4425376B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device and its manufacturing method that use a ZnO-family compound semiconductor, are a vertical type that can take out an electrode from the upper and lower surfaces of a chip, having superior crystallinity of a semiconductor layer and high light emission efficiency, at the same time, which do not use a sapphire substrate, and are convenient in a manufacturing process and use. SOLUTION: A silicon nitride film 2 is provided on the surface of a silicon substrate 1, at least n-type and p-type layers 3 and 4 and 6 and 7 consisting of a ZnO-family compound semiconductor are provided on the silicon nitride film 2, and a semiconductor lamination part 11 is laminated, so that a light emission layer is formed. The silicon nitride film 2 is preferably subjected to heat treatment under atmosphere, where nitrogen as an ammonia gas exists for forming.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はZnO系化合物半導
体を用い、高い記憶密度を有する光ディスクメモリや、
レーザビームプリンタの高精細化に必要な青色領域で発
光可能な半導体レーザや発光ダイオードなどの半導体発
光素子およびその製法に関する。さらに詳しくは、基板
にシリコン基板を用いながら発光特性の優れた半導体層
を積層し、電極をチップの上下両面から取り出せると共
に劈開をすることができる半導体発光素子およびその製
法に関する。
The present invention relates to an optical disk memory using a ZnO-based compound semiconductor and having a high storage density,
The present invention relates to a semiconductor light emitting device such as a semiconductor laser or a light emitting diode capable of emitting light in a blue region required for high definition of a laser beam printer, and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor light-emitting element in which a semiconductor layer having excellent light-emitting characteristics is laminated on a substrate using a silicon substrate, electrodes can be taken out from both upper and lower surfaces of the chip and cleaved, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】フルカラーディスプレーや、信号灯など
の光源に用いられる青色系(紫外から黄色の波長領域を
意味する、以下同じ)の発光ダイオード(以下、LED
という)や、室温で連続発振する次世代の高精細DVD
光源用などの青色系半導体レーザ(以下、LDという)
は、最近サファイア基板上にGaN系化合物半導体を積
層することにより得られるようになり脚光を浴びてい
る。
2. Description of the Related Art A blue light-emitting diode (hereinafter, referred to as an LED from ultraviolet to yellow wavelength region) used for a light source such as a full-color display and a signal light (hereinafter, referred to as an LED).
) And next-generation high-definition DVDs that oscillate continuously at room temperature
Blue semiconductor lasers for light sources (hereinafter referred to as LD)
Has recently been spotlighted by being obtained by laminating a GaN-based compound semiconductor on a sapphire substrate.

【0003】この構造は、図6にLDチップの斜視説明
図が示されるように、サファイア基板21上にIII 族チ
ッ化物化合物半導体が有機金属化学気相成長法(Metal
Organic Chemical Vapor Deposition 以下、MOCV
Dという)により順次積層されるもので、GaN緩衝層
22、n形GaN層23、Al0.12Ga0.88Nからなる
n形クラッド層24、GaNからなるn形光ガイド層2
5、InGaN系化合物半導体の多重量子井戸構造から
なる活性層26、p形GaNからなるp形光ガイド層2
7、p形Al0.2 Ga0.8 Nからなるp形第1クラッド
層28a、Al 0.12Ga0.88Nからなるp形第2クラッ
ド層28b、p形GaNからなるコンタクト層29が順
次積層され、積層された半導体層の一部が図6に示され
るようにドライエッチングなどによりエッチングされて
n形GaN層23を露出させ、その表面にn側電極3
1、前述のコンタクト層29上にp側電極30がそれぞ
れ形成されることにより構成されている。
FIG. 6 shows a perspective view of an LD chip.
As shown in the figure, a group III chip is placed on a sapphire substrate 21.
Metal oxide chemical vapor deposition (Metal)
Organic Chemical Vapor Deposition, MOCV
D) and a GaN buffer layer
22, n-type GaN layer 23, Al0.12Ga0.88Consisting of N
n-type cladding layer 24, n-type light guide layer 2 made of GaN
5. From the multiple quantum well structure of InGaN-based compound semiconductor
Active layer 26, p-type light guide layer 2 made of p-type GaN
7, p-type Al0.2Ga0.8P-type first cladding made of N
Layer 28a, Al 0.12Ga0.88N-type p-type second crack
Layer 28b and a contact layer 29 made of p-type GaN.
Next, a part of the stacked semiconductor layers is shown in FIG.
Etched by dry etching etc.
The n-type GaN layer 23 is exposed and an n-side electrode 3
1. A p-side electrode 30 is provided on the contact layer 29 described above.
It is constituted by being formed.

【0004】一方、ZnO系化合物半導体もワイドギャ
ップエネルギー半導体で、Cdを混晶させることにより
バンドギャップエネルギーのナロー化がなされ、同様に
青色系の発光をさせ得るため、種々の研究がなされ始め
ている。そして、このZnO系化合物半導体もGaN系
化合物半導体やサファイアと同様にヘキサゴナル(hexa
gonal)結晶であり、格子定数もこれらと近いため、Ga
N系化合物半導体のエピタキシャル成長用基板として工
業的に広く用いられているサファイアが、基板として考
えられている。このサファイア基板上へのZnO系化合
物半導体の成長は、たとえば「ルーム−テンパラチャー
ウルトラバイオレット レーザ エミッション フロ
ム セルフアッセンブルド ZnO マイクロクリスタ
ライトシン フィルムズ(Room-temperature ultraviol
et laser emission from self-assembled ZnO microcry
stallite thin films)」(アプライドフィジックスレタ
ー(Applied Physics Letters)第72巻25号、19
98年6月22日号、3270〜3272頁)にも記載
されている。
On the other hand, ZnO-based compound semiconductors are also wide-gap energy semiconductors, and various studies have begun to be carried out because the band gap energy can be narrowed by mixing crystals of Cd and blue light can be emitted similarly. . This ZnO-based compound semiconductor is also hexagonal (hexagonal) similarly to the GaN-based compound semiconductor and sapphire.
gonal) crystal and the lattice constant is close to these,
Sapphire, which is widely used industrially as a substrate for epitaxial growth of an N-based compound semiconductor, is considered as a substrate. The growth of the ZnO-based compound semiconductor on the sapphire substrate is described, for example, in "Room-temperature ultra violet laser emission from self-assembled ZnO microcrystallite thin films (Room-temperature ultraviol
et laser emission from self-assembled ZnO microcry
stallite thin films) "(Applied Physics Letters, Vol. 72, No. 25, 19)
(June 22, 1998, p. 3270-3272).

【0005】[0005]

【発明が解決しようとする課題】前述のように、従来の
青色系の半導体発光素子では、基板としてサファイア基
板が用いられているため、基板に導電性がなく、積層体
の上面と下面に電極が形成される垂直型の素子(チップ
の表面と裏面に電極が形成された構造を意味する、以下
同じ)を構成できない。そのため、両方の電極を、積層
した半導体層の表面とその一部をエッチングして露出さ
せた下層の半導体層に設けなければならず、製造工程が
複雑であると共に、チップのボンディングも複雑になる
という問題がある。しかも、サファイア基板は非常に硬
いため、劈開をすることが困難であり、半導体レーザの
光共振器の鏡面として必要な平坦な端面を形成できない
という問題がある。すなわち、サファイア基板は、良好
な単結晶半導体層が得られるのと引き換えに、製造プロ
セス上で素子製作の際に、加工性や電極形成に難点があ
ることを強いられている。
As described above, in a conventional blue semiconductor light emitting device, since a sapphire substrate is used as a substrate, the substrate has no conductivity and electrodes are provided on the upper and lower surfaces of the laminate. (Which means a structure in which electrodes are formed on the front and back surfaces of a chip, the same applies hereinafter) cannot be formed. Therefore, both electrodes must be provided on the surface of the laminated semiconductor layer and the lower semiconductor layer in which a part of the surface is etched and exposed, which complicates the manufacturing process and the chip bonding. There is a problem. Moreover, since the sapphire substrate is very hard, it is difficult to cleave the sapphire substrate, and there is a problem that a flat end face required as a mirror surface of an optical resonator of a semiconductor laser cannot be formed. In other words, the sapphire substrate is forced to have difficulties in workability and electrode formation when manufacturing an element in a manufacturing process in exchange for obtaining a good single crystal semiconductor layer.

【0006】本発明はこのよな問題を解決するためにな
されたもので、ZnO系化合物半導体を用い、チップの
表裏両面から電極を取り出すことができる垂直型で、か
つ、半導体層の結晶性が優れて発光効率が高いと共に、
基板にサファイア基板を用いないで製造プロセスおよび
使用面で便利な構造となる半導体発光素子およびその製
法を提供することを目的とする。
The present invention has been made to solve such a problem, and it is a vertical type using a ZnO-based compound semiconductor, from which electrodes can be taken out from both front and back surfaces of a chip, and having a semiconductor layer having good crystallinity. With excellent luminous efficiency,
It is an object of the present invention to provide a semiconductor light emitting device having a convenient structure in terms of a manufacturing process and use without using a sapphire substrate as a substrate, and a method for manufacturing the same.

【0007】本発明の他の目的は、シリコン基板上にZ
nO系化合物半導体を結晶性よく成長するためにとくに
適したシリコン基板の表面処理を含む半導体発光素子の
製法を提供することにある。
Another object of the present invention is to provide a Z
An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device including a surface treatment of a silicon substrate which is particularly suitable for growing an nO-based compound semiconductor with good crystallinity.

【0008】[0008]

【課題を解決するための手段】本発明者らは、前述のよ
うにサファイア基板上にZnO系化合物半導体を成長す
ることの不便さを解消するため、大口径で取り扱いやす
いシリコン基板を用いてZnO系化合物半導体を成長す
べく鋭意検討を重ねた。その結果、シリコン基板上に直
接ZnO系化合物半導体を成長しようとしても、ZnO
系化合物がアモルファス化してしまって結晶性のよい半
導体層を得ることができない理由が、ZnO系化合物を
成長するために導入するラジカル酸素により、ZnO系
化合物半導体が成長する前に、まずシリコン基板の表面
が強烈に酸化されてアモルファス化することにあり、シ
リコン基板の表面にチッ化処理を施して薄いチッ化膜を
形成しておくことにより、シリコン基板表面の酸化が防
止されて、結晶性の優れたZnO系化合物半導体層を成
長することができ、発光特性の優れた半導体発光素子が
得られることを見出した。
In order to eliminate the inconvenience of growing a ZnO-based compound semiconductor on a sapphire substrate as described above, the present inventors used a large-diameter silicon substrate which is easy to handle. Intensive investigations were made to grow a compound semiconductor. As a result, even if a ZnO-based compound semiconductor is to be grown directly on a silicon
The reason that the system compound becomes amorphous and a semiconductor layer with good crystallinity cannot be obtained is that radical oxygen introduced for growing the ZnO compound causes the silicon substrate to grow first before the ZnO compound semiconductor grows. The surface is intensely oxidized and becomes amorphous. By applying a silicon nitride treatment to the surface of the silicon substrate to form a thin nitride film, the oxidation of the silicon substrate surface is prevented and the crystallinity is reduced. It has been found that an excellent ZnO-based compound semiconductor layer can be grown, and a semiconductor light-emitting element having excellent light-emitting characteristics can be obtained.

【0009】本発明による半導体発光素子は、シリコン
基板と、該シリコン基板の表面に設けられるシリコンチ
ッ化膜と、該シリコンチッ化膜上に設けられ、ZnO系
化合物半導体からなるn形層およびp形層を少なくとも
有し、発光層を形成すべく積層される半導体積層部とを
含んでいる。
A semiconductor light emitting device according to the present invention comprises a silicon substrate, a silicon nitride film provided on a surface of the silicon substrate, an n-type layer made of a ZnO-based compound semiconductor, and a p-type layer provided on the silicon nitride film. A semiconductor laminated portion having at least a shape layer and laminated to form a light emitting layer.

【0010】ここにZnO系化合物半導体とは、Znを
含む酸化物、具体例としてはZnOの他IIA族元素とZ
nまたはIIB族元素とZnまたはIIA族元素およびIIB
族元素とZnのそれぞれの酸化物であることを意味す
る。
[0010] Here, the ZnO-based compound semiconductor is an oxide containing Zn, specifically, a group IIA element in addition to ZnO and ZZ.
Group n or IIB element and Zn or Group IIA element and IIB
It means that it is an oxide of each of a group III element and Zn.

【0011】この構造にすることにより、シリコン基板
の表面にシリコンチッ化膜が形成されているため、Zn
O系化合物半導体層を成長するためのラジカル酸素が導
入されても、シリコン基板の表面が酸化して荒らされる
ことがなく、その表面に成長するZnO系化合物半導体
層も結晶性よく成長する。その結果、結晶性のよい半導
体積層部が得られ、優れた発光特性を有する半導体発光
素子が得られる。
According to this structure, since a silicon nitride film is formed on the surface of the silicon substrate, Zn
Even if radical oxygen for growing the O-based compound semiconductor layer is introduced, the surface of the silicon substrate is not oxidized and roughened, and the ZnO-based compound semiconductor layer grown on the surface also grows with good crystallinity. As a result, a semiconductor laminated portion having good crystallinity is obtained, and a semiconductor light emitting device having excellent light emitting characteristics is obtained.

【0012】前記シリコンチッ化膜の表面がアモルファ
ス化しないで平坦面に形成されていることが、その上に
成長されるZnO系化合物半導体層の結晶性が一層良好
になるため好ましい。
It is preferable that the surface of the silicon nitride film is formed on a flat surface without being made amorphous, since the crystallinity of the ZnO-based compound semiconductor layer grown thereon is further improved.

【0013】ここにシリコンチッ化膜の表面が平坦面に
形成されるとは、表面がアモルファス化して凹凸が激し
くならないで、格子配列が認識し得る程度の表面状態を
いい、たとえば反射高エネルギー電子回折法(RHEE
D法;10〜50kVで加速された電子ビームを基板表
面に浅い角度(1〜2゜以下)で入射させ、表面原子に
よって反射回折された電子ビームを蛍光スクリーンに投
影して結晶の表面状態を調べる方法)により、ストリー
クの状態から点状(spotty)の像が現れる程度の状態を
意味する。
Here, "the surface of the silicon nitride film is formed as a flat surface" refers to a surface state in which the lattice arrangement can be recognized without the surface becoming amorphous and unevenness becoming severe. Diffraction method (RHEE
Method D: An electron beam accelerated at 10 to 50 kV is incident on the substrate surface at a shallow angle (1 to 2 ° or less), and the electron beam reflected and diffracted by the surface atoms is projected on a fluorescent screen to change the surface state of the crystal. (Investigation method) means a state in which a spotty image appears from the streak state.

【0014】前記シリコンチッ化膜が、100Å以下の
厚さに形成されていることが、シリコンチッ化膜の表面
が多結晶化しないで、平坦な面になりやすいため好まし
い。
It is preferable that the silicon nitride film is formed to a thickness of 100 ° or less because the surface of the silicon nitride film tends to be flat without being polycrystallized.

【0015】前記半導体積層部が、Cdx Zn1-x
(0≦x<1)からなる活性層を、Mgy Zn1-y
(0≦y<1)からなり前記活性層よりバンドギャップ
エナルギーの大きいクラッド層により挟持するダブルヘ
テロ構造を有することにより、ZnO系化合物半導体を
用い、発光特性の優れたLEDやLDが得られるため好
ましい。
[0015] The semiconductor lamination portion is made of Cd x Zn 1-x O
The active layer composed of (0 ≦ x <1) is formed of Mg y Zn 1-y O
(0 ≦ y <1), which has a double hetero structure sandwiched by cladding layers having a bandgap energy larger than that of the active layer, so that an LED or LD using a ZnO-based compound semiconductor and having excellent emission characteristics can be obtained. preferable.

【0016】本発明の半導体発光素子の製法は、シリコ
ン基板をチッ素が存在する雰囲気下で熱処理することに
よりシリコン基板の表面にシリコンチッ化膜を形成し、
該シリコンチッ化膜上にZnO系化合物半導体からなり
発光層を形成する半導体積層部を成長することを特徴と
する。
According to a method of manufacturing a semiconductor light emitting device of the present invention, a silicon nitride film is formed on a surface of a silicon substrate by heat-treating the silicon substrate in an atmosphere in which nitrogen is present.
A semiconductor laminated portion made of a ZnO-based compound semiconductor and forming a light emitting layer is grown on the silicon nitride film.

【0017】この方法を用いることにより、シリコン基
板の表面に酸化を防止するチッ化膜が形成されながら、
表面が多結晶化しないで、シリコン基板の結晶面を維持
することができ、その表面に結晶性の優れたZnO系化
合物半導体を成長することができると共に、シリコンチ
ッ化膜が非常に薄く形成され、シリコン基板と半導体積
層部との間の導電性が分断されない。
By using this method, a nitrided film for preventing oxidation is formed on the surface of the silicon substrate.
The crystal plane of the silicon substrate can be maintained without polycrystallizing the surface, a ZnO-based compound semiconductor having excellent crystallinity can be grown on the surface, and the silicon nitride film can be formed very thin. In addition, the conductivity between the silicon substrate and the semiconductor laminated portion is not divided.

【0018】前記シリコンチッ化膜を形成する処理を、
形成されるシリコンチッ化膜の表面がシリコン基板の平
坦面を維持できるように該処理の温度または時間を制御
しながら行うことが、多結晶化を防止することができて
好ましい。すなわち、たとえば650℃でチッ化処理を
行う場合、5〜10分程度、さらに好ましくは7分程度
でチッ化処理を行うと優れた結晶性のZnO系化合物半
導体層が得られるが、15分程度行うと表面が多結晶化
し、その上に成長されるZnO系化合物半導体も多結晶
化して結晶性のよいZnO系化合物半導体層が得られな
い。また、800℃でチッ化処理を行う場合、3分程度
の処理時間でも、優れた結晶性のZnO系化合物半導体
層が得られ、逆にチッ化処理の温度を低くすると、処理
時間を長くするほうが好ましい。これらの条件は、たと
えば前述のRHEED法によりシリコンチッ化膜の表面
状態を検査することにより、シリコンチッ化膜の表面が
平坦面になるように、条件設定をすることができる。
The process for forming the silicon nitride film is as follows:
It is preferable to perform the treatment while controlling the temperature or time so that the surface of the formed silicon nitride film can maintain the flat surface of the silicon substrate because polycrystallization can be prevented. That is, for example, in the case of performing the nitriding treatment at 650 ° C., when performing the nitriding treatment in about 5 to 10 minutes, and more preferably in about 7 minutes, a ZnO-based compound semiconductor layer having excellent crystallinity can be obtained. Then, the surface is polycrystallized, and the ZnO-based compound semiconductor grown thereon is also polycrystallized, so that a ZnO-based compound semiconductor layer having good crystallinity cannot be obtained. In addition, in the case of performing the nitriding treatment at 800 ° C., even with a treatment time of about 3 minutes, a ZnO-based compound semiconductor layer having excellent crystallinity can be obtained. Conversely, when the temperature of the nitriding treatment is lowered, the treatment time is lengthened. More preferred. These conditions can be set so that the surface of the silicon nitride film becomes flat by inspecting the surface state of the silicon nitride film by, for example, the above-mentioned RHEED method.

【0019】[0019]

【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体発光素子およびその製法について説明をす
る。
Next, a semiconductor light emitting device of the present invention and a method of manufacturing the same will be described with reference to the drawings.

【0020】本発明の半導体発光素子は、図1にその一
実施形態であるLEDチップの斜視説明図が示されるよ
うに、シリコン基板1の表面にシリコンチッ化膜2が設
けられており、そのシリコンチッ化膜2上にZnO系化
合物半導体からなるn形層3、4およびp形層6、7を
少なくとも有し、発光層を形成するように半導体積層部
11が積層されている。
FIG. 1 is a perspective view of an LED chip according to an embodiment of the present invention. As shown in FIG. 1, a silicon nitride film 2 is provided on the surface of a silicon substrate 1. On the silicon nitride film 2, at least n-type layers 3, 4 and p-type layers 6, 7 made of a ZnO-based compound semiconductor are provided, and a semiconductor laminated portion 11 is laminated so as to form a light emitting layer.

【0021】前述のように、本発明者らは、シリコン基
板上にZnO系化合物半導体を結晶性よく成長するため
に鋭意検討を重ねた結果、シリコン基板上に直接ZnO
系化合物半導体を成長しようとすると、ZnO系化合物
半導体の材料であるラジカル酸素が、最初にシリコンと
激しく反応して、表面がアモルファス状になり凹凸が形
成され、それが原因で結晶性のよいZnO系化合物半導
体層が得られないことを見出した。そして、シリコン基
板の表面をまずチッ化処理して、基板表面のダングリン
グボンドのSiとNとを化合させ、シリコンチッ化膜を
表面に薄く形成することにより、結晶性の優れたZnO
系化合物半導体をその上に成長することができることを
見出した。このシリコンチッ化膜は、チッ素ガスまたは
アンモニアガスなどのチッ素が存在する雰囲気下で熱処
理をし、シリコン基板の表面にチッ化膜を形成すること
により好ましい結果が得られたが、チッ化処理をし過ぎ
るとかえってその上のZnO系化合物半導体が多結晶化
して結晶性の優れたZnO系化合物半導体を得ることが
できなかった。
As described above, the present inventors have made intensive studies to grow a ZnO-based compound semiconductor on a silicon substrate with good crystallinity, and as a result, have found that
When an attempt is made to grow a compound semiconductor, radical oxygen, which is a material of the ZnO compound semiconductor, first reacts violently with silicon, and the surface becomes amorphous and irregularities are formed. It has been found that a base compound semiconductor layer cannot be obtained. Then, the surface of the silicon substrate is first subjected to a nitriding treatment, Si and N of dangling bonds on the surface of the substrate are combined, and a thin silicon nitride film is formed on the surface.
It has been found that a compound semiconductor can be grown thereon. This silicon nitride film was heat-treated in an atmosphere in which nitrogen such as nitrogen gas or ammonia gas is present, and a preferable result was obtained by forming a nitride film on the surface of the silicon substrate. If the treatment is excessively performed, the ZnO-based compound semiconductor thereon is rather polycrystallized, and a ZnO-based compound semiconductor having excellent crystallinity cannot be obtained.

【0022】すなわち、シリコン基板1を洗浄処理して
MBE(Molecular Beam Epitaxy;分子線エピタキシ
ー)結晶成長装置に入れ、たとえばNH3 ガスをRF電
源にてプラズマ励起した状態で、MBE結晶成長装置に
導入し、シリコンチッ化膜2を形成する処理温度と処理
時間を種々変化させたときの、その上に成長されるZn
O系化合物半導体層の膜質の状態を調べた。その検査結
果が表1に示されるように、650℃の熱処理を7分間
行うと非常に膜質がよく(二重丸)、5分から10分行
った場合は、良好なZnO系化合物半導体層の膜質が得
られる(白丸)が、同じ温度で15分間熱処理を行うと
ZnO系化合物半導体層がアモルファス化して好ましく
なかった(×印)。また、800℃で3分間のチッ化処
理を行った結果、同様にZnO系化合物半導体層の良好
な膜質が得られた。この関係を図2に示すと、良好な膜
質が得られる範囲としては、当然低い温度では処理速度
が遅いため、長い処理時間で同様の膜質が得られ、図2
の実線で囲まれる範囲Aの条件で処理を行うことによ
り、良好な膜質のシリコンチッ化膜が得られ、その上に
成長されるZnO系化合物半導体層も良好な膜質が得ら
れることが想定される。
That is, the silicon substrate 1 is subjected to a cleaning treatment and put into an MBE (Molecular Beam Epitaxy) crystal growth apparatus. For example, NH 3 gas is introduced into the MBE crystal growth apparatus in a state of being plasma-excited by an RF power supply. Then, when the processing temperature and the processing time for forming the silicon nitride film 2 are variously changed, the Zn grown thereon is changed.
The state of the film quality of the O-based compound semiconductor layer was examined. As shown in Table 1, the heat treatment at 650 ° C. for 7 minutes gives a very good film quality (double circle), and the heat treatment at 650 ° C. for 5 to 10 minutes gives a good film quality of the ZnO-based compound semiconductor layer. Was obtained (white circles), but heat treatment at the same temperature for 15 minutes was not preferable because the ZnO-based compound semiconductor layer became amorphous (x mark). In addition, as a result of performing the nitriding treatment at 800 ° C. for 3 minutes, similarly, good film quality of the ZnO-based compound semiconductor layer was obtained. FIG. 2 shows this relationship. As a range in which good film quality can be obtained, the processing speed is naturally low at a low temperature, and thus the same film quality can be obtained over a long processing time.
It is assumed that by performing the treatment under the condition of the range A surrounded by the solid line, a silicon nitride film having good film quality can be obtained, and also a ZnO-based compound semiconductor layer grown thereon can have good film quality. You.

【0023】[0023]

【表1】 この膜質の検査は、図3(a)に示されるように、一般
にMBE装置に装備されている反射高エネルギー電子回
折法(RHEED法)と呼ばれる方法、すなわち電子銃
51により10〜50kVで加速された電子ビーム52
を基板53表面に浅い角度(1〜2゜以下)θで入射さ
せ、表面原子によって反射回折された電子ビーム54を
蛍光スクリーン55に投影して結晶の表面状態を調べる
方法を用い、電子の加速電圧を20Vで行った。この方
法により行うことにより、電子ビームの入射、反射、回
折ビームの計測が浅い角度で行われるため、ほぼ基板5
3に垂直な方向から行われる分子線の供給に影響を与え
ないで、成膜しながら測定することができる。
[Table 1] As shown in FIG. 3A, the inspection of the film quality is accelerated at 10 to 50 kV by an electron gun 51, that is, a method generally called a reflection high energy electron diffraction method (RHEED method) provided in the MBE apparatus. Electron beam 52
Is incident on the surface of the substrate 53 at a shallow angle (1 to 2 ° or less) θ, and the electron beam 54 reflected and diffracted by the surface atoms is projected on the fluorescent screen 55 to examine the surface state of the crystal. The voltage was set at 20V. By performing this method, the incidence, reflection, and diffraction beam measurement of the electron beam are performed at a shallow angle.
The measurement can be performed while the film is formed without affecting the supply of the molecular beam performed from the direction perpendicular to the direction of 3.

【0024】この回折像としては、基板表面が結晶構造
であると直線または帯状の明暗(ストリーク状の像)が
現れるが、基板表面に凹凸が現れてアイランドが形成さ
れると、これらのアイランドを透過回折した電子ビーム
の寄与が大きくなり、ストリーク状の像は消失して点状
(spotty)の像が現れる。さらに表面が多結晶体になる
と、スポットが消失してリング状の回折像が得られる。
これは微結晶の方位がランダムに分布していることによ
って生じる。さらに表面がアモルファスになると、原子
配列の周期性がなくなり、したがって回折条件は満たさ
れなくなり、RHEED線は一様な強度の帯状(ハロ
ー)になる。したがって、この測定によりシリコンチッ
化膜2の表面状態を観察しながら、その上に成長される
ZnO系化合物半導体の膜質を同様に調べることによ
り、両者の間の相関性が得られる。
As the diffraction image, if the substrate surface has a crystal structure, a straight or band-like light and dark (streak-like image) appears, but if the substrate surface has irregularities and islands are formed, these islands are formed. The contribution of the transmitted and diffracted electron beam increases, so that the streak-like image disappears and a spotty image appears. Further, when the surface becomes polycrystalline, the spot disappears and a ring-shaped diffraction image is obtained.
This is caused by the random distribution of crystallite orientations. Further, when the surface becomes amorphous, the periodicity of the atomic arrangement is lost, so that the diffraction condition is not satisfied, and the RHEED line becomes a band (halo) of uniform intensity. Therefore, by observing the surface state of the silicon nitride film 2 by this measurement and similarly examining the film quality of the ZnO-based compound semiconductor grown thereon, a correlation between the two can be obtained.

【0025】この表面状態の測定を行いながら、シリコ
ン基板1の表面のチッ化処理をまず行うと、最初はシリ
コン基板の表面に酸化膜が形成されているため、表面の
平坦性はなく、図3(c)に示されるようなリング状の
回折像が得られる。この状態で、前述のNH3 ガスをR
F電源にてプラズマ励起した状態でMBE装置のチャン
バー内に導入し、ホルダー(基板)を650℃程度に昇
温すると、シリコン基板1の表面の酸化した酸素が還元
されて除去され、表面状態は図3(b)に示されるよう
に、点状の像が現れる。この状態で保持すると、表面の
酸素が除去されてダングリングボンドになったSiとN
とが化合してシリコンチッ化物が形成され、チッ化処理
が続くが、100Å程度以下のチッ化膜2の厚さでは、
回折像は前述の点状の像が維持される。しかし、10分
より長くチッ化処理を続けると、点状の像がぼやけ、1
5分程度行うと、再度図3(c)に示されるようなリン
グ状の像になる。
When the surface of the silicon substrate 1 is first subjected to a nitrification treatment while measuring the surface state, an oxide film is first formed on the surface of the silicon substrate. A ring-shaped diffraction image as shown in FIG. 3 (c) is obtained. In this state, the aforementioned NH 3 gas is
When the holder (substrate) is heated to about 650 ° C. while being introduced into the chamber of the MBE apparatus under plasma excitation with the F power supply, oxidized oxygen on the surface of the silicon substrate 1 is reduced and removed, and the surface state becomes As shown in FIG. 3B, a point image appears. When held in this state, the surface oxygen is removed to form dangling bonds between Si and N.
Are combined to form silicon nitride, and the nitriding process continues, but with a thickness of the nitrided film 2 of about 100 ° or less,
The above-mentioned point-like image is maintained as the diffraction image. However, if the nitriding process is continued for more than 10 minutes, the dot image becomes blurred.
After about 5 minutes, a ring-shaped image is again formed as shown in FIG.

【0026】すなわち、前述の良好な膜質が得られるの
は、図3(b)に示されるようなスポット状の回折像が
得られる状態からやや点状の像がぼやける状態の平坦性
のチッ化膜の状態にZnO系化合物半導体が成長される
場合で、図3(c)に示されるようなリング状の回折像
になると、チッ化処理のし過ぎで、表面状態の凸凹が顕
著となり、その状態では、その上に成長されるZnO系
化合物半導体の結晶性が低下する。従って、表面がアモ
ルファス化して凹凸が激しくならないように、平坦性を
維持するチッ化処理を行うことにより、良好なZnO系
化合物半導体の膜質が得られる。
That is, the above-mentioned good film quality is obtained only when the spot-like diffraction image as shown in FIG. 3B is obtained and the dot-like image is slightly blurred. In the case where a ZnO-based compound semiconductor is grown in the state of a film, when a ring-like diffraction image as shown in FIG. 3C is obtained, the surface state becomes significantly uneven due to excessive nitriding treatment. In this state, the crystallinity of the ZnO-based compound semiconductor grown thereon decreases. Therefore, good film quality of the ZnO-based compound semiconductor can be obtained by performing a nitriding treatment for maintaining flatness so that the surface is not amorphous and unevenness is not increased.

【0027】シリコン基板1は、通常のICなどに用い
られる、たとえばリン(P)ドープのn形シリコン基板
(111)を用いることができる。しかし、ボロン
(B)などをドープしたp形基板や面方位が(100)
のものでもよい。このシリコン基板1は、予め、アセト
ン、メタノールおよび純粋による超音波洗浄などの有機
洗浄と、希釈フッ酸による表面酸化膜のライトエッチン
グからなる基板洗浄が行われる。
As the silicon substrate 1, for example, an n-type phosphorus (P) -doped silicon substrate (111) used for an ordinary IC or the like can be used. However, a p-type substrate doped with boron (B) or the like or having a plane orientation of (100)
It may be. The silicon substrate 1 is previously subjected to organic cleaning such as ultrasonic cleaning with acetone, methanol and pure, and substrate cleaning including light etching of a surface oxide film with diluted hydrofluoric acid.

【0028】シリコンチッ化膜2は、前述のように、チ
ッ素が存在する雰囲気下で熱処理をすることにより形成
することが、シリコン基板1の表面が多結晶やアモルフ
ァス状態にならない状態で形成しやすいため好ましい。
このチッ化処理は、前述のようにMBE装置である必要
はないが、その表面状態を観察しながら処理を行う場合
は、MBE装置であれば、前述のようにRHEED法に
より観察をしながら処理をすることができるため好まし
い。また、チッ素が存在する雰囲気にするのに、前述の
例では、アンモニアガスをプラズマ励起して使用した
が、N2 ガスをプラズマ励起することもでき、またNO
2 を使用することもできる。このシリコンチッ化膜2
は、前述のように多結晶状態にならず、平坦面が得られ
る状態になるように処理される。すなわち、厚さで10
0Å以下、さらに好ましくは50Å以下の厚さになるよ
うに形成される。そのための条件は、処理温度と処理時
間で調整され、温度が高ければ短時間で、低い温度であ
れば比較的長い時間の処理により得られる。
As described above, the silicon nitride film 2 can be formed by performing heat treatment in an atmosphere in which nitrogen is present, so that the surface of the silicon substrate 1 does not become polycrystalline or amorphous. It is preferable because it is easy.
This nitriding treatment does not need to be performed by the MBE apparatus as described above. However, when the processing is performed while observing the surface state, if the MBE apparatus is used, the processing is performed while observing by the RHEED method as described above. This is preferred because In addition, in the above-described example, the ammonia gas is used with plasma excitation to use an atmosphere in which nitrogen is present. However, N 2 gas can be plasma-excited, and NO gas can be used.
2 can also be used. This silicon nitride film 2
Is processed so as not to be in a polycrystalline state as described above, but to be in a state where a flat surface can be obtained. That is, 10
It is formed so as to have a thickness of 0 ° or less, more preferably 50 ° or less. The conditions for this are adjusted by the processing temperature and the processing time. The higher the temperature, the shorter the time, and the lower the temperature, the longer the processing.

【0029】半導体積層部11は、図1に示される例で
は、Gaをドープしたn形ZnOからなるコンタクト層
3が1μm程度、同じくGaをドープしたMgy Zn
1-y O(0≦y<1、たとえばy=0.15)からなる
n形クラッド層4が0.2μm程度、Cdx Zn1-x
(0≦x<1、かつクラッド層よりバンドギャップエネ
ルギーが小さくなる組成、たとえばx=0.08)から
なる活性層5が0.1μm程度、GaおよびNを同時ド
ープしたMgy Zn1-y O(0≦y<1、たとえばy=
0.15)からなるp形クラッド層6が0.2μm程度、
GaおよびNを同時ドープしたZnOからなるp形コン
タクト層7が1μm程度、それぞれ積層されることによ
り、ダブルヘテロ構造の発光層形成部を有する半導体積
層部11になっている。これらの半導体層は、前述のM
BE装置でチッ化処理に引き続き成長される。なお、活
性層5は、非発光再結合中心の形成を避けるため、ノン
ドープであることが好ましい。また、n形およびp形ク
ラッド層4、6は、活性層5よりバンドギャップが大き
く、キャリアを活性層5内に有効に閉じ込める効果を有
するように形成されている。
In the example shown in FIG. 1, the semiconductor lamination portion 11 has a contact layer 3 made of Ga-doped n-type ZnO of about 1 μm, and a Mg y Zn
The n-type cladding layer 4 made of 1-y O (0 ≦ y <1, for example, y = 0.15) is about 0.2 μm, and Cd x Zn 1-x O
(0 ≦ x <1, and a composition in which the band gap energy is smaller than that of the cladding layer, for example, x = 0.08) is about 0.1 μm, and Mg y Zn 1-y doped with Ga and N simultaneously. O (0 ≦ y <1, for example, y =
0.15) is about 0.2 μm,
A p-type contact layer 7 made of ZnO doped with Ga and N at the same time is laminated to a thickness of about 1 μm to form a semiconductor laminated portion 11 having a light emitting layer forming portion having a double hetero structure. These semiconductor layers correspond to the aforementioned M
It is grown in the BE apparatus following the nitriding treatment. The active layer 5 is preferably non-doped in order to avoid formation of non-radiative recombination centers. The n-type and p-type cladding layers 4 and 6 are formed so as to have a band gap larger than that of the active layer 5 and have an effect of effectively confining carriers in the active layer 5.

【0030】半導体積層部11上には、電流を拡散させ
るための、たとえばITO膜からなる透明電極8が0.
2μm程度成膜されており、その表面の一部にNi/A
lまたはNi/Auなどの積層体からなるp側電極10
がリフトオフ法などにより、また、シリコン基板1の裏
面には、Ti/AlまたはTi/Auなどの積層体から
なるn側電極9が真空蒸着などにより全面に形成されて
いる。
On the semiconductor laminated portion 11, a transparent electrode 8 made of, for example, an ITO film for diffusing a current is set to 0.1 mm.
A film of about 2 μm is formed, and Ni / A
1 or a p-side electrode 10 made of a laminate such as Ni / Au
An n-side electrode 9 made of a laminate of Ti / Al or Ti / Au is formed on the entire back surface of the silicon substrate 1 by a vacuum deposition method or the like.

【0031】つぎに、このLEDの製法について説明を
する。たとえばMBE装置内にシリコン基板1をセッテ
ィングし、基板1の温度を650℃程度にし、NH3
スを流量0.6sccmで導入し、出力300W程度の
高周波電源にてプラズマ励起した状態でチャンバー内に
導入する。この程度の流量にすることが、プラズマ励起
光が強く得られるため好ましい。そして、7分程度チッ
化処理を行う。
Next, a method of manufacturing the LED will be described. For example, the silicon substrate 1 is set in the MBE apparatus, the temperature of the substrate 1 is set to about 650 ° C., NH 3 gas is introduced at a flow rate of 0.6 sccm, and the plasma is excited by a high frequency power supply of about 300 W into the chamber. Introduce. It is preferable to set the flow rate to this level because the plasma excitation light can be strongly obtained. Then, a nitrification process is performed for about 7 minutes.

【0032】つぎに、基板1の温度を300〜450℃
程度にし、プラズマ酸素の照射条件下において、Znの
ソース源(セル)のシャッターを開け、Znを照射する
と共に、n形ドーパントのGaのシャッターも開けてn
形のZnOからなるn形コンタクト層3を1μm程度成
長させる。ついで、さらにMgのソース源(セル)のシ
ャッターも開け、Mg0.15Zn0.85Oからなるn形クラ
ッド層4を0.2μm程度成長する。
Next, the temperature of the substrate 1 is set to 300 to 450 ° C.
Under the conditions of plasma oxygen irradiation, the Zn source source (cell) shutter is opened to irradiate Zn, and the n-type dopant Ga shutter is also opened to n.
An n-type contact layer 3 made of ZnO is grown to about 1 μm. Then, the shutter of the source (cell) of Mg is opened, and the n-type cladding layer 4 made of Mg 0.15 Zn 0.85 O is grown to about 0.2 μm.

【0033】つぎに、活性層5を成長するため、Mgの
セルおよびドーパントのGaのセルを閉め、Cdのソー
スメタルのセルのシャッターを開いてCdを照射し、C
0. 08Zn0.92Oを0.1μm程度成長する。ついで、
Cdのセルのシャッターを閉め、再度Mgのセルおよび
Gaのセルを開け、さらにp形ドーパントとしてのプラ
ズマ励起N2 を導入する。Gaはn形ドーパントである
が、プラズマ励起N2と同時ドーピングをすることによ
り、効果的にp形化できるため、同時にドーピングして
いる。そして、Mg0.15Zn0.85Oからなるp形クラッ
ド層6を0.2μm程度成長し、同様に同時ドーピング
をしてp形ZnOからなるp形コンタクト層7を1μm
程度成長することにより半導体積層部11を成長する。
Next, in order to grow the active layer 5, the cell of Mg and the cell of Ga as a dopant are closed, the shutter of the cell of the source metal of Cd is opened, and Cd is irradiated.
the d 0. 08 Zn 0.92 O to growth of about 0.1μm. Then
The shutter of the Cd cell is closed, the Mg cell and the Ga cell are opened again, and plasma-excited N 2 as a p-type dopant is introduced. Although Ga is an n-type dopant, it can be effectively p-type by co-doping with plasma-excited N 2 , so that it is doped at the same time. Then, a p-type cladding layer 6 made of Mg 0.15 Zn 0.85 O is grown to a thickness of about 0.2 μm, and simultaneously doped to form a p-type contact layer 7 made of p-type ZnO of 1 μm.
The semiconductor laminated portion 11 is grown by growing the semiconductor layer 11 to a certain degree.

【0034】その後、MBE装置よりエピタキシャル成
長がされたウェハを取り出し、たとえばスパッタ装置に
入れてITO膜を成膜し、透明電極8を0.2μm程度
の厚さに設ける。その後、基板1の裏面を研磨し、10
0μm程度の厚さとし、真空蒸着などにより基板1の裏
面にTi/Alなどからなるn側電極9を全面に、IT
O膜8上の一部にTi/Alなどからなるp側電極10
をたとえばリフトオフ法などにより、それぞれ0.2μ
m程度づつ形成する。その後ウェハからチップ化するこ
とにより、図1に示されるLEDチップが得られる。
After that, the epitaxially grown wafer is taken out from the MBE apparatus and put into, for example, a sputtering apparatus to form an ITO film, and the transparent electrode 8 is provided to a thickness of about 0.2 μm. Thereafter, the back surface of the substrate 1 is polished,
A thickness of about 0 μm, an n-side electrode 9 made of Ti / Al or the like is
P-side electrode 10 made of Ti / Al or the like on a part of O film 8
Are each 0.2 μm by a lift-off method or the like.
m. Thereafter, by chipping from the wafer, the LED chip shown in FIG. 1 is obtained.

【0035】本発明の半導体発光素子によれば、シリコ
ン基板の表面にチッ化シリコン膜が設けられ、その上に
ZnO系化合物半導体層が積層されているため、ZnO
系化合物半導体層が結晶性よく成長されており、シリコ
ン基板を用いた青色系の半導体発光素子が、サファイア
基板上に成長するのと同様の高い発光効率で得られる。
すなわち、従来はシリコン基板上にZnO系化合物半導
体を成長しても、膜質が悪く、非発光再結合中心が多い
ため、発光効率が非常に悪かったが、本発明により、シ
リコン基板を用いた青色系の半導体発光素子が得られ
た。一方、チッ化シリコン膜は100Å以下と非常に薄
い層であり、上下の導電性半導体層に挟まれることによ
り、殆ど電圧降下をすることなく導通性を有する。その
結果、チップの上下からp側電極およびn側電極をそれ
ぞれ取り出すことができる垂直型の発光素子となり、電
極形成のための積層された半導体層の一部をエッチング
する必要がなくなり、非常に製造工程が簡略化すると共
に、発光素子をマウントする場合に両電極をワイヤボン
ディングしないで、一方はダイボンディングにより直接
電極を接続することができてワイヤボンディングを減ら
すことができ、使用面でも非常に便利になる。
According to the semiconductor light emitting device of the present invention, the silicon nitride film is provided on the surface of the silicon substrate, and the ZnO-based compound semiconductor layer is laminated thereon.
Since the system compound semiconductor layer is grown with good crystallinity, a blue semiconductor light emitting device using a silicon substrate can be obtained with the same high luminous efficiency as when growing on a sapphire substrate.
That is, conventionally, even when a ZnO-based compound semiconductor was grown on a silicon substrate, the film quality was poor and the number of non-radiative recombination centers was large, so the luminous efficiency was very poor. As a result, a semiconductor light emitting device was obtained. On the other hand, a silicon nitride film is a very thin layer having a thickness of 100 ° or less, and has conductivity with almost no voltage drop by being sandwiched between upper and lower conductive semiconductor layers. As a result, a vertical light emitting element can be obtained in which the p-side electrode and the n-side electrode can be respectively taken out from the upper and lower sides of the chip, and it is not necessary to etch a part of the laminated semiconductor layer for forming the electrode. The process is simplified, and when mounting the light-emitting element, both electrodes are not wire-bonded, and one of them can be directly connected to the electrode by die bonding, which reduces wire bonding, making it very convenient in terms of use. become.

【0036】さらに、後述するようなLDを形成する場
合に、光共振器の端面を鏡面にすることが好ましいが、
シリコン基板上に立法晶の半導体層が積層されることに
より、基板から半導体積層部が立法晶により整列するた
め、サファイア基板と比べて、劈開をすることが容易で
あり、光共振器の端面を劈開面で形成することができ
る。その結果、発振特性の優れた青色系の半導体レーザ
を得ることができる。
Further, when forming an LD as described later, it is preferable to make the end face of the optical resonator a mirror surface.
By stacking the cubic semiconductor layer on the silicon substrate, the semiconductor stacked portion is aligned by the cubic crystal from the substrate, so that it is easier to cleave than the sapphire substrate, and the end face of the optical resonator is It can be formed on a cleavage plane. As a result, a blue semiconductor laser having excellent oscillation characteristics can be obtained.

【0037】前述の例は、LEDの例であったが、LD
であっても同様である。この場合、半導体積層部11が
若干異なり、たとえば図4に断面説明図が示されるよう
に、活性層15はノンドープのCd0.03Zn0.97O/C
0.2 Zn0.8 Oからなるバリア層とウェル層とをそれ
ぞれ50Åおよび40Åづつ交互に2〜5層づつ積層し
た多重量子井戸構造により形成することが好ましい。ま
た、活性層15が薄く充分に光を活性層15内に閉じ込
められない場合には、たとえばZnOからなる光ガイド
層14、16が活性層15の両側に設けられる。
Although the above-described example is an example of an LED, an LD
The same applies to In this case, the semiconductor laminated portion 11 is slightly different. For example, as shown in a sectional view of FIG. 4, the active layer 15 is made of non-doped Cd 0.03 Zn 0.97 O / C.
It is preferable to form the barrier layer and the well layer made of d 0.2 Zn 0.8 O by a multiple quantum well structure in which 2 to 5 layers are alternately stacked by 50 ° and 40 °, respectively. When the active layer 15 is too thin to sufficiently confine light in the active layer 15, light guide layers 14 and 16 made of, for example, ZnO are provided on both sides of the active layer 15.

【0038】また、図4に示される例では、電流狭窄層
17を埋め込むSAS型構造のLDチップの例で、p形
Mg0.15Zn0.85Oからなるp形第1クラッド層6aの
上に、たとえばn形Mg0.2 Zn0.8 Oからなる電流狭
窄層17が0.4μm程度設けられ、一旦結晶成長装置
からウェハを取り出し、表面にレジスト膜を設けてスト
ライプ状にパターニングをし、NaOHなどのアルカリ
溶液により電流狭窄層17をストライプ状にエッチング
して、ストライプ溝18が形成され、再度MBE装置に
ウェハを戻し、p形Mg0.15Zn0.85Oからなるp形第
2クラッド層6bおよびp形ZnOからなるp形コンタ
クト層7が前述の例と同様に成長されることにより形成
されている。この場合は、ITOからなる透明電極は不
要で、p形コンタクト層7上にもほぼ全面にp側電極1
0が形成されている。なお、図示されていないが、p形
第1クラッド層6aと電流狭窄層17との間にp形Ga
Nからなるエッチングストップ層が設けられることが好
ましい。
In the example shown in FIG. 4, an LD chip having a SAS structure in which the current confinement layer 17 is buried is formed, for example, on the p-type first cladding layer 6a made of p-type Mg 0.15 Zn 0.85 O. A current confinement layer 17 made of n-type Mg 0.2 Zn 0.8 O is provided in a thickness of about 0.4 μm. Once the wafer is taken out of the crystal growth apparatus, a resist film is provided on the surface and patterned in a stripe shape, and the resultant is exposed to an alkaline solution such as NaOH. The current confinement layer 17 is etched in a stripe shape to form a stripe groove 18, and the wafer is returned to the MBE apparatus again, and the p-type second cladding layer 6b made of p-type Mg 0.15 Zn 0.85 O and the p-type ZnO The contact layer 7 is formed by growing in the same manner as in the above-described example. In this case, a transparent electrode made of ITO is unnecessary, and the p-side electrode 1 is almost entirely formed on the p-type contact layer 7.
0 is formed. Although not shown, a p-type Ga layer is provided between the p-type first cladding layer 6a and the current confinement layer 17.
It is preferable to provide an etching stop layer made of N.

【0039】ZnO系化合物半導体は、ウェットエッチ
ングによりエッチング処理をすることができるため、G
aN系化合物半導体では難しい電流狭窄層を埋め込むS
AS型構造のLDチップを形成することができ、活性層
の近くに電流狭窄層を形成することができ、高特性の半
導体レーザが得られる。しかし、LDチップの構造は、
SAS型構造に限らず、p側電極をストライプ状にした
だけの電極ストライプ構造や、ストライプ状電極の両側
の半導体層をp形クラッド層の上部までをメサ型形状に
エッチングするメサストライプ構造や、プロトンなどを
打ち込んだプロトン打込み型にすることもできる。電極
ストライプ構造のLDチップの例を図5に示す。この構
造はp側電極10がストライプ状にパターニングされて
いることと、電流狭窄層が設けられていない点で図4の
構造と異なるだけで、他の構造は図4と殆ど同じで、同
じ部分には同じ符号を付して、その説明を省略する。な
お、6はp形クラッド層である。
Since ZnO-based compound semiconductors can be etched by wet etching, G
S to bury current constriction layer, which is difficult with aN-based compound semiconductor
An LD chip having an AS type structure can be formed, a current confinement layer can be formed near an active layer, and a semiconductor laser with high characteristics can be obtained. However, the structure of the LD chip is
Not limited to the SAS type structure, an electrode stripe structure in which the p-side electrode is simply formed in a stripe shape, a mesa stripe structure in which the semiconductor layers on both sides of the stripe-shaped electrode are etched into a mesa shape up to the top of the p-type cladding layer, A proton implantation type in which protons or the like are implanted can also be used. FIG. 5 shows an example of an LD chip having an electrode stripe structure. This structure is different from the structure in FIG. 4 only in that the p-side electrode 10 is patterned in a stripe shape and the current constriction layer is not provided, and other structures are almost the same as those in FIG. Are denoted by the same reference numerals, and description thereof is omitted. Reference numeral 6 denotes a p-type cladding layer.

【0040】このような構造にしても、基板にシリコン
が用いられているため、上下両面から両電極を取り出す
ことができ、製造面および使用面の両方から非常に便利
であると共に、光共振器の端面を劈開による劈開面で形
成することができるため、高特性の半導体レーザが得ら
れる。
Even in such a structure, since silicon is used for the substrate, both electrodes can be taken out from both the upper and lower surfaces, which is very convenient from both the manufacturing and use sides, and has an optical resonator. Can be formed as cleavage planes by cleavage, so that a semiconductor laser with high characteristics can be obtained.

【0041】前述の例では、LEDとして、ダブルヘテ
ロ構造の例であったが、単純なpn接合やMIS(金属
−絶縁層−半導体層)構造など他の構造にすることもで
きる。また、LDチップの構造も、光ガイド層がなく他
の層が設けられたり、前述の積層構造に限定されるもの
ではない。さらに、シリコン基板のチッ化処理やその後
のZnO系化合物半導体の成長をMBE装置を用いて行
ったが、MOCVD装置などを用いてチッ化処理および
その後の半導体層の成長を行っても、その条件さえ設定
されれば、一々表面状態を観察しながら行う必要はな
く、同様の表面状態を形成することができ、他の方法で
製造することもできる。
In the above example, the LED has a double hetero structure, but other structures such as a simple pn junction or a MIS (metal-insulating-semiconductor layer) structure may be used. In addition, the structure of the LD chip is not limited to the above-described laminated structure without the light guide layer provided with another layer. Furthermore, although the silicon substrate and the subsequent growth of the ZnO-based compound semiconductor were performed using the MBE apparatus, even if the nitrogen processing and the subsequent growth of the semiconductor layer were performed using the MOCVD apparatus, etc. As long as it is set, it is not necessary to perform the observation while observing the surface state, and the same surface state can be formed, and it can be manufactured by another method.

【0042】[0042]

【発明の効果】本発明によれば、シリコン基板上にZn
O系化合物半導体を成長することができ、上下両面に電
極を設ける垂直型の青色系の半導体発光素子が得られ
る。そのため、製造工程が簡単でコストダウンを行うこ
とができると共に、使用段階でもワイヤボンディングを
減らすことができ、使用しやすい半導体発光素子が安価
に得られる。
According to the present invention, Zn is deposited on a silicon substrate.
An O-based compound semiconductor can be grown, and a vertical blue semiconductor light-emitting device having electrodes on both upper and lower surfaces can be obtained. Therefore, the manufacturing process is simple, cost can be reduced, and wire bonding can be reduced even at the stage of use, so that an easy-to-use semiconductor light emitting device can be obtained at low cost.

【0043】さらに、劈開することができるため、優れ
た端面を有するレーザ共振器が得られ、高い記憶密度を
有する光ディスクや、レーザビームプリンタの高精細化
に利用できる短波長の高性能の半導体レーザが得られ
る。
Further, since the laser cavity can be cleaved, a laser resonator having an excellent end face can be obtained, and an optical disk having a high storage density and a high-performance semiconductor laser with a short wavelength which can be used for high definition of a laser beam printer. Is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体発光素子の一実施形態のLED
チップの斜視説明図である。
FIG. 1 shows an LED according to an embodiment of the semiconductor light emitting device of the present invention.
It is a perspective explanatory view of a chip.

【図2】シリコン基板表面のチッ化処理の温度と時間に
よる好ましい条件の関係を示す図である。
FIG. 2 is a diagram showing a relationship between preferable conditions depending on temperature and time of a nitrification treatment of a silicon substrate surface.

【図3】RHEED法による基板表面の検査方法の説明
図および観察される基板表面の回折像の説明図である。
FIG. 3 is an explanatory view of a method of inspecting a substrate surface by the RHEED method and an explanatory view of an observed diffraction image of the substrate surface.

【図4】本発明の半導体発光素子の他の実施形態の断面
説明図である。
FIG. 4 is an explanatory sectional view of another embodiment of the semiconductor light emitting device of the present invention.

【図5】本発明の半導体発光素子の他の実施形態の断面
説明図である。
FIG. 5 is an explanatory sectional view of another embodiment of the semiconductor light emitting device of the present invention.

【図6】従来のGaN系化合物半導体を用いたLDチッ
プの一例の斜視説明図である。
FIG. 6 is a perspective explanatory view of an example of a conventional LD chip using a GaN-based compound semiconductor.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 シリコンチッ化膜 4 n形クラッド層 5 活性層 6 p形クラッド層 11 半導体積層部 Reference Signs List 1 silicon substrate 2 silicon nitride film 4 n-type clad layer 5 active layer 6 p-type clad layer 11 semiconductor laminated portion

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成11年8月2日(1999.8.2)[Submission date] August 2, 1999 (1999.8.2)

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項4[Correction target item name] Claim 4

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0006[Correction target item name] 0006

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0006】本発明はこのよな問題を解決するために
なされたもので、ZnO系化合物半導体を用い、チップ
の表裏両面から電極を取り出すことができる垂直型で、
かつ、半導体層の結晶性が優れて発光効率が高いと共
に、基板にサファイア基板を用いないで製造プロセスお
よび使用面で便利な構造となる半導体発光素子およびそ
の製法を提供することを目的とする。
[0006] The present invention has been made to solve the Do you Yo this problem, using the ZnO based compound semiconductor, a vertical type that can be taken out electrodes from both sides of the chip,
It is another object of the present invention to provide a semiconductor light emitting device having excellent crystallinity of a semiconductor layer and high luminous efficiency, and having a structure convenient in terms of a manufacturing process and use without using a sapphire substrate, and a method for manufacturing the same.

【手続補正3】[Procedure amendment 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0023[Correction target item name] 0023

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0023】[0023]

【表1】 この膜質の検査は、図3(a)に示されるように、一般
にMBE装置に装備されている反射高エネルギー電子回
折法(RHEED法)と呼ばれる方法、すなわち電子銃
51により10〜50kVで加速された電子ビーム52
を基板53表面に浅い角度(1〜2゜以下)θで入射さ
せ、表面原子によって反射回折された電子ビーム54を
蛍光スクリーン55に投影して結晶の表面状態を調べる
方法を用い、電子の加速電圧を20Vで行った。この
方法により行うことにより、電子ビームの入射、反射、
回折ビームの計測が浅い角度で行われるため、ほぼ基板
53に垂直な方向から行われる分子線の供給に影響を与
えないで、成膜しながら測定することができる。
[Table 1] As shown in FIG. 3A, the inspection of the film quality is accelerated at 10 to 50 kV by an electron gun 51, that is, a method generally called a reflection high energy electron diffraction method (RHEED method) provided in the MBE apparatus. Electron beam 52
Is incident on the surface of the substrate 53 at a shallow angle (1 to 2 ° or less) θ, and the electron beam 54 reflected and diffracted by the surface atoms is projected on the fluorescent screen 55 to examine the surface state of the crystal. voltage was carried out in the 20 k V. By performing this method, the incidence, reflection,
Since the measurement of the diffracted beam is performed at a shallow angle, the measurement can be performed while forming the film without affecting the supply of the molecular beam performed from a direction substantially perpendicular to the substrate 53.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岩田 拡也 茨城県つくば市梅園1−1−4 通商産業 省 工業技術院電子技術総合研究所内 (72)発明者 ポール・フォンス 茨城県つくば市梅園1−1−4 通商産業 省 工業技術院電子技術総合研究所内 (72)発明者 田辺 哲弘 京都市右京区西院溝崎町21番地 ローム株 式会社内 (72)発明者 高須 秀視 京都市右京区西院溝崎町21番地 ローム株 式会社内 Fターム(参考) 5F041 AA03 AA31 AA42 CA02 CA04 CA06 CA23 CA33 CA34 CA40 CA41 CA46 CA65 CA66 CA73 CA82 CA88 CA92 CB02 CB03 DA07 FF13 FF16 5F073 AA04 AA07 AA74 BA04 BA07 CA22 CB04 CB07 CB22 DA05 DA06 DA21 DA32 EA07 FA27 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroya Iwata 1-1-4 Umezono, Tsukuba, Ibaraki Pref. Ministry of International Trade and Industry (METI) (72) Inventor Paul Fons 1 Umezono, Tsukuba, Ibaraki -1-4 Ministry of International Trade and Industry, National Institute of Advanced Industrial Science and Technology (72) Inventor Tetsuhiro Tanabe 21 Ryoin Mizozakicho, Ukyo-ku, Kyoto City Inside Rohm Co., Ltd. Address ROHM F-term (reference) FA27

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板と、該シリコン基板の表面
に設けられるシリコンチッ化膜と、該シリコンチッ化膜
上に設けられ、ZnO系化合物半導体からなるn形層お
よびp形層を少なくとも有し、発光層を形成すべく積層
される半導体積層部とを含むシリコン基板を用いたZn
O系化合物半導体発光素子。
1. A semiconductor device comprising: a silicon substrate; a silicon nitride film provided on a surface of the silicon substrate; and at least an n-type layer and a p-type layer provided on the silicon nitride film and made of a ZnO-based compound semiconductor Using a silicon substrate including a semiconductor laminated portion laminated to form a light emitting layer
O-based compound semiconductor light emitting device.
【請求項2】 前記シリコンチッ化膜の表面がアモルフ
ァス化しないで平坦面に形成されてなる請求項1記載の
半導体発光素子。
2. The semiconductor light emitting device according to claim 1, wherein a surface of said silicon nitride film is formed on a flat surface without being made amorphous.
【請求項3】 前記シリコンチッ化膜が、100Å以下
の厚さに形成されてなる請求項1または2記載の半導体
発光素子。
3. The semiconductor light emitting device according to claim 1, wherein said silicon nitride film is formed to a thickness of 100 ° or less.
【請求項4】 前記半導体積層部が、Cdx Zn1-x
(0≦x<1)からなる活性層を、Mgy Zn1-y
(0≦y<1)からなり前記活性層よりバンドギャップ
エナルギーの大きいクラッド層により挟持するダブルヘ
テロ構造を有する請求項1、2または3記載の半導体発
光素子。
4. The method according to claim 1, wherein the semiconductor lamination portion is Cd x Zn 1-x O
The active layer composed of (0 ≦ x <1) is formed of Mg y Zn 1-y O
4. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device has a double hetero structure which is sandwiched by a cladding layer made of (0 ≦ y <1) and having a band gap energy larger than that of the active layer.
【請求項5】 シリコン基板をチッ素が存在する雰囲気
下で熱処理することによりシリコン基板の表面にシリコ
ンチッ化膜を形成し、該シリコンチッ化膜上にZnO系
化合物半導体からなり発光層を形成する半導体積層部を
成長することを特徴とする半導体発光素子の製法。
5. A silicon nitride film is formed on a surface of the silicon substrate by heat-treating the silicon substrate in an atmosphere in which nitrogen is present, and a light emitting layer is formed on the silicon nitride film by using a ZnO-based compound semiconductor. A method for manufacturing a semiconductor light emitting device, comprising: growing a semiconductor laminated portion to be formed.
【請求項6】 前記シリコンチッ化膜を形成する処理
を、形成されるシリコンチッ化膜の表面がシリコン基板
の平坦面を維持できるように該処理の温度または時間を
制御しながら行う請求項5記載の半導体発光素子の製
法。
6. A process for forming the silicon nitride film while controlling the temperature or time of the process so that the surface of the formed silicon nitride film can maintain the flat surface of the silicon substrate. A method for producing the semiconductor light-emitting device according to the above.
JP21122299A 1999-07-26 1999-07-26 ZnO-based compound semiconductor light emitting device using silicon substrate and method of manufacturing the same Expired - Lifetime JP4425376B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP21122299A JP4425376B2 (en) 1999-07-26 1999-07-26 ZnO-based compound semiconductor light emitting device using silicon substrate and method of manufacturing the same
PCT/JP2000/004998 WO2001008229A1 (en) 1999-07-26 2000-07-26 ZnO COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND PRODUCTION METHOD THEREOF
EP07123034A EP1912298A1 (en) 1999-07-26 2000-07-26 ZnO based compound semiconductor light emitting device and method for manufacturing the same
KR1020027001072A KR100694928B1 (en) 1999-07-26 2000-07-26 Phenolic compound semiconductor light emitting device and method of manufacturing the same
TW089114903A TW469511B (en) 1999-07-26 2000-07-26 ZnO compound-based semiconductor light emitting element, and manufacturing process therefor
EP00949916A EP1199755A4 (en) 1999-07-26 2000-07-26 ZNO COMPOSITE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND ITS PRODUCTION METHOD
US10/031,931 US6674098B1 (en) 1999-07-26 2000-07-26 ZnO compound semiconductor light emitting element
US10/713,205 US6987029B2 (en) 1999-07-26 2003-11-17 ZnO based compound semiconductor light emitting device and method for manufacturing the same
US11/166,254 US7605012B2 (en) 1999-07-26 2005-06-27 ZnO based compound semiconductor light emitting device and method for manufacturing the same

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WO2002045179A1 (en) * 2000-11-30 2002-06-06 Shin-Etsu Handotai Co.,Ltd. Light-emitting device and its manufacturing method and visible-light-emitting device
KR100389738B1 (en) * 2001-03-05 2003-06-27 김영창 SHORT WAVELENGTH ZnO LED AND METHOD FOR PRODUCING OF THE SAME
US6982438B2 (en) 2001-07-25 2006-01-03 Shin-Etsu Handotai Co., Ltd. Light emitting device and method for fabricating the same
WO2003049205A1 (en) * 2001-11-30 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Light emitting element and manufacturing method thereof
JP2004228318A (en) * 2003-01-22 2004-08-12 Sharp Corp Oxide semiconductor light emitting device
JP2004247654A (en) * 2003-02-17 2004-09-02 Sharp Corp Oxide semiconductor light emitting device, method of manufacturing the same, and semiconductor light emitting device using oxide semiconductor light emitting device
JP2004266057A (en) * 2003-02-28 2004-09-24 Sharp Corp Oxide semiconductor light emitting device and method of manufacturing the same
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WO2006080099A1 (en) * 2005-01-25 2006-08-03 Kodenshi Corporation Photodiode having hetero-junction between semi-insulating zinc oxide semiconductor thin film and silicon

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