JP2001043690A - Negative booster circuit, nonvolatile semiconductor memory device using the same, and semiconductor circuit device - Google Patents

Abstract

(57) Abstract: In a negative booster circuit, the influence of a parasitic bipolar transistor on a substrate is suppressed, and the re-recovery time is shortened. SOLUTION: The effect of a parasitic NPN bipolar transistor on a substrate is suppressed by using an N-channel MOS transistor having a triple well structure capable of arbitrarily setting a substrate potential, and a charge between series-connected capacitors generated during a boosting operation. Is provided with an intermediate node reset circuit 103 for resetting when the step-up operation is not performed.
High efficiency and low voltage operation with transistors,
It is possible to realize a negative booster circuit in which the recovery time is fast and the power consumption during the recovery is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a negative booster circuit, a nonvolatile semiconductor memory device and a semiconductor circuit device using the same, and more particularly, to a charge pump type negative booster circuit comprising N-channel MOS transistors having a triple well structure. And a non-volatile semiconductor storage device and a semiconductor circuit device using the same.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device such as a flash EEPROM requires a positive high voltage higher than a power supply voltage and a negative high voltage lower than a ground as shown in FIG. It is. In recent years, due to demands for downsizing the system, mounting of a booster circuit for generating a high voltage in a semiconductor circuit device is desired.

First, as a basic booster circuit, a Dickson type charge pump type negative booster circuit for generating a negative voltage will be described. FIG.
FIG. 12A is a charge pump type negative booster circuit that generates a negative voltage composed of a diode element, a capacitor, and a boosting clock; FIG. 12B is a clock used in the negative booster circuit; FIG. 5 is a waveform diagram showing a node and an output voltage. In FIG. 12A, CLKA (12
01) and CLKB (1202) are boosting clocks having the same frequency and opposite phases. When both clocks CLKA and CLKB are at L level, they are set to GND.
When it is at the H level, it becomes the power supply voltage VDD. C1201,
C1202 are the clocks CLKA and CLK, respectively.
This is a capacitor that synchronizes with B and increases or decreases the potential of the nodes N1201 and N1202. C1203 is an output capacity.
D1201 is a diode for input rectification to prevent backflow of a negative voltage generated inside the circuit to the input level VSS, D1202 is a rectification diode between the nodes N1201 and N1202, and D1203 is an output rectification diode for the output OUT12. It is a diode.

The operation of the charge pump type negative booster circuit shown in FIG. First, when one clock CLKA is at the H level and the other clock CLKB is at the L level, the node N1202
, The potential is lowered from the initial potential (0 V) to −VDD. Since the potential of the node N1202 is lower than the potential of the output OUT12, a PN forward current flows through the diode D1203. Next, when the clock CLKA goes low and the clock CLKB goes high, the potential of the node N1202 becomes higher than the potential of the output OUT12, so that the PN forward current of the diode D1203 stops. On the other hand, since the clock CLKA becomes L level, the diode D
A PN forward current starts to flow into 1202. As mentioned above,
By repeatedly synchronizing with the clocks CLKA and CLKB, the potential of each node changes, and a current flows to the node having a lower potential by the diode, that is, the charge moves, and a negative voltage is gradually generated at the output OUT12. The ideal final potential is that the output OUT12 is −2 (VDD−Vd) + V
d, the node N1202 has a negative voltage of −2 (VDD−Vd), and the node N1201 has a negative voltage of − (VDD−Vd). Here, Vd is the junction voltage of the PN junction. The negative booster circuit using the clock and the capacity is called a charge pump type negative booster circuit. Note that by changing the direction of each diode, a positive voltage can be generated.

The above is a charge pump type negative booster circuit using a diode element. Next, a description will be given of a charge pump type negative booster circuit composed of MOS transistors in order to incorporate this charge pump type negative booster circuit into an LSI such as a nonvolatile semiconductor memory device.

FIG. 13A shows a charge pump type negative booster circuit using a P-channel MOS transistor.
(B) is a waveform diagram showing a clock used in the negative booster circuit, a node of the negative booster circuit, and an output voltage. CLKA and CLKB are boosting clocks having the same frequency and opposite phases, C1301 and C1302
Is a capacitor for increasing or decreasing the potentials of the nodes N1301 and N1302 in synchronization with the clocks CLKA and CLKB.
Reference numerals 301, M1302, and M1303 are P-channel MOS transistors corresponding to the diode elements in FIG.

Hereinafter, a P-channel MO shown in FIG.
The operation of the charge pump type negative booster circuit using the S transistor will be described. First, it is assumed that the clock CLKA changes to the L level and the clock CLKB changes to the H level.
When the potential of node N1301 is lower than the potential of node N1302 by the threshold value Vth of P-channel MOS transistor M1302, the potential of node N1302 is reduced to the potential of node N1 via P-channel MOS transistor M1302.
A current flows in the direction of 301. That is, the P-channel MO
The S transistor M1302 has the same boosting effect as the diode element of FIG. 12A, and generates a negative voltage at the output OUT1301. However, an increase in the threshold value Vth of the P-channel MOS transistor described below hinders this boosting operation.

Hereinafter, the threshold value of the MOS transistor and the rise of the threshold value due to the substrate bias effect will be described using a general equation. Vth = Vth0 + ΔVth (VBB)

FIG. 3 shows the dependency of the threshold value Vth of the MOS transistor on the source-substrate potential difference VBB. V
th0 is the threshold voltage at VBB = 0,

(Equation 1) And ΔVth (VBB) is the amount of change in the threshold voltage due to VBB,

(Equation 2) Becomes Where K and Φ are

(Equation 3) Φ = (kT / q) ln (N / ni)

[0010] Where VFB is the flat band voltage, Cox is the oxide film capacitance, N is the impurity concentration of the substrate, ni is the intrinsic carrier concentration of silicon, εs is the dielectric constant of silicon, q is the charge of electrons, T is the absolute temperature, and k is the absolute temperature. Boltzmann's constant, K, represents the sensitivity of Vth to VBB and is called the substrate effect constant. From these relational expressions, as shown in FIG.
That is, as the P-channel MOS transistor becomes closer to the output, the potential difference VBB between the P + diffusion and the N-substrate increases.
It becomes clear that the threshold value also rises.

Next, the reason why the substrate potential of the P-channel MOS transistors M1301, M1302 and M1303 in FIG. 13A is set to VSS will be described. In a normal P-type silicon wafer / N-well twin-well MOS process, the potential of the N-well of the P-channel MOS transistor is set to VDD. This is because, when a positive voltage is applied to the P + diffusion, if the N well is set to VSS, the P + diffusion and the N well are in a PN forward direction relationship.
A current flows from the diffusion in the direction of the N well, but this is to prevent it. However, since the booster circuit of this time handles a negative voltage, there is no possibility as described above. Therefore, the substrate potential is set to VSS in order to suppress a rise in the threshold value caused by the potential difference between the drain / source of the MOS transistor and the substrate, that is, to make VBB as small as possible. However, when the N-substrate is set to VSS and V
Even if BB is suppressed, an increase in the threshold value in the subsequent stage of the negative booster circuit is unavoidable, and the increase in the threshold value hinders the boosting operation.

As described above, it can be seen that the charge pump type negative booster circuit composed of P-channel MOS transistors has a limit on boosting capability due to an increase in threshold. By the way, if the N-well and the P + diffusion are short-circuited, the rise of the threshold can be suppressed. However, a negative voltage is applied to the N-well, and the P-type silicon wafer and the N-well become PN.
It becomes a forward direction, a leak occurs, and the boosting operation is hindered.

Therefore, recently, on a P-type silicon wafer,
Semiconductor MO having twin well structure forming N well
From the S process, a P-well is implanted into an N-well as shown in FIG.
An S process has been developed. Next, the N channel M
A case where a charge pump type negative booster circuit is formed using an OS transistor will be described. In general, an N-channel MO
When a negative booster circuit is formed by S transistors, a negative voltage is applied to the N + diffusion, so that the P-type silicon wafer and the N + diffusion have a PN forward direction relationship, a current flows, and a negative boost operation cannot be performed. However, by making the N-channel MOS transistor a triple well structure, the problem of the PN forward current between the P-type silicon wafer and the N + diffusion is also reduced.
Also, the N well and the P +
The problem of leakage when the diffusion is short-circuited can also be prevented. In FIG. 15, 1501 is a P-type silicon wafer, 1502 is an N-well (hereinafter, Deep-N well) formed on the P-type silicon wafer 1501,
1503 is a P-well formed on the Deep-N well 1502, and M1501 is a P-well 1503
Is an N-channel MOS transistor.
When a charge pump type negative booster circuit constituted by the N-channel MOS transistor M1501 having the triple well structure is realized, even if a negative voltage is input to the P well 1503, the P-type silicon wafer 1501, the Deep-N well 15
02, the N-channel MO
The source (N + diffusion) of S transistor M1501 and P well 1503 can be short-circuited, and a negative booster circuit in which boosting efficiency does not decrease due to a rise in threshold value caused by the body bias effect can be realized.

In this case as well, although the effect of the threshold value Vth0 at VBB = 0 still remains, a threshold canceling type charge pump type negative booster circuit which completely eliminates the effect of the threshold value Vth0 has also been proposed. Have been. Hereinafter, a threshold canceling type charge pump type negative booster circuit will be described with reference to FIG.

The charge pump type negative booster circuit of the threshold canceling type is basically the same as the boosting operation performed by the diode element shown in FIG. M160 in FIG.
1, M1603 is an N-channel MOS transistor corresponding to the diode element in FIG.
2. M1604 is an N-channel MOS transistor M1
By controlling the gate voltages of the N-channel MOS transistors M1601 and M1603,
An N-channel MOS transistor C1 for surely turning OFF the circuit 1603 or ON state on the contrary
1601 and C1603 are clock CLK
1. Nodes N1601, N1602 in synchronization with CLK2
C1602 and C1604, which increase and decrease the potential of the node N1603, respectively, and synchronize the clocks CLK3 and CLK4, respectively.
This is a capacitor for increasing or decreasing the potential of N1605 and pumping the gate potential of N-channel MOS transistors M1601 and M1603.

Next, the operation of the charge pump type negative booster circuit of the threshold cancellation type will be described. In the charge pump type negative booster circuit of the threshold canceling system, four booster clocks CLK1, CLK2,
CLK3 and CLK4 are required. The operation of the negative booster circuit will be described by dividing the time. First, in the section T1, the clocks CLK1 and CLK2 are at the H level and the clock CLK
3. CLK4 is fixed at L level. As in the sections T2 and T4, when the clock CLK1 falls to the L level, the node N1601 is clocked down by the capacitor C1601 to about -VDD. N-channel MOS transistor M having node N1601 as a gate terminal
1602 is turned off, and a potential difference is applied between the gate terminal of the N-channel MOS transistor M1601 and the node N1601, so that the potential at the node N1602 changes to the node N1.
A current flows to 601 (charge moves in the opposite direction). Next, as in the section T3, the clock CLK
When 3 goes to the H level, the gate potential of N-channel MOS transistor M1601 rises, N-channel MOS transistor M1601 is reliably turned on, and the current from node N1602 to node N1601 can be increased. As a result, the node N1601 and the node N16
02 has the same potential relationship. Similarly to the clock CLK1, when the clock CLK2 changes to the L level, the node N
The potential of 1602 becomes -VDD. Sections T6, T7 and T
At 8, the potential at the node N1602 becomes negative,
The channel MOS transistor M1602 turns ON,
The gate potential of N-channel MOS transistor M1601 is set to be the same as the potential of node N1602. Since the gate potential is the same as the potential of node N1602, N-channel MOS transistor M1601 is completely turned off. On the other hand, N-channel MOS transistor M1603
As in the case of the N-channel MOS transistor M1601 in which the clock CLK1 is at the L level, the transistor is completely turned on, and a current flows from the node N1604 to the node N1602. As described above, the four boosting clocks C
As the operations of LK1, CLK2, CLK3, and CLK4 continue, charges move, and a negative voltage can be generated.

In recent years, a negative booster circuit of the threshold canceling type has been adopted, and a negative voltage of about -10 V is generated. However, when a potential difference of -10 V is applied to both ends of the capacitor, a device must be developed that can maintain a high voltage. If the voltage generated by the negative booster circuit is larger than the withstand voltage of the capacitor, the capacitors C101 and C101 shown in FIG.
Capacitors are connected in series as in 102, and the voltage applied to one capacitive element is divided to reduce the voltage.

[0018]

When a charge pump type negative booster circuit is constituted by P-channel MOS transistors, there is a problem that the boosting capability is reduced due to the substrate bias effect. Therefore, a charge pump type negative boosting circuit using an N-channel MOS transistor has been proposed. However, when performing a negative boosting operation with an N-channel MOS transistor, the relationship between the N + diffusion of the transistor and the P-type silicon wafer in the PN forward direction is established. And the boost operation cannot be performed. Therefore, FIG.
5, a CMOS process having a triple well structure has been proposed.

However, the NPN bipolar transistor parasitic on the triple well structure has a great influence on the boosting operation, and sometimes the boosting operation cannot be performed at all beyond the reduction of the boosting capability. The parasitic NPN bipolar transistor having the triple well structure is represented by Q1 in FIG.
As shown at 501, the Deep-N well 1502 is a collector terminal, the P well 1503 in the Deep-N well 1502 is a base terminal, and the N + diffusion 1507 of the N-channel MOS transistor M1501 is an emitter terminal.
FIG. 17 is a circuit diagram showing a part of a negative booster circuit including an N-channel MOS transistor, which also specifies a parasitic NPN bipolar transistor. N-channel MOS transistor M1501 shown in FIG. 15 corresponds to N-channel MOS transistor M1701 in FIG. FIG.
The NPN bipolar transistor Q1501 corresponds to the NPN bipolar transistor Q1701 in FIG. 17, and the capacitor C1501 in FIG. 15 corresponds to a capacitor between the node N1701 and the clock CLKA in FIG.

Now, assuming that the clock CLKA transitions from the H level to the L level to start the negative boosting operation, the node N1502 is pulled down from the potential in the initial state via the capacitor C1501. Node N1502 is N channel M
It is connected to the N + diffusion 1507 of the OS transistor M1501, and when the node N1502 shifts to a low potential, the N-channel MOS transistor M1501
Is in the ON state, a current flows from the capacitor C1502 to the capacitor C1501, and a charge is moved to generate a negative voltage. In the triple well structure, the P well 1503 and the N + diffusion 1507
Since the reaction is in a forward direction and the reaction speed of the PN junction diode is faster than the reaction speed of the MOS transistor, a current flows from the P well 1503 to the N + diffusion 1507 first. This PN forward current becomes the base current of NPN bipolar transistor Q1501, and De
A collector current is generated with the ep-N well 1502 as a collector terminal. Collector current is Deep-N well 1
The potential Vnt of 502 flows from VDD which has been fixed. That is, the negative boosting operation due to the potential change from the H level to the L level of the boosting clock causes the NPN bipolar transistor Q1501 parasitic on the triple well structure.
And the negative boost operation is hindered.

Next, the problem of the capacitance connected in series to reduce the high voltage applied to both ends will be described. High voltage can be generated by using a negative booster circuit.
The capacitance element is between the internal node and the clock, and the largest voltage is applied. Assuming that the withstand voltage of the capacitor is 10 V, when the voltage is increased by 10 V or more, the capacitors are connected in series to divide the voltage applied to one capacitor. FIG.
Is a charge pump type negative booster circuit having a mechanism of connecting capacitors in series and dividing a voltage applied to one capacitor so that the voltage applied to each capacitor does not exceed the withstand voltage of the capacitor. The capacitors C101 and C102 in FIG.
Is a capacitor connected in series to divide the voltage applied between the nodes N101 and N103. When the charge pump type negative booster circuit shown in FIG. 1 is started, electric charge also accumulates at the intermediate node N102 of the capacitor connected in series. The problem here is that even if the boosting operation is stopped once, the intermediate node N102 of the capacitance elements C101 and C102 is connected only to the capacitance, so that the charge accumulated there is ideally held. Nodes N101, N
Even if the voltage of the node 103 becomes the initial state (0 V) and the boosting operation is restarted, the clocking operation is not transmitted to the node N101 because the charge is accumulated in the node N102, and the startup time is long. Reference numeral 1801 in FIG. 18 is an example in which the intermediate node of the booster circuit is reset. However, although 1801 in FIG. 18 can reset the middle of the booster circuit, it cannot be used as means for resetting the intermediate node of the series-connected capacitors.

The present invention has been made in view of such a problem, and it is possible to provide a negative booster circuit which operates at a high efficiency and a low voltage by disabling a bipolar transistor parasitic on a triple well structure. And
An object of the present invention is to provide a means for resetting an intermediate node of a capacitor connected in series, thereby shortening a restart time of a negative booster circuit.

[0023]

In order to achieve the above object, a negative boosting circuit according to the first aspect of the present invention includes a gate, a source, and a drain of an N-channel MOS transistor formed in a P-well having a triple well structure. In a negative booster circuit that increases and decreases the potential by using a clock via a capacitor and generates a negative voltage, the P well is set to a floating potential or the P well is set to a predetermined potential.

According to a second aspect of the present invention, a negative booster circuit is provided.
5. The negative booster circuit according to claim 1, wherein:
The potential of the Deep-N well is set to a floating potential.

According to a third aspect of the present invention, there is provided a negative booster circuit according to the first aspect.
Wherein the negative voltage is applied to the P well.

According to a fourth aspect of the present invention, there is provided a negative booster circuit according to the third aspect.
In the negative booster circuit described in (1), a negative voltage is externally applied to the P well, and when the P well becomes a specific negative voltage, this is detected, and a boosting clock of the negative booster circuit is supplied. And the potential of the P-well at the preceding stage of the negative boosting circuit is compared with the potential of the boosting node at the subsequent stage, and the potential at the boosting node at the subsequent stage is lower by a specific potential than the potential at the P-well at the preceding stage. A switching circuit configured to switch the P-well to apply the negative voltage of the subsequent boosting node instead of the externally applied negative voltage.

According to a fifth aspect of the present invention, a negative booster circuit is provided.
The clock booster circuit according to claim 1, further comprising a clock modulator that outputs a clock signal obtained by modulating an input clock signal by shortening an H-level time interval of the signal by a predetermined time. A P-well is supplied with a clock signal for use and the P-well is pumped to a negative voltage by the modulated clock signal.

According to a sixth aspect of the present invention, there is provided a negative booster circuit according to the first aspect.
6. The negative booster circuit according to claim 5, wherein said negative booster circuit is connected in series between nodes having a potential exceeding a withstand voltage of a capacitive element used for boosting operation. A reset circuit is provided for setting an intermediate node therebetween to a predetermined initial potential when the circuit is not operating.

According to a seventh aspect of the present invention, there is provided a nonvolatile semiconductor memory device including the negative booster circuit according to any one of the first to sixth aspects.

An eighth aspect of the present invention is a semiconductor circuit device including the negative booster circuit according to any one of the first to sixth aspects.

[0031]

(Embodiment 1) A negative booster circuit according to Embodiment 1 of the present invention employs N
An N-channel MOS transistor having a triple well structure is used as a channel MOS transistor, and the P-well and the Deep-N-well are set to a floating potential, thereby disabling the parasitic NPN bipolar transistor.

FIG. 2 shows an N-channel MO having a triple well structure used in the negative booster circuit according to the first embodiment.
FIG. 3 is a diagram showing a cross section of an S transistor. FIG. 3 shows a negative booster circuit using the N-channel MOS transistor having the triple well structure of FIG. In FIG. 2, 201 is
The P-type silicon wafer 202 includes a Deep-N well 203 formed on the P-type silicon wafer 201,
Is a P-well formed on the Deep-N well 202, 208 is a P-well terminal of a floating potential, and 209 is
Deep-N well terminal of floating potential, M201 is an N channel MOS transistor formed on the P well 203, Q201 is an NPN bipolar transistor parasitic on the triple well structure of the N channel MOS transistor M201, C201, C202 Is a capacitor that increases or decreases the potentials of the nodes N202 and N203 by synchronizing with a boosting clock (not shown). In FIG. 3, CLKA and CLKB are boosting clocks.

In the negative booster circuit according to the first embodiment thus configured, the parasitic NPN bipolar transistor Q20 of the N-channel MOS transistor M201
The boosting operation for disabling 1 will be described below. Since the P well 203 and the Deep-N well 202 are separated from each other, the respective potentials can be set to a specific potential or a floating potential (floating). P well 20
3. By setting the Deep-N well 202 to a floating potential, the potential of the base and the collector of the parasitic NPN bipolar transistor Q201 becomes floating,
Even if the base current Ib flows from the P-well 203 to the node N202 by the boosting operation by synchronizing the capacitor C201 with the boosting clock (not shown), the Deep-N well 202 is floating, and therefore, the Deep-N
Only the charge existing in the well 202 flows initially,
Stationary collector current Ie is not generated.

As described above, the negative booster circuit according to the first embodiment has an N-channel MO having a triple well structure in which the P well 203 and the Deep-N well 202 have floating potentials.
With the provision of the S transistor M201, the parasitic NPN bipolar transistor Q201 is invalidated, and an efficient negative booster circuit can be realized.

(Second Embodiment) A negative booster circuit according to a second embodiment of the present invention is similar to the deep boost circuit according to the first embodiment.
Regardless of whether or not the potential of the N well is set to the floating potential,
Using a level detection circuit and a switch circuit,
By keeping the base potential lower than the N + diffusion / emitter potential, the parasitic NPN bipolar transistor is disabled.

FIG. 4 shows a P-well / base potential and an N + diffusion / emitter potential controlled by a level detection circuit, a switch circuit, and an external negative booster circuit used in the negative booster circuit according to the second embodiment. FIG. 3 is a circuit diagram showing a part of a negative booster circuit. FIG. 5 is a circuit diagram specifically configuring the level detection circuit of FIG. 4, and FIG. 6 is a circuit diagram specifically configuring the switch circuit of FIG. In FIG. 4, M401,
M402 is a triple well structure N-channel MOS
The transistors Q401 and Q402 are NPN bipolar transistors parasitic to the N-channel MOS transistor, CLKA and CLKB are boosting clocks,
Reference numerals 1 and 405 denote AND-type circuits which receive clocks CLKA and CLKB and an output from the level detection circuit 402 and output the nodes N402 and N407, respectively.
Is a level detection circuit that outputs an L level or an H level to the node N405 by detecting the potential of the node N406. An external circuit 403 applies a constant negative voltage to the P wells of the N channel MOS transistors M401 and M402. The negative booster circuit 404 compares the potentials of the node N406 and the node N409, and as a result of the comparison, a switch circuit connecting one of the nodes N406 and N409 to the node N403, and C401 and C402 output the clocks CLKA and CLKB, respectively. Synchronously, nodes N401, N
This is a capacitor for increasing or decreasing the potential of 404. In FIG.
501, 502, 503 are inverters, M501, M
502 is an N-channel MOS transistor, M503,
M504 is a P-channel MOS transistor. 6, 601 is a level difference detection circuit, and 602 is
Inverter with voltage level conversion, 603 is a buffer with voltage level conversion, M601 and M602 are N-channel MOS transistors, and 605 and 606 are inputs for inputting the potential of a subsequent boosting node and an external negative boosting circuit to the switch circuit. A terminal 604 is an output of the switch circuit.

The boosting operation of disabling the parasitic NPN bipolar transistor Q401 in the negative boosting circuit according to the second embodiment thus configured will be described below. First, the level detection circuit of FIG. 5 will be described. The level detection circuit shown in FIG. 5 applies a negative voltage to be monitored to the VBB terminal, that is, the potential of the P-well this time, and uses the threshold voltage of the N-channel MOS transistor as a reference value.
The negative voltage can be detected at the constant value. In FIG. 5, N-channel MOS transistors M501 and M502 are connected in series.
As a result, N-channel MOS transistors M501, M501
When a negative voltage lower than VSS by twice the threshold value of 502 is input, the input of the inverter 501 changes from VDD to a negative voltage, the output of the inverter 501 changes to the H level, and the output of the inverters 502 and 503 is controlled by the inverters 502 and 503. The terminal LV changes from the L level to the H level.

Next, the switch circuit of FIG. 6 will be described. The level difference detection circuit 601 compares the potential of the boosting node at the subsequent stage of the negative boosting circuit input to the node N601 with the output potential of the external negative boosting circuit input to the node N602, and changes the potential of the node N601 to the node N602. Is lower than the potential by a predetermined set value, the node N603
Output a level, and if not, node N
A signal 603 is output at the H level. Therefore, when the potential of the subsequent boosting node is lower than the output potential of the external negative boosting circuit by a predetermined set value, N603 becomes L level, and inverter 602 with voltage level conversion
N channel MOS transistor M602 is
F, while the N-channel MOS transistor M601
Is turned on by the buffer with voltage level conversion 603, so that the output 604 becomes the potential of the subsequent boosting node. That is, the input 605 is connected to the output 604. When the potential of the subsequent boosting node is not lower than the output potential of the external negative boosting circuit by a predetermined set value, N60
3 goes to the H level, and the N-channel MOS transistor M
Since the 601 is turned off and the N-channel MOS transistor M602 is turned on, the output 604 becomes the potential of the external negative booster circuit. That is, input 606 is output 6
04 will be connected.

Next, a negative boosting operation using the level detection circuit 402 and the switch circuits 404 and 406 in FIG. 4 will be described, particularly with respect to the N-channel MOS transistor M401. First, at the start of the operation of the negative booster circuit, the node N409 and the node N406 have substantially the same potential, so the switch circuit 404 connects the node N406 to the node N403. Then, the external negative booster circuit 403
However, when a sufficient negative voltage has not yet been generated, the potential of the node N406 is input to the level detection circuit 402, so that the output of the level detection circuit 402 to the node N405 becomes L level, and the node of the AND type circuit 401 N
The output to 402 is at the L level regardless of the level of the clock CLKA, and the negative boosting operation is not started. next,
When the external negative boosting circuit 403 generates a negative voltage larger than the set value set by the level detecting circuit 402, the level detecting circuit 402 detects that, and the node N405
Output to H level. Thus, the output of the AND-type circuit 401 to the node N402 is the clock CLKA.
And the negative boosting operation is started.
At this time, since the negative boosting operation has just been started, the potential of the node N406 is lower than that of the node N409, and the switch circuit 404 includes the node N406 and the node N406.
403 remains connected. At this time, since the P well / base potential is lower than the N + diffusion / emitter potential, the base current Ib does not flow.
No collector current Ie from the ep-N well / collector to the N + diffusion / emitter is generated.

External negative booster circuit 403 to node N403
The negative voltage to be input to the transistor has no steady current load if the parasitic NPN bipolar transistor Q401 does not operate. Therefore, for example, the negative voltage is multi-stage compared to a negative booster circuit of an N-channel MOS transistor, but is constituted by a P-channel MOS transistor. It is possible to supply a negative voltage by the charge pump type negative booster circuit. Since the current load is small, the capacity and the size of the transistor may be small although the number of stages is large.

When the negative boosting circuit becomes stable, that is, when the potential of the boosting node N409 in the subsequent stage becomes lower than the potential of the output node N406 of the external negative boosting circuit by a predetermined set value, the switch circuit 404 is turned on. , Node N4
09 to connect node N403,
The input to the P-well switches from the external negative booster circuit to the booster node at the subsequent stage. At this time, since the negative boosting circuit is stable, the potential of the subsequent boosting node N409 is lower than that of the preceding node N401, and the base current Ib does not flow.
No collector current Ie is generated.

As described above, the negative booster circuit according to the second embodiment includes the level detection circuit 402 for maintaining the P well / base potential lower than the N + diffusion / emitter potential, and the switch circuits 404 and 406. The parasitic NPN bipolar transistors Q401 and Q402 are invalidated, and an efficient negative booster circuit can be realized.

In the negative booster circuit according to the second embodiment,
Although the level detection circuit 402 is specifically configured in FIG. 5, this is merely an example. For example, when the negative voltage to be monitored falls below a set value, the output changes from L level to H level. Any level detection circuit may be used as long as the same effect is obtained.

Further, in the negative booster circuit according to the second embodiment,
Although the switch circuits 404 and 406 are specifically configured in FIG. 6, this is an example, and the present embodiment 2
As long as the switch circuit has the same function as that shown in FIG. 6, the switch circuit is not limited to the circuit configuration of FIG. 6, and the same effect can be obtained.

(Embodiment 3) The negative booster circuit according to Embodiment 3 of the present invention uses a clock modulation circuit to set the P well / base potential to N + as in Embodiment 2.
It keeps it below the diffusion / emitter potential and disables the parasitic NPN bipolar transistor.

FIG. 7 is a diagram showing a charge pump type negative booster circuit using a clock modulation circuit, and input and output waveforms to the clock modulation circuit. In FIG. 7, CLK
A and CLKB are boosting clocks having the same frequency and opposite phases, and 701 and 702 are clocks CLKA and CLKB respectively as input waveforms, and output waveforms to nodes N702 and N706 having the same waveform as the input waveform. A clock modulation circuit C701, C702 that generates an output waveform to nodes N704 and N708 that rises later and falls earlier by a predetermined time compared to clocks CLKA and CLKB, and that has a shorter H-level temporal section; ,
C703 and C704 are clock modulation circuits 701 and 70
2 in synchronization with the output from nodes N701 and N7, respectively.
03, a capacitor for increasing or decreasing the potential of N705 and N707, M
Reference numerals 701 and M702 denote N-channel MOS transistors having a triple well structure, and Q701 and Q702 denote NPN bipolar transistors which are parasitic in the triple well structure.

The negative boosting operation for disabling the parasitic NPN bipolar transistors Q701 and Q702 in the negative boosting circuit according to the third embodiment, which is configured as described above,
This will be described below. First, nodes N702 and N706 having the same waveform as the clocks CLKA and CLKB are connected to the capacitors C701,
N channel MOS transistor M70 via C703
1. The N + diffusion / nodes N701 and N705 of M702 are pumped to perform a boosting operation. At this time, the node N7 modulated by the clock modulation circuits 701 and 702
04, using the output waveform of N708, the capacitance C702,
By pumping C704, the N-channel MO
The potential of the P well of the S transistors M701 and M702 is reduced to a negative voltage. During the section in which the P-wells of the N-channel MOS transistors M701 and M702 are reduced to a negative voltage by this negative boosting operation, the nodes N702 and N7
06 changes from the H level to the L level, and the nodes N701 and N701
705 is reduced to a negative voltage. Therefore, the potential of the P well becomes a negative potential earlier than the N + diffusion region in timing, so that no base current flows from the base to the emitter, the parasitic NPN bipolar transistors Q701 and Q702 do not become active, and efficient boosting is performed. Operation is obtained.

As described above, the negative booster circuit according to the third embodiment keeps the P-well / base potential lower than the N + diffusion / emitter potential, so that the clock modulation circuits 701, 70
2, the parasitic NPN bipolar transistors Q701 and Q702 are disabled, and an efficient negative booster circuit can be realized.

(Embodiment 4) The negative booster circuit according to the fourth embodiment of the present invention connects capacitors in series and divides the voltage applied to one capacitor so as to withstand the high voltage generated by the negative booster circuit. By providing a circuit that resets the potential between the capacitors at the start of the boosting operation when the voltage is increased,
This enables effective boosting operation.

In the present invention, the node N102 is grounded to VSS during standby by using a circuit for resetting the intermediate node as indicated by 103 in FIG. The path to VSS uses a P-channel MOS transistor, and inputs a negative voltage to the gate at the time of reset to operate the P-channel MOS transistor. As the negative voltage used at the time of resetting, a P-channel MOS cross-coupled negative voltage generating circuit as shown in FIG. 8 is used. In addition, although there is a method of generating a negative voltage, the negative voltage used here is for resetting the potential of the intermediate node by a P-channel MOS transistor.
It suffices if there is a negative voltage slightly larger than the threshold value of the transistor, and there is no need for continuous supply. The reset means 1801 of the prior art shown in FIG. 18 resets the middle of the booster circuit, and does not reset the intermediate node where the capacitors are connected in series. By connecting to a node, it may be used as a reset circuit of an intermediate node.

As described above, the negative booster circuit according to the fourth embodiment includes the reset circuit of the intermediate node, so that after the boosting operation is stopped once, the charges accumulated between the capacitors connected in series are reset by the reset circuit. When erasing and restarting the boosting operation, it is possible to realize an efficient negative boosting circuit capable of shortening the startup time.

(Embodiment 5) A nonvolatile semiconductor memory device according to Embodiment 5 of the present invention is a flash EEPROM.
A negative booster circuit is built in a nonvolatile semiconductor memory device such as M. FIG. 9 is a diagram showing a nonvolatile semiconductor memory device having a built-in negative booster circuit. As described above, the nonvolatile semiconductor memory device according to the fifth embodiment includes the negative booster circuit in the device, thereby enabling the operation of reading, erasing, and writing of the flash EEPROM with a single power supply, and achieving high efficiency. It is possible to realize a nonvolatile semiconductor memory device that can be reduced in size.

Sixth Embodiment A semiconductor circuit device according to a sixth embodiment of the present invention has a built-in negative booster circuit in the semiconductor circuit device. FIG. 10 shows the flash EEP
FIG. 2 is a diagram illustrating a semiconductor circuit device having a built-in ROM core. As described above, the semiconductor circuit device according to the sixth embodiment incorporates the negative booster circuit, thereby enabling the flash EEPROM PR.
The negative voltage can be used for purposes other than the OM / core erase and write operations, and there is no need to input a negative voltage from outside the chip, and operation with a single power supply is possible.
Cost reduction can be realized.

[0054]

According to the negative booster circuit of the first aspect, in the negative booster circuit composed of an N-channel MOS transistor having a triple well structure, a triple well structure having the P-well of the N-channel MOS transistor as a base terminal is provided. There is an effect that the effect of the parasitic NPN bipolar transistor peculiar to the semiconductor MOS process can be suppressed and a highly efficient boosting operation can be realized. Also, since the substrate bias effect, which is a problem when handling a negative voltage with a P-channel MOS transistor, does not occur with an N-channel MOS transistor,
The negative booster circuit composed of the N-channel MOS transistor is different from the negative booster circuit of the P-channel MOS transistor.
This has the effect of realizing a negative booster circuit capable of high efficiency boosting capability and low voltage operation.

According to the negative booster circuit of the second aspect, the first aspect is as follows.
5. The negative booster circuit according to claim 1, wherein:
By setting the potential of the Deep-N well to the floating potential, the effect of the NPN bipolar transistor parasitic on the triple well structure is suppressed, and there is an effect that high-efficiency and low-voltage operation can be performed.

According to the third aspect of the present invention, there is provided a negative booster circuit.
In the negative booster circuit described in (1), by applying a negative voltage to the P well, the effect of the NPN bipolar transistor parasitic on the triple well structure is suppressed, and there is an effect that high efficiency and low voltage operation are possible.

According to the negative booster circuit of claim 4, according to claim 3 of the present invention.
In the negative booster circuit described in (1), a negative voltage is externally applied to the P well, and when the P well becomes a specific negative voltage, this is detected, and a boosting clock of the negative booster circuit is supplied. And the potential of the P-well at the preceding stage of the negative boosting circuit is compared with the potential of the boosting node at the subsequent stage, and the potential at the boosting node at the subsequent stage is lower by a specific potential than the potential at the P-well at the preceding stage. When the P-well is provided with a switch circuit that switches so as to apply the negative voltage of the subsequent boosting node instead of applying the negative voltage from the outside, the potential of the P-well is constantly changed. D
The potential of the NPN can be set lower than the potential of the deep N-well, so that the NPN parasitic on the triple well structure can be reduced.
Since the base current of the bipolar transistor is not generated, the NPN bipolar transistor can be invalidated, resulting in high efficiency and low voltage operation.

According to the negative booster circuit of claim 5, claim 3 is
The clock booster circuit according to claim 1, further comprising a clock modulator that outputs a clock signal obtained by modulating an input clock signal by shortening an H-level time interval of the signal by a predetermined time. Inputting a clock signal for use and pumping the P-well to a negative voltage with the modulated clock signal, the potential of the P-well can be constantly made lower than the potential of the Deep-N well, whereby the triple Since the base current of the NPN bipolar transistor that is parasitic on the well structure is not generated, the NPN bipolar transistor can be made invalid, which has an effect of increasing the efficiency and operating at a low voltage.

According to the negative booster circuit of claim 6, claim 1 is
6. The negative booster circuit according to claim 5, wherein said negative booster circuit is connected in series between nodes having a potential exceeding a withstand voltage of a capacitive element used for boosting operation. By providing a reset circuit that sets an intermediate node between the intermediate nodes to a predetermined initial potential when the circuit is not operating, the intermediate nodes of the series-connected capacitive elements can be reset even when the negative booster circuit is restarted. Since no charge is accumulated in the intermediate node, the time required for stabilizing the boosting operation after the restart is reduced, a boosted voltage can be obtained at high speed, and the power consumption at the time of recovery is reduced.

According to a seventh aspect of the present invention, a single power supply is provided by incorporating the negative booster circuit according to any one of the first to sixth aspects in the nonvolatile semiconductor memory device. In this case, a high voltage can be obtained, and since a plurality of power supplies are not required outside the chip, there is an effect that the cost can be reduced.

According to the semiconductor circuit device of the eighth aspect, by incorporating the negative booster circuit according to any one of the first to sixth aspects in the semiconductor circuit device, a high voltage can be generated with a single power supply. Since there is no need for a plurality of power supplies outside the chip, the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a negative booster circuit having an N-channel MOS transistor configuration according to the present invention.

FIG. 2 is a diagram showing an N-channel MOS transistor having a triple well structure and a well structure according to the first embodiment of the present invention;

FIG. 3 is an N-channel MO according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram showing a charge pump type negative booster circuit having an S transistor configuration.

FIG. 4 is a diagram illustrating a negative booster circuit according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a level detection circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a switch circuit according to a second embodiment of the present invention.

FIGS. 7A and 7B are diagrams illustrating a negative booster circuit using the clock modulation circuit according to the third embodiment of the present invention (FIG. 7A) and input / output waveforms to the clock modulation circuit (FIG.

FIG. 8 shows a P-channel MO according to the fourth embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an S cross-coupled negative voltage generation circuit.

FIG. 9 is a diagram illustrating a flash EEPROM including a negative booster circuit according to a fifth embodiment of the present invention;

FIG. 10 is a diagram illustrating a system LSI including a negative booster circuit according to a sixth embodiment of the present invention;

FIG. 11 shows the structure of a flash EEPROM (FIG. 11A)
FIG. 4 is a diagram showing a relationship between voltages necessary for reading, erasing, and writing (FIG. 13B).

FIG. 12 is a diagram showing a conventional charge pump type negative booster circuit having a diode configuration (FIG. 12A) and clock, node, and output waveforms (FIG. 10B).

FIG. 13 is a diagram showing a conventional charge-pump type negative booster circuit composed of P-channel MOS transistors (FIG. 13A) and waveforms of clocks, nodes, and outputs (FIG. 13B).

FIGS. 14A and 14B are diagrams illustrating a substrate bias effect (FIGS. 13A and 13B) of a P-channel MOS transistor. FIGS.

FIG. 15 is a diagram showing a triple well structure and a parasitic NPN bipolar transistor.

FIG. 16 is a diagram showing a threshold cancellation type charge pump type negative booster circuit (FIG. (A)) and waveforms of respective clocks and nodes (FIG. (B)).

FIG. 17 is a circuit diagram showing a parasitic NPN bipolar transistor and an N-channel MOS transistor.

FIG. 18 is a circuit diagram showing a reset circuit of the booster circuit.

[Explanation of symbols]

 Reference Signs List 101 Negative booster circuit 102 P-well potential control unit 103 Reset circuit 104, 105 Boosted clock control signal CLK1, CLK2, CLK3, CLK4 Clock 201 P-type silicon wafer 202 Deep-N well 203 P-well Q201 Parasitic NPN bipolar transistor 208 Floating potential P-well terminal 209 Deep-N-well terminal of floating potential CLKA, CLKB Clock 401, 405 AND-type circuit 402 Level detection circuit 403 External negative booster circuit 404, 406 Switch circuit 501, 502, 503 Inverter M501, M502 N-channel MOS transistor 601 Level difference detection circuit 602 Inverter with voltage level conversion 603 Buffer with voltage level conversion 604 Output of switch circuit 605, 606 Switch Input terminal of the road 701 and 702 the clock modulation circuit Q701, Q 702 NPN bipolar transistor

Continuing from the front page (72) Inventor Ikuo Fuchigami 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yoichi Nishida 1006 Odaka Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.F-term ( Reference) 5B025 AD10 AE05 AE06 5H730 AA14 BB02 BB05 DD04

Claims (8)

[Claims] 1. Negative booster for increasing / decreasing potentials of a gate, a source, and a drain of an N-channel MOS transistor formed in a P-well having a triple well structure using a clock via a capacitor to generate a negative voltage. In the circuit, the P-well has a floating potential, or the P-well has a predetermined potential. 2. The negative booster circuit according to claim 1, wherein the potential of the P well and the potential of the Deep-N well are floating potentials. 3. The negative booster circuit according to claim 1, wherein a negative voltage is applied to said P well. 4. The negative booster circuit according to claim 3, wherein a negative voltage is externally applied to said P well, and when said P well reaches a specific negative voltage, said negative voltage is detected. A level detection circuit for supplying a boosting clock of the booster circuit, and a potential of a P-well at a preceding stage of the negative booster circuit is compared with a potential of a boosting node at a subsequent stage. A switch circuit that switches to apply a negative voltage of the boosting node of the subsequent stage to the P-well instead of applying the external negative voltage when the potential becomes lower than a specific potential. Characteristic negative booster circuit. 5. The negative boosting circuit according to claim 3, wherein the clock modulation circuit outputs a clock signal obtained by modulating an input clock signal by shortening an H-level time interval of the signal by a predetermined time. Inputting a boosting clock signal to the clock modulation circuit;
A negative booster circuit, wherein the P-well is pumped to a negative voltage by a modulated clock signal. 6. The negative booster circuit according to claim 1, wherein said negative booster circuit is arranged between nodes to which a potential exceeding a withstand voltage of a capacitive element used for boosting operation is applied. And a reset circuit for setting an intermediate node between the series-connected capacitive elements to a predetermined initial potential when the circuit is not operating. 7. A nonvolatile semiconductor memory device comprising the negative booster circuit according to claim 1. 8. A semiconductor circuit device comprising the negative booster circuit according to claim 1.