JP2001043688A - Flash memory circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] The operating speed of a flash memory has been reduced due to a delay caused by a specific read operation, the operating speed of a high-voltage transistor of a decoder circuit, and the like. A clock control circuit receives an external clock signal and a trigger signal, and generates a plurality of time-delay trigger signals each delayed by at least one clock period from the trigger signal; A clock trigger signal generating circuit for receiving the trigger signal and generating a clock trigger signal; and a clock buffer circuit for receiving the external clock signal and the clock trigger signal and generating an internal clock signal. A gate voltage providing circuit for receiving a plurality of address signals and a gate voltage substantially separated from the low voltage portion; and providing the gate voltage to the gate voltage providing circuit for use as an output of the gate voltage providing circuit. A gate voltage selection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present application claims "clock control and decoder circuits and high voltage comparators" filed July 29, 1999, which is hereby incorporated by reference in its entirety.
Claim the benefit of a US provisional patent application titled

[0002]

The present invention relates generally to semiconductor devices, and more particularly, to a clock control circuit for controlling an internal clock signal of a semiconductor device, particularly a nonvolatile semiconductor memory device such as a flash memory device. The invention also relates generally to semiconductor devices, and more particularly, to semiconductor devices, and more particularly, to decoder circuits for non-volatile semiconductor storage devices such as flash memory devices.

[0003]

2. Description of the Related Art Generally, a flash memory device includes an address sequencer, a row and column decoder, a sense amplifier, a write amplifier, and a memory cell array. An example of a flash memory device is described in US Pat.
No. 490,107, the disclosure of which is incorporated herein by reference. . The memory cell array includes a plurality of memory cells arranged in rows (rows) and columns (columns). Each memory cell can hold one bit of information.
Columns of memory cells in a memory cell array are typically coupled to bit lines. The column decoder selects a bit line together with the address sequencer. Similarly, memory cells arranged in a row of a memory cell array are usually coupled to a word line. The row decoder and the address sequencer select a word line. The row and column decoders and the address sequencer together select individual memory cells or groups of memory cells.

[0004] Memory cells in a memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W / A) applies a set of predetermined voltages to store information in a selected memory cell. This operation is called a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cell enables the sense amplifier (S / A) to determine and retrieve information. This operation is called a read operation.

[0005]

The speed of read and write operations is often increased to implement high performance flash memory devices. One way to increase the speed of a read operation is synchronization. Synchronizing the read operation with an external clock improves the speed of the read operation. However, under certain conditions, performing a particular read operation takes longer than other read operations, which may result in asynchronous conditions.

For example, when word line switching occurs,
That is, a delay is often experienced when reading the first memory cell along the word line after reading the last memory cell along the previous word line in the memory cell. This delay is often greater than one clock period of the external clock, thus disrupting synchronization of the read operation to the external clock. As a result, an error occurs and wrong data is read from the selected memory cell.

In addition, the decoder circuit needs to supply a relatively high program voltage V _pp to the memory cell during a write or program operation. Decoder circuit, since it must handle the V _pp, the decoder circuit must use a high-voltage transistor. However, high voltage transistors have a slower operation than low voltage transistors because they have a thicker oxide layer.

Therefore, it is advantageous to use lower voltage transistors to increase the speed of program and read operations. Since the decoder circuit requires a high voltage transistor to process the V _pp, it is beneficial to separate the low-voltage part a high voltage portion of the decoder circuit. If most of the logic switching is handled in the low voltage portion of the decoder circuit, a flash memory device with increased capacity for fast read and program operations would be obtained.

[0009]

SUMMARY OF THE INVENTION The present invention provides a clock control circuit for receiving an external clock signal and generating an internal clock signal, a synchronous flash memory device using the clock control circuit, and an internal clock from the external clock signal. A method for generating a clock signal is provided. The generated internal clock signal blocks (blocks) a selected number of external clock cycles. The start of the external clock cycle block is triggered by a trigger signal.

[0010] The shift register assembly is used in a control clock circuit to receive an external clock and a trigger signal. In a shift register assembly, shift registers are coupled in series. A first shift register coupled in series receives the trigger signal as an input and provides it to the second shift register delayed by one external clock period. The second shift register is likewise
Delay the input by one external clock period and provide it to a third shift register, and so on. Therefore, each shift register outputs a time delay trigger signal. The time delay trigger signal output by any one shift register is temporally shifted by one or more external clock periods from the time delay trigger signals from all other shift registers.

The time delay trigger signal thus generated is combined with the clock reject signal to generate a clock trigger signal. The clock trigger signal is input to the clock buffer together with the external clock signal. The timing and duration of the clock trigger signal determine the start and stop of external clock cycle blocking. A second embodiment of the present invention is a method for generating an internal clock signal. In this embodiment, a clock control circuit is used,
An external clock signal is received and an internal clock signal is generated that blocks a portion of the external clock signal. The clock control circuit is used in any semiconductor device.

A third embodiment of the present invention is a synchronous flash memory device having a clock control circuit. In a conventional flash memory device, data reading and writing are performed asynchronously. Systems in which flash memory devices are used operate at high clock frequencies.
Synchronous flash memory devices are used to meet the system requirements of systems where the clock frequency is constantly increasing. Flash memory devices use a clock control circuit that takes into account the fact that some data sensing takes longer than others. If necessary, by providing additional delay, the internal clock generated from the external clock by the clock control circuit solves the problem of data sensing delay.

[0013] The present invention also provides a decoder circuit. The decoder circuit includes a gate voltage providing circuit and a gate voltage selecting circuit. The gate voltage providing circuit receives a plurality of address signals and a gate voltage, and provides a gate voltage as an output. The gate voltage providing circuit provides the gate voltage output when the address signal indicates that a condition for generating the gate voltage output is satisfied. The gate voltage selection circuit provides a gate voltage to the gate voltage providing circuit for use as an output of the gate voltage providing circuit.

[0014]

DETAILED DESCRIPTION OF THE INVENTION Many additional features of the present invention are:
BRIEF DESCRIPTION OF THE DRAWINGS Although better understood by reference to the following detailed description, and more clearly appreciated when considered in conjunction with the accompanying drawings, in the drawings, like reference characters refer to the same parts throughout the drawings. I. Overview FIG. 1 shows an embodiment of a synchronous flash memory. The synchronous flash memory has a clock control circuit 2. The clock control circuit 2 receives the external clock signal 3 and combines the external clock signal with the trigger signal 5 to generate an internal clock signal 7. Address sequencer 4
Receives the internal clock signal 7, orders the address by an address, and generates an address signal synchronized with the internal clock signal 7. The address signal is provided to column buffer 6 and row buffer 8. The address signal is selectively corrected and supplied to a column decoder circuit 24 and a row decoder circuit 26. A column and row decoder circuit generates a column signal and a column decode signal,
A specific memory cell of the memory cell array 51 is selected for read and program operations.

Since each memory cell has a configuration similar to that of a MOS transistor, the memory cell has a source region and a drain region on a substrate. The memory cell has a floating gate and a control gate between the substrates.
Information is stored in the memory cell, ie, in the floating gate, by applying a set of predetermined voltages to the memory cell. Similarly, a set of predetermined voltages applied to a memory cell is used to read information contained in the memory cell.

The memory cell array 51 includes a plurality of memory cells 36, 38, 40, 42, 44, 46, 48 and 5
Contains 0. For easy understanding, the memory cell array 5
Only a subset of the memory cells in one is shown. Memory cells 36, 38, 44 and 46 are grouped into a first memory cell block, and memory cells 40, 42, 4
8 and 50 are grouped into a second memory cell block. Each memory cell block is coupled to a corresponding write amplifier and sense amplifier pair through a corresponding control transistor. That is, the drain of the control transistor is coupled to the write amplifier and the sense amplifier. For example, the first column control transistor 28 of the first memory cell block includes the write amplifier 16 and the sense amplifier 1
8.

Similarly, the drain of the memory cell is coupled to a control transistor. For example, the drains of the memory cells 36 and 44 are connected to the first column control transistor 2
8 sources. The gate of the control transistor is coupled to column decoder circuit 24 through a decode signal line. For example, first and third column control transistors 28 and 30 are coupled to a first column decode signal line 29 from column decoder circuit 24.

The write amplifier and sense amplifier pairs are also coupled to corresponding input / output buffers. FIG.
Then, the write amplifier 16 and the sense amplifier 18 connect the input /
Write amplifier 20 and sense amplifier 22 are coupled to output buffer 12 and are coupled to input / output buffer 14. Input / output buffers 12 and 14 are further coupled to external clock signal 3 and data input / output bus 1. Prior to the program operation, the program data arriving through the data input / output bus is connected to an external clock signal 3
And stored in the corresponding input / output buffer in synchronization with
Next, a program operation is executed in synchronization with internal clock signal 7 generated by clock control circuit 2.
During a read operation, data detected or sensed is sensed in synchronization with an internal clock signal 7 at a corresponding input / output.
Stored in the output buffer and then the external clock signal 3
And is sent out through the data input / output bus 1. Input and output transfers to and from the input / output buffers can be performed simultaneously. Such synchronous transfer maximizes both read and program operating speeds. However, each read and program operation depends on the internal clock signal 7 generated by the clock control circuit 2.

II. Clock Control Circuit As described above in connection with FIG. 1, in order to perform a read operation, a predetermined voltage level must be applied to the appropriate memory cell. These read voltages are applied through word and bit lines. Word and bit lines inherently incorporate delays due to the resistance and capacitance of a given line. During a read operation, such a delay increases if there is a transition from the last set of memory cells on a word line to the next set of memory cells on the next word line, i.e., a boundary crossing or a word line switch.
When there is a word line switch, the read operation is performed from one memory cell of the same word line to another memory cell because the operation read voltage level must be removed from one word line and applied to another word line. Often takes twice as long as the read operation. In other words, data sensing is
It takes longer than one clock cycle of the external clock signal 3.

To provide additional time for data sensing, an internal clock signal 7 is generated by clock control circuit 2 of FIG. Internal clock signal 7 is synchronized to the external clock signal, but includes one or more blocked clock cycles. By supplying the internal clock signal 7 to the address sequencer, the data clocked on the data I / O bus is delayed as needed to allow for more time for data sensing.

The clock control circuit 2 includes a shift register
It includes an assembly 100, a clock trigger signal generator 23, and a clock buffer 25. The clock control circuit 2 generates an internal clock signal 7 by inputting the external clock signal 3 and the trigger signal 5. Shift register
The assembly 100 uses the external clock signal 3 to provide a delayed trigger signal to the clock trigger signal generator 23. The clock buffer generates the internal clock signal 7 by the input of the external clock signal 3 and the clock trigger signal 27 generated from the clock trigger signal generator 23.

FIG. 3 shows the shift register assembly 10.
0 shows an example. The trigger signal 5 is generated from the address sequencer shown in FIG. The address sequencer 4 generates a trigger signal 5 at each increment of the address. Trigger signal 5 is coupled to the input of inverter 102. The output of inverter 102 is coupled to the input of first shift register 104. The first time delay trigger signal L ₀ output from the first shift register 104 is:
It is coupled to the input of the second shift register 106. Second
The second time delay trigger signal L ₁ , which is the output of the shift register 106, is coupled to the input of the third shift register 108. The third shift register 108 generates a third time delayed trigger signal L ₂ as an output. Shift registers 104, 106 and 108 are each coupled to external clock 3. Although FIG. 3 shows only three shift registers in shift register assembly 100, the number of shift registers used can be varied and depends on the number of external clock cycles blocked from internal clock signal 7. I do.

Referring to FIG. 4, shift registers 104, 106, 108 in shift register assembly 100 of FIG.
Is shown. External clock signal 3 is coupled to the input of inverter 110. The output of inverter 110 is coupled to the gate of transistor 112. The drain of transistor 112 is coupled to the input of shift register 104. The source of transistor 112 is coupled to the input of inverter 114 and the output of inverter 116. Inverters 114 and 116 have a first latch. This first latch stores the input of the shift register in synchronization with the falling edge of the external clock signal 3.

The output of the inverter 114 and the inverter 11
The input of 6 is coupled to the drain of transistor 118. The gate of transistor 118 is coupled to external clock signal 3. The source of transistor 118 is coupled to the input of inverter 120 and the output of inverter 122. Inverters 120 and 122 include a second latch. This second latch stores the contents of the first latch in synchronization with the rising edge of the external clock signal 3. Output of inverter 120 and inverter 122
Are coupled together to provide a time delay trigger signal that is the output of the shift register.

The clock trigger signal generation circuit 130 receives the time delay trigger signals L ₀ , L ₁ and L ₂ generated from the shift register assembly 100. The clock trigger signal generation circuit 130 of FIG.
And a third two-input NOR gate 132, 134 and 136. The first time delay trigger signal L ₀ is
Is coupled to a first input of a two-input NOR gate 132. The second time delay trigger signal L ₁ is the second two-input N
The third time delay trigger signal L ₂ is coupled to the first input of the OR gate 134 and is coupled to the third two-input NOR gate 13.
6 is coupled to the first input.

The second inputs of the two-input NOR gates 132, 134 and 136 each have a clock blocking signal B
1, bound to B2 and B3. Clock blocking signal B
1, B2 and B3 are usually set before the manufacture of the synchronous flash memory device, but the clock blocking signal can be set during the operation of the synchronous flash memory device. Clock blocking signals B1, B2 and B3 determine the number of external clock cycles blocked from internal clock signal 7.

For example, when the first clock blocking signal B1 is set to low (low level) and the second and third clock blocking signals B2 and B3 are set to high (high level), one external clock is output. The cycle is blocked from the internal clock signal 7. If the first and second clock blocking signals B1 and B2 are set low and the third clock blocking signal B3 is set high, two external clock cycles are blocked from the internal clock signal 7.

FIG. 5 shows the clock trigger signal generation circuit 13.
0, three two-input NOR gates are shown, but the number of two-input NOR gates used depends on the internal clock signal 7
Only depends on the number of clock cycles to be blocked.
The clock trigger signal generation circuit 130 also has a three-input N
OR gate 138 is included. The outputs of the three two-input NOR gates are coupled to the inputs of a three-input NOR gate 138. The output of the three input NOR gate 138 is the output of the clock trigger signal generation circuit and is coupled to the input of clock buffer 140 of FIG. Each two-input NOR gate 13
The outputs of 2, 134 and 136 go high when both the corresponding clock block signal and the corresponding time delay trigger signal are low. This output of the three-input NOR gate, when combined with the external clock signal 3 at the clock buffer 140, is used to block one or more external clock signals.

In FIG. 6, the clock buffer 140 of FIG.
Is shown. The output of the clock trigger signal generation circuit of FIG. 5, which is the input of the clock buffer, is coupled to the input of the inverter 142. The output of inverter 142 is coupled to the drain of transistor 143. Transistor 1
The source of 43 is coupled to the input of inverter 146 and the output of inverter 148. Inverters 146 and 1
48 has a latch.

The external clock signal 3 is supplied to the inverter 144
And the first input of a two-input NAND gate 150. The output of the inverter 144 is the transistor 1
It is coupled to 43 gates. The output of the inverter 146 and the input of the inverter 148 are connected to the two-input NAND gate 15.
0 is coupled to the second input. Two-input NAND gate 1
The output of 50 is coupled to the input of inverter 152.

The clock trigger signal, which is the input to inverter 142, contains information on how many external clock cycles are blocked when generating internal clock signal 7. The output of inverter 142 is internal clock signal 7 with one or more external block cycles blocked. FIG.
FIG. 7 is a timing chart summarizing the operation of the clock control circuit 2 of FIGS. External clock signal timing diagram 8
2. trigger signal timing diagram 84, first time delay trigger signal 86, second time delay trigger signal 88, and
An internal clock signal timing diagram 90 is shown.

As can be seen from the timing diagram, when the trigger signal 5 goes high, the first time delay trigger signal L ₀
Goes low at the rising edge of the external clock signal 3. When the first time delay trigger signal L ₀ goes low, the second time delay trigger signal L ₁ goes low at the rising edge of the external clock signal 3. If both time delay signals L ₀ and L ₁ are implemented using clock blocking signals B 1 and B 2, two adjacent clock cycles are:
The external clock signal 3 is blocked from the internal clock signal 7. Thus, as illustrated in FIG. 7, the internal clock signal is similar or synchronous with the external clock signal. However, internal clock signal 7 includes two missing clock cycles. Eliminating clock cycles provides additional time for read or data sensing operations.

II (a). Data Timing Control Circuit The internal clock signal 7 provides an additional time or external clock signal for data sensing, ie, reading data from memory cells, through the use of the data timing control circuit. Provide more clock cycles to the sense amplifier. FIG. 8 illustrates the data timing control circuit 15 that generates the data sensing signal 63.
The data / timing control circuit 15 includes the extended data circuit 7
1 and the ATD circuit 9. The ATD circuit 9 is supplied with an A ₀ signal which is the least significant bit of the address signal from the address sequencer. The address sequencer generates a pulse that is the A ₀ signal at each address increment.

ATD circuit 9 is a P-channel transistor
91 and an N-channel transistor 95. P channel
The reference voltage V_ccContact
Connected to the source of the P-channel transistor 91.
An anti-93 is connected. The other end of the resistor 93 has N
Drain of channel transistor 91, capacitor 97
And the first input of a two-input NOR gate 99
Is connected. A ₀The signal is a P-channel transistor
To both gates of transistor 91 and N-channel transistor 95.
Supplied. These two transistors are both A₀Faith
Acts as an inverter that inverts the signal. For example, A₀Faith
Signal is high, P-channel transistor 91 is off.
And the N-channel transistor is turned on,
Creates a path to ground. Therefore, N-channel transistors
The first input of the NOR gate 99 connected to the
Pulled down to the ground, low. Conversely, A₀signal
Is low, the P-channel transistor 91 is turned on.
Since the N-channel transistor is turned off, V_ccWhat
Path. Therefore, the N-channel transistor 99
The first input of the NOR gate 99 connected to
V_ccThat is, it is pulled high.

The second input to the NOR gate 99 is A ₀
Coupled to the signal. At each low-to-high transition of the A ₀ signal, the ATD signal, which is the output of NOR gate 99, is low because the first input of NOR gate 99 is pulled to ground. During the transition from the high of A ₀ signal to a low, the first input of NOR gate 99 is pulled up gradually to a high. While the first input of NOR gate 99 thus transitions from low to high, both inputs to NOR gate 99 are low. Thus, the output of NOR gate 99 goes from high to low, producing a rising edge for the ATD signal. The ATD signal is high until the first input of NOR gate 99 transitions high. When the first input of NOR gate 99 goes high,
The ATD signal goes low, causing a falling edge of the ATD signal. The resistor 93 and the capacitor 97 generate the A
A time constant for determining the time period or pulse width of the TD signal is determined. The ATD signal provides one input to data timing control circuit 15. Another input to the data timing control circuit 15 is an extended data sense (E
XSNS) signal 70.

The EXSNS signal 70 corresponds to the extension data circuit 7
1 generated by The logic state of the EXSNS signal 70 depends on the extended reset data sense (RESETEX) signal 73 and the extended set data sense (SETEX) signal 75 which are inputs to the extended data circuit 71. FIG. 9 (a)
The set data sensing buffer exemplified in FIG.
The reset data sensing buffer illustrated in FIG. 9B generates a RESETEX signal 75. The set data sensing buffer and the reset data sensing buffer are identical except for the input to each buffer. The set data sensing buffer is supplied with an internal clock signal and a trigger (TRG) signal as inputs. On the other hand, the reset data sensing buffer has as inputs the internal clock signal and the _A0 signal.

In FIG. 9A, the internal clock (INTC
LK) signal is connected to a first input of NAND gate 901 and an input of inverter 903. When the INTCLK signal goes low, the transistor switch 905 turns on. When the transistor switch 905 is turned on, the output of the inverter 907 connected to the drain of the transistor switch 905 is transmitted to the inverters 909 and 911 through the source of the transistor switch 905. The input of inverter 907 is connected to the TRG signal. Inverters 909 and 911 invert the signal from the source of transistor switch 905 and provide this signal to a second input of NAND gate 901. Inverters 909 and 911 also serve to maintain a logic state at the second input of NAND gate 901, which is essentially a TRG signal. The output of NAND gate 901 is coupled to the input of inverter 913. The output of the inverter 913 is the SETEX signal 73. If the INTCLK signal is low and the output of NAND gate 901 is high, S
The ETEX signal 73 is low.

When the INTCLK signal goes high, the transistor switch 905 turns off and the NAND gate 9
The first input of 01 also goes high. Therefore, INTCLK
When the signal goes high, NAN, which is basically a TRG signal
The signal of the second input of the D gate 901 is “clock (cloc
ked) "to set the logic state of the SETEX signal 73. Therefore, before the INTCLK signal goes high, TRG
If the signal was low, the SETEX signal is also low. However, before the INTCLK signal goes high, TRG
If the signal was high, the SETEX signal will also be high. Therefore, when the TRG signal is high, the SETEX signal is
High at the rising edge of INTCLK and TRG
When the signal goes low, the SETEX signal goes low on the falling edge of INTCLK.

As described above, the reset data shown in FIG.
Data sensing buffer, except for the input to the buffer,
The same as the set data sensing buffer of FIG.
It is like. Therefore, the RESETEX signal 75 is
It is generated in the same way as the EX signal. But A₀signal
Affects the logic state of the RESETEX signal 75. Obedience
Therefore, when the INTCLK signal goes high, A₀The signal is
"Clocked", the logic state of the RESETEX signal 75
Set. A before the INTCLK signal goes high. ₀Faith
If the signal is low, the RESETEX signal is also low.
However, before the INTCLK signal goes high, A₀Signal
If high, the RESETEX signal goes high. Follow
A₀When the signal is high, the RESETEX signal is INT
It goes high on the rising edge of CLK and A₀Signal is low
RESETEX signal goes to the rising edge of INTCLK.
Goes low on falling edge.

Returning to FIG. 8, the RESETEX signal 75 and the SETEX signal 73 are supplied as inputs to the extended data circuit 71. SETEX signal 73 is coupled to the gate of first transistor 77 and the input of inverter 83. The output of the inverter 83 is the second transistor 81
To the gate. When the SETEX signal goes high, the first transistor 77 turns on and the second transistor 81 turns off due to the intervening inverter 83. The source of first transistor 77 is coupled to ground, and the drain of first transistor 77 is connected to inverter 8
5 and 87. EXSNS signal 70 is the output of inverter 87. Inverters 85 and 87
Acts as a latch and maintains the logic state of the drain of the first transistor 77. Thus, when the first transistor is turned on, a path to ground is formed and EXSN
The S signal 70 goes high.

Conversely, when the SETEX signal goes low, the first transistor 77 turns off and the second transistor 81 turns on. The RESETEX signal 73 is the third signal.
Is connected to the gate of the transistor 79. This third transistor 79 has a source coupled to ground and a drain coupled to the source of second transistor 81. The drain of the second transistor is coupled to inverters 85 and 87 and the EXSNS signal 70
Also serves as a second signal source. If the SETEX signal 75 is low, and if the RESETEX signal 73 is high, a path to ground is formed. Thus, EXSNS signal 70 is pulled low to ground.

The EXSNS signal 70 is supplied to the data / timing control circuit 15 and the ATD signal from the ATD circuit 9 is output.
Combined with the signal to produce the data sense signal 63. In FIG. 8, the transistors of the data timing control circuit 15 operate in a manner similar to the transistors of the ATD circuit 9 previously described. Therefore, the transistors 101a and 101b receiving the ATD signal and the transistor 105a
And 105b act as inverters. Resistance 10
3a and 107a are also capacitors 103b and 107b
And 107c operate similarly to resistor 93 and capacitor 97 of ATD circuit 9, i.e., produce an RC delay or time constant. However, with the addition of capacitor 107c, the delay experienced at the input of NOR gate 109b is longer than the delay experienced at the input of NOR gate 109a. However, such a delay becomes significant only when EXSNS signal 70 goes high.

When the EXSNS signal 70 is high and the other input of the NOR gate 109b is low, the NOR gate 1
The output of 09b goes high. If the input of NOR gate 109b is low, the input to NOR gate 109a is also low due to the similarity of the components coupled to NOR gate 109a and the components. NOR gate 10
If the input at 9a is low, the output of NOR gate 109a will be high. NO which is also the input of NOR gate 111
When the outputs of both R gates 109a and 109b go high, SNS signal 63 also goes high.

Similarly, when EXSNS signal 70 goes low, the output of NOR gate 109b goes low. NOR
Since the input to gate 109a is also low, the output of NOR gate 109a goes high. If the outputs of both NOR gates 109a and 109b, which are also inputs to NOR gate 111, are low, SNS signal 63 will also be low.

[0045] In Figure 10, EXSNS signal, TRG signal, A ₀ signal, ATD signal, SNS signal, and a timing diagram of internal and external clock signals for operation of the interaction with data timing control circuit 15 of the signal For example. Since the internal clock signal to provide input to the address sequencer, A ₀ signal is dependent on the state of the INTCLK signal. Therefore, for each rising edge of the INTCLK signal, A ₀ signal is switched, i.e., changes state. ATD signal from the ATD circuit 9 that depends on the state of A ₀ signal is generated on the falling edge of the A ₀ signal signal. The ATD signal indicates the start of a transition from one address to another. Since the SNS signal 63 functions to control the sense amplifier, the period TS1 and the period TS1
During 2, the sense amplifier is triggered to read the memory cell on the rising edge of the SNS signal. As described in connection with FIG. 8, the duration of the periods TS1 and TS2 is determined by the resistance 107a and the capacitors 107b and 10b.
7c. Therefore, if more time is required for data sensing, additional capacitance is added,
Extend the duration of periods TS1 and TS2.

The sense amplifier is triggered to stop reading the memory cell at the falling edge of the SNS signal. In the case of the standard read operation, it is assumed that two external clock cycles are provided to the sense amplifier to read the memory cell. In FIG. 10, if the TRG signal is high on the rising edge of the external clock signal, the next internal clock cycle is skipped. FIG.
When the TRG signal is high, boundary crossing occurs, as described above in connection with. When a boundary intersection occurs, the sense amplifier needs additional time to read data. INTCLK signal, because it is supplied to the address sequencer for controlling the increment of the address, A ₀ signal does not change until the rising edge of the INTCLK signal. If the A ₀ signal does not change, A
No TD signal is generated. ATD signal is not generated and A ₀
If the signal does not change, the SNS signal remains high and the sense amplifier continues to read data from the memory cells. Thus, delaying the internal clock signal by an extra external clock cycle provides the sense amplifier with additional time to perform a read operation.

III. Decoder Circuit As illustrated above in connection with FIG.
And row decoder 8 generates a column signal sequence and a column decode signal based on the address signal generated by address sequencer 4. One embodiment of the decoder circuit of the present invention in FIG. 11 in which the high voltage and low voltage portions are separated is used as the column decoder circuit 24 or the row decoder circuit 26 illustrated in FIG. Address signals A ₀ . . _An-1 is provided as an input from the row buffer 8 or the column buffer 6, as shown in FIG. In FIG. 11, the address selection circuit 162 outputs the address signals A ₀ . . An _n-1 is applied to each gate voltage providing circuit 240a,
Invert zero or more of these signals as needed before providing them to 240b, 240c and 240d. Address signals A ₀ . . When A _n-1 indicates the selection of an individual gate voltage providing circuit, zero or more address signals A ₀ . .
_An-1 is inverted to apply a logic "high" (high level "H") to all signal inputs for that particular gate voltage providing circuit.

For example, when all the address signals A ₀ . . A
_If the gate voltage providing circuit 240a is selected when _n-1 is a logic "low" (low level "L"), all signals 164 provided to the gate voltage providing circuit 240a,
166, 168 and 170 are the address selection circuits 16
2 and all signals 164, 166, 168 and 17 applied to the input of the gate voltage providing circuit 240a.
0 is a logic "high" when applied. In another example,
All address signals A ₀ . . If the gate voltage providing circuit 240d is selected when A _n-1 is logic “high”, all signals 188, 190, 192 and 194 provided to the gate voltage providing circuit 240d The gate voltage providing circuit 240
All signals 188, 190, 19 applied to the input of d
2 and 194 are logic "high" when applied.

FIGS. 12A and 12B show conventional circuits used as the gate voltage selection circuit 200 and the gate voltage supply circuits 240a to 240d of the address decoder circuit of FIG. 11, respectively. FIG. 12A shows a gate voltage selection circuit 200 that outputs a voltage output V _ppi 203.
Is shown. The voltage level of the voltage output V _ppi 203 is either V _cc or V _pp and depends on the read signal R.
The read signal R is generated by a system using a synchronous flash memory device and provided to the synchronous flash memory device when a read operation is required.

The read signal R is a depletion type N channel.
It is coupled to the gate of channel transistor 202. Dep
Drain of the relation type N-channel transistor 202
Is V _ccAnd a depletion-type N-channel transformer.
The source of the resistor 202 is a voltage output of 203V._ppiBound to
It is. The read signal R is also supplied to the input of the inverter 210.
Be combined. The output of inverter 210 is a P-channel transistor.
It is coupled to the gate of transistor 208. P channel
The source of transistor 208 is coupled to common 209
You. The drain of the P-channel transistor 208
The gate of the N-channel transistor 204
Is combined with Enhancement type N-channel transistor
The drain of the star 204 is V_ppIs combined with

The drain of P-channel transistor 208 is also coupled to the source and gate of depletion type N-channel transistor 206. The gate of enhancement N-channel transistor 204 is coupled to the drain of P-channel transistor 208. The enhancement N-channel transistor 204 is a high voltage transistor having a thick oxide layer and a low conductivity due to the need to handle a high gate program voltage _Vpp .

The read signal R goes high during a read operation. When the read signal R is high, the N-channel transistor 202 turns on and the voltage at the source of the transistor 202 approaches _Vcc . Therefore, the voltage output V _ppi 203
Approaches _Vcc . When the read signal R is high, the output of the inverter 210 goes low. When the output of the inverter 210 goes low, the P-channel transistor turns on and the enhancement N-channel transistor 206
A potential close to the ground is supplied to the gate and the source. Since the potential close to the ground is also applied to the gate of the depletion type N-channel transistor 204 and turns it off,
Providing V _pp to the voltage output V _ppi 203 is prevented.

The read signal R is low during the program operation.
, The depletion type N-channel transistor 2
02 is off and V_ccIs the voltage output V_ppiProvided to 203
Is prevented. When the read signal R is low,
Since the output of inverter 210 goes high, the P-channel
The transistor 208 is turned off. Enhancement type N
Since the channel transistor 204 is turned on, the program
Ram drain voltage V _ppIs the voltage output V_ppiProvided to 203
Is done.

Since each gate voltage providing circuit provides a necessary voltage to each column control transistor or each row of a memory cell, both the column decoder circuit 24 and the row decoder circuit 26 have the same configuration as that of FIG. A plurality of gate voltage providing circuits 220 are provided for each output. In the gate voltage supply circuit 220, the address selection circuit 162
Is input to the NAND gate 222 as an input signal. The output of NAND gate 222 is coupled to the drain of N-channel transistor 224 and the gate of N-channel transistor 230. The gate of N-channel transistor 224 is coupled to _Vcc . The source of N-channel transistor 224 is coupled to the source of P-channel transistor 226 and the gate of P-channel transistor 228.

P channel transistors 226 and 22
Eight drains are coupled to V _ppi input terminals 225 and 227, respectively. The V _ppi input is provided by the gate voltage selection circuit 200. The gate of P-channel transistor 226, the source of P-channel transistor 228, and the drain of N-channel transistor 230 are coupled to output voltage 231 of gate voltage providing circuit 220. The source of N-channel transistor 230 is coupled to common 229.

When a specific gate voltage providing circuit 220 is not selected, the input signals I ₀ . . . At least one of In _-1 is a logical "low". When at least one of the inputs to NAND gate 222 is logic "low", the output of NAND gate 222 is logic "high". When the output of NAND gate 222 is logic "high", N-channel transistor 230
Turns on, and pulls down the output voltage 231 to near the ground of the common 229. When output voltage 231 is reduced, P-channel transistor 226 turns on, providing a logic “high” voltage to the gate of P-channel transistor 228, thereby preventing providing a high voltage at output 231. Therefore, the gate voltage providing circuit 220 does not provide an output voltage for a read or program operation when not selected.

A specific gate voltage providing circuit 220 is selected.
Input signal I₀. . . I_n-1Are all logic "high"
And the output of NAND gate 222 is a logical "low".
is there. Applied to the gate of N-channel transistor 230
Low logic will cause the transistor to go low
Thus, the output 231 is not pulled low. NAND game
A logic low from the output of port 222 is an N-channel
P-channel transistor 22 through transistor 224
8 is applied to the gate. N-channel transistor 22
8 is turned on and the output 231 is set to V_ppi227 voltage level
V according to the bell _ppOr V_ccPull up to high.

Transistors 226, 228 and 230
In order must handle V _pp, they are high-voltage transistor with a thick oxide layer and a relatively low conductivity. When V _cc is lower than normal, the conductivity of the P-channel transistor 228 is actually lower, thus slowing down the read operation. Therefore, the transistor 202 that provides V _cc to V _ppi 203 must be large.

FIG. 13 illustrates one embodiment of a gate voltage providing circuit 240 of the present invention having an independent high voltage section and an independent low voltage section. The low voltage section of the gate voltage providing circuit performs an operation that requires high speed switching. In the gate voltage providing circuit 240, when the gate voltage providing circuit 240 is selected, the NAND gate 242 becomes the NA of the conventional circuit.
The ND gate 222 receives an input signal in the same manner.

The output 243 of the NAND gate 242 is N
Gate of channel transistor 248, inverter 24
6 and the drain of an N-channel transistor 252. Output 247 of inverter 246
Is coupled to the drain of N-channel transistor 250. N-channel transistor 250 has its gate coupled to the source of N-channel transistor 248 and the source of N-channel transistor 252. The source of N-channel transistor 250 is coupled to output voltage 260 of the gate voltage providing circuit. Read signal R is provided to the input of inverter 244. The output of inverter 244 is applied to the gate of transistor 252. Transistors 248 and 250 are low-voltage N-channel transistors having a threshold voltage of 0V. N-channel transistor 250 is used to separate the high voltage section from the low voltage section.

When a particular gate voltage providing circuit is not selected, the output 243 of the NAND gate 242 is high and the output 247 of the inverter 246 is low. N
Since channel transistor 248 turns on, N-channel transistor 250 turns on and node 249 goes high. Therefore, the low output from the inverter 246 is output as the output of the specific gate voltage providing circuit.
When the low output of the gate voltage providing circuit is applied to the gates of transistors 254 and 256 operating as inverters, P-channel transistor 254 turns on, applying V _ppi to the gate of P-channel transistor 258, 256 turns off.
As a result, P-channel transistor 258 turns off and V _ppi is not provided at output 260.

When a particular gate voltage providing circuit is selected, the output 243 of the NAND gate 242 goes low and the output 247 of the inverter 246 is high. When the read signal R is high, indicating a read operation, the output of the inverter 244 is low, so that the N-channel transistor 252 is turned off. Output 260 is raised to V _ppi .

Because of the channel capacitance of N-channel transistor 250, node 249 at the gate of N-channel transistor 250 is tied high, maintaining the high conductivity of N-channel transistor 250. Inverter 24
Because 6 is formed by a high conductivity transistor, the output 260 is driven strongly and the read operation is fast. Further, the inverter 246 does not lower the V _ppi voltage by producing a high output. Therefore, FIG.
The depletion-type N-channel transistor 202 of the gate voltage selection circuit of FIG. 2A does not need to be large to compensate for the voltage drop of V _ppi .

When a specific gate voltage providing circuit is selected and the read signal R is low to indicate a program operation, the output of the inverter 244 is high, so that the N-channel transistor 252 is turned on. N-channel transistor 2
48 gradually turns off as node 249 is pulled low. In connection with a read operation, output 260 is pulled up to V _ppi as described above. However, when turned off, the N-channel transistor 248 functions as a buffer, and separates the low voltage portion of the gate voltage providing circuit from the high voltage portion of the gate voltage providing circuit. Therefore, the program voltage, that is, the voltage higher than the read voltage is provided to the output 260 without affecting the low voltage portion of the gate voltage providing circuit.

IV. Address Sequencer The address sequencer sequentially increments the address by one in synchronization with the rising edge of the internal clock signal. A toggle signal is used to generate an address signal. Such a toggle signal is generated inside the address sequencer.

Conventionally, a number of logic gates configured together have been used to generate n addresses using a toggle signal. This conventional configuration of the logic gate illustrated in FIG.
A series of delays was forced through n-1 NAND gates and n-1 inverters. The sum of these delays represents a large delay, especially in view of increasing the operating clock frequency of the memory device. For example, if the delay of t ₁ is associated with each logic gate, the total amount of delay is J = n × t _1. This prevents the clock period from becoming shorter than J. Thus, reducing the delay path of the logic gates, i.e., the number of gates of the address signal generator, provides the ability for the memory device to operate at a higher frequency clock.

FIG. 14 shows a conventional address sequencer 30.
0 is a block diagram of FIG. The trigger signal generator 301 generates a trigger signal 5, which is sent to the clock control circuit 2 to initiate clock cycle suppression of the internal clock signal, as previously described in connection with FIGS. Provided. This means that the trigger signal 5 is generated 1
The generation of the trigger signal 5 is just one example and is not limited to this particular example. Clock trigger signal generator 301 is coupled to an address signal generated internally by address sequencer 300.

The address sequencer 300 includes address signal generators 304, 308 and 312 for generating address signals A ₀ , A ₁ and _An-1 respectively. For clarity, the address signals A ₂ . . . A
The address signal generator for _n-2 is not shown in FIG. Each address signal generator has an internal clock signal 7
And the inverted internal clock signal. Internal clock signal input 7 is inverted by inverter 302 to generate an inverted internal clock signal. Address signal generator 304,
308 and 312 are two-input XOR gates 3
03, 307 and 311.

The first input of XOR gate 303 is tied to a logical "1". A second input of XOR gate 303 is coupled to output A ₀ of address signal generator 304. A first input of XOR gate 303 is also coupled to a first input of NAND gate 305. XOR gate 3
03 is also coupled to a second input of NAND gate 305. The output of NAND gate 305 is coupled to the input of inverter 306.

The output toggle signal (Tg) of the inverter 306
l (0)) is the first input of the XOR gate 307 and NA
It is coupled to a first input of ND gate 309. The output A ₁ of the second address generator 308 is
And a second input of NAND gate 309. The output of NAND gate 309 is coupled to the input of inverter 310. The output of inverter 310 is a toggle signal (Tgl (1)). A first input of the XOR gate 311 is connected to a toggle signal (Tgl (n−
2)). A second input of XOR gate 311 is coupled to output _An-1 of address signal generator 312.

Address signal generator 30 shown in FIG.
One of 4, 308 or 312, two-input XOR gate 3
03, 307 or 311 the NAND gate 30
5 or 309 and one configuration of the inverters 306 or 310 are represented by the following Boolean equations (Boolea
n equation).

[0072]

(Equation 1)

With AB = A + B and conventional Boolean algebra, the following Boolean equation is obtained: If the even address, ie, n is even, the resulting Boolean equation is:

[0074]

(Equation 2)

If the odd address, ie, n is odd, the resulting Boolean equation is:

[0076]

(Equation 3)

The Boolean equations (2) and (3) are shown in FIG.
5 (a) to 5 (c). If the delay of the NOR gate is equal to the delay of the NAND gate, the minimum cycle time limited by the address sequencer is reduced. Therefore, the delay is
Decrease. For example, if the delay of a NOR or NAND gate is T _an , then the total delay is J = 20 × T _an .
Conventionally, the delay is a combination of a NAND gate and an inverter. Therefore, the total delay is even longer. For example, the total delay is about 20. Therefore, the cycle time n × T _ai is improved. When T _ai is 0.5 ns, 10 ns is reduced.

Similarly, in another embodiment of the address sequencer, the Boolean equations (1) and (1a) are such that m = 1 /
It is operated by setting 2. For m = 1/2, using conventional Boolean algebra, one obtains the following Boolean equation:

[0079]

(Equation 4)

By combining equation (5) with equation (4), the following Boolean equation is obtained.

[0081]

(Equation 5)

Thus, using equation (1), the following Boolean equation is obtained:

[0083]

(Equation 6)

Boolean equations (6), (7) and (8)
Is represented by the logic gates illustrated in FIGS. 16A to 16C when k = n / 2. FIG. 16 (a)
16 (c), the total number of NAND gates is n / 2, so that the cycle time for limiting the address sequencer is reduced to half. Another embodiment of the address sequencer is illustrated in FIG. The address sequencer of FIG. 17 is the same as the conventional address sequencer illustrated in FIG. However, in FIG.
Clock inputs to some address sequencers are address bits. For the last column control transistor indicating the transition (start / end) of the word line, the address bit from the address buffer is used. The inverse of the last column address bit is used instead of the clock input to the address sequencer.

For example, in the case of an address including the address signals A0 to A21, 22 address buffers are used. The address buffer for the address bits A0 to A5 uses an internal clock signal. A5 is assumed to be a word line switching address bit. But,
Although some address signal is used, the word line switching address bits allow a maximum delay time due to word line switching. A5 is used as a clock signal and provides a clock input to the remaining address buffers used to generate addresses A6-A21.

V. Data Sensing Returning to FIG. 1, sense amplifiers 18 and 22 are coupled to individual data lines. These data lines are coupled to the individual memory block bit lines. The initial voltage level of these data lines is usually 0. However, due to the capacitance generated between adjacent data lines, the data lines often have a voltage higher than the ground level. Thus, a delay is experienced when a predetermined read voltage is applied to the data line and S / A 18 and 22 attempt to sense data from the memory cell. Conventionally, the data lines are separated, ie, a large space is provided between the data lines to eliminate the delay. However, adding a large amount of space between the data lines adds memory die dimensions,
That is, the physical space occupied by the flash memory device also increases.

To remove the delay without increasing the size of the memory die, pull-down transistors are introduced on the data lines. In FIG. 18, a pull-down transistor 801 is coupled to a data line 803. The gate of the pull-down transistor 801 is connected to the reset signal line 80.
5 Before reading the memory cell, the reset signal line 805 goes high for a short period of time. Thus, the pull-down transistor is turned on and grounds the data line. Since all data lines initially start at the ground voltage level, the capacitance coupling between the data lines decreases with the capacitance of the individual data lines. Thus, the delay experienced by the data lines is reduced without increasing the size of the memory die.

VI. High Voltage Comparator As illustrated in connection with FIG.
It requires a set of predetermined voltages to be applied to the memory cells. The high voltage comparator circuit 54 of FIG. 1 includes a set of transistors that determine the exact timing when the predetermined voltage is high enough to start programming the memory cell. FIG. 19 shows an embodiment of the high voltage comparator circuit 54 of FIG. The high voltage comparator circuit of FIG. 19 detects when the voltage level of the predetermined program voltage on the line AA corresponds to the voltage level on the line BB. The voltage level of the line V _ref is always assumed to be high, the voltage level of the line V _pp is assumed to be increasing. Line V _pp is coupled to the gate of V _pp transistor 181. As the voltage level on line V _pp increases, V
_{The pp} transistor 181 turns on and the line BB coupled to the drain of the V _pp transistor 181 slowly goes to V _cc . Accordingly, the voltage level of the line V _pp is increased, the voltage level of the line BB also gradually increases.

The line BB is connected to the BB transistor 183 and A
It is also coupled to the gate of A transistor 185. Therefore, when the voltage level of the line BB gradually increases, the BB and AA transistors also gradually turn on. The line AA is coupled to the source of the AA transistor 185,
It is also coupled to the drain of reference transistor 187. Line V _ref is coupled to the gate of reference transistor 187. Because of the constant voltage level applied to the line _Vref , the reference transistor 187 is on and therefore the line A
The voltage level of A approaches the voltage _Vcc . As the AA transistor gradually turns on, a path is created from voltage _Vcc to ground, so that the voltage level on line AA is gradually reduced. Therefore, as the voltage level of the line BB gradually increases, the voltage level of the line AA gradually decreases.

Line AA is also coupled to the gate of AA depletion type transistor 167, and line BB is coupled to BB
It is coupled to the gate of depletion type transistor 169. When the voltage level of the line BB gradually increases, BB
The depletion type transistor 167 is gradually turned on. Similarly, when the voltage level of the line AA gradually decreases, the AA depletion type transistor 167 gradually turns off. BB depletion type transistor 16
9 is coupled to the mutually coupled gates of the first P-channel transistor 163 and the second P-channel transistor 165. When the BB depletion transistor 169 turns on, a path to ground is formed,
The first P-channel transistor 163 and the second P-channel transistor 165 are turned on.

Line V_PPOKIs an AA depletion type tiger
Source of transistor 167 and second P-channel transistor
Coupled to the drain of the Second P-channel
The transistor turns on and the AA depletion type
When the transistor 167 turns off slowly, the line voltage V_cc
Provided a route to. Therefore, the track V_PPOKThe voltage of
Increases rapidly. In other words, the voltage level of the line BB is
Increase to correspond to the voltage level on line AA, where the line
The voltage level of the road AA is decreasing and the line V _PPOKNo electricity
The pressure level increases. Therefore, the voltage level of the line BB is
As soon as the voltage level becomes higher than the voltage level of the line AA, the line V
_PPOKVoltage level rises sharply and the line V_PPOKIs the voltage V
_ccbecome. Track V_PPOKIndicates that the voltage level of the line BB is
Big enough to start reselling program, i.e.
That is, the voltage level of the line BB is higher than the voltage level of the line AA.
Indicates that it is big. Therefore, the programming of the memory cell
Is a predetermined program voltage, that is, the line BB and the line
When the voltage level of AA reaches a specific operating voltage level
Get started right away.

VII. Conclusion Accordingly, the present invention provides a clock control circuit capable of generating an internal clock by blocking (blocking) an external clock signal for one or more selected clock cycles. Although application in a NOR type synchronous flash memory device has been described, this clock control circuit has wide application in semiconductor devices requiring similar internal clock signals. That is, this clock control circuit
An ND type synchronous flash memory device is similarly useful.

The present invention also provides a decoder circuit capable of rapidly generating a predetermined voltage for program and read operations. Although the application in NOR flash memory devices has been described, this decoder circuit also has a wide range of applications in semiconductor devices that require an increased supply of predetermined voltages. That is, this decoder control circuit is similarly useful in a NAND-type synchronous flash memory device.

Further, while the invention has been described in certain specific embodiments, many additional modifications and variations will be apparent to those skilled in the art. Thus, it will be appreciated that the invention may be practiced otherwise than as specifically described. That is, the embodiments of the present invention are intended to be illustrative in all aspects and not restrictive, and the scope of the present invention is deemed to be determined not by the above description but by the appended claims and their equivalents . (Supplementary Note 1) A clock control circuit that receives an external clock signal and a trigger signal and generates an internal clock signal, the clock control circuit receiving the external clock signal and the trigger signal, each of which is delayed by at least one clock cycle from the trigger signal. Shift register assembly for generating a plurality of time delay trigger signals, a clock trigger signal generation circuit for receiving the time delay trigger signal and generating a clock trigger signal, and receiving the external clock signal and the clock trigger signal. A clock buffer circuit for generating the internal clock signal. (Supplementary note 2) The clock control circuit according to supplementary note 1, wherein the shift register assembly includes a plurality of serially coupled plurality of the shift register assemblies each receiving the external clock signal and generating one of the plurality of time delay trigger signals. A shift register, wherein a first one of the serially coupled shift registers receives the trigger signal, and each subsequent shift register receives the time delay trigger signal generated by the immediately preceding shift register. Clock control circuit. (Supplementary note 3) The clock control circuit according to supplementary note 2, wherein each of the time delay trigger signals is shifted from all other time delay trigger signals by at least one cycle of the external clock signal. circuit. (Supplementary Note 4) The clock control circuit according to supplementary note 2, wherein the plurality of shift registers coupled in series include three shift registers coupled in series. (Supplementary Note 5) In the clock control circuit according to Supplementary Note 1, the clock trigger signal generation circuit includes a first stage circuit having a plurality of first stage NOR gates each receiving two input signals and generating an output signal. A second stage circuit having a second stage NOR gate for receiving a plurality of input signals, the second stage circuit being coupled to an output signal of each of the first stage NOR gates. (Supplementary Note 6) In the clock control circuit according to Supplementary Note 5, one of the two input signals of the first stage NOR gates is one of the plurality of time delay trigger signals, and the number of the time delay trigger signals is one. And the first stage N
A clock control circuit, wherein the number of OR gates has a one-to-one correspondence. (Supplementary note 7) The clock control circuit according to supplementary note 5, wherein one of the two input signals of each of the first stage NOR gates is one of a plurality of clock rejection signals. (Supplementary note 8) The clock control circuit according to supplementary note 7, wherein the plurality of clock blocking signals are programmed in advance during manufacturing. (Supplementary Note 9) In the clock control circuit according to Supplementary Note 7, the number of clock cycles blocked from the external clock signal to generate the internal clock signal is determined by the plurality of clock blocking signals. Clock control circuit. (Supplementary note 10) The clock control circuit according to supplementary note 9, wherein a time during which the number of clock cycles is blocked from the external clock signal is determined by the clock trigger signal. (Supplementary Note 11) In the clock control circuit according to supplementary note 1, the clock buffer circuit blocks the external clock signal and the clock trigger signal in order to block some external clock signal cycles and generate the internal clock signal. A clock control circuit characterized by combining the following. (Supplementary Note 12) A method of generating an internal clock signal from an external clock signal and a trigger signal, the method comprising:
A clock control circuit having a shift register assembly, a clock trigger signal generation circuit, and a clock buffer circuit, wherein the shift register assembly receives the external clock signal and the trigger signal and generates a plurality of time delay trigger signals. Receiving the time delay trigger signal by the clock trigger signal generation circuit, generating a clock trigger signal by combining the time delay trigger signal, and receiving the external clock signal and the trigger signal by the clock buffer circuit; A method for generating an internal clock signal, comprising: generating the internal clock signal. (Supplementary note 13) The method of generating an internal clock signal according to supplementary note 12, wherein the shift register assemblies are serially coupled, each receiving the external clock signal and generating one of the plurality of time delay trigger signals. A plurality of shift registers, a first of the serially coupled shift registers receiving the trigger signal, and each subsequent shift register receiving the time delay trigger signal generated by the immediately preceding shift register. A method for generating an internal clock signal, the method comprising: (Supplementary note 14) The internal clock signal generation method according to supplementary note 12, wherein each of the time delay trigger signals is shifted from all other time delay trigger signals by at least one cycle of the external clock signal. Internal clock signal generation method. (Supplementary note 15) The internal clock signal generating method according to supplementary note 13, wherein the plurality of shift registers coupled in series include three shift registers coupled in series. (Supplementary Note 16) In the internal clock signal generation method according to supplementary note 12, the clock trigger signal generation circuit includes a first stage circuit and a second stage circuit, and receives the time delay trigger signal to generate the clock trigger signal. Generating the plurality of output signals by receiving the time delay trigger signal by the first stage circuit, and receiving the plurality of output signals from the first stage circuit by the second stage circuit; A method for generating an internal clock signal, comprising generating a clock trigger signal. (Supplementary note 17) In the internal clock signal generation method according to supplementary note 16, further, the first stage circuit receives a plurality of clock rejection signals, and the clock rejection signal is used to generate the internal clock signal. A method for generating an internal clock signal, comprising determining the number of clock cycles blocked from a clock signal. (Supplementary note 18) In the internal clock signal generation method according to supplementary note 17, a time during which the number of clock cycles is blocked from the external clock signal to generate the internal clock signal is determined by the clock trigger signal. A method of generating an internal clock signal. (Supplementary note 19) The method of generating an internal clock signal according to supplementary note 12, wherein when the external clock signal and the clock trigger signal are combined, the clock trigger signal for preventing some external clock signal cycles is used. Wherein the internal clock signal is generated by the clock buffer circuit. (Supplementary Note 20) The system includes a plurality of memory cells, and a clock control circuit that receives an external clock signal and a trigger signal to generate an internal clock signal, and the internal clock signal is used for reading synchronous data and programming. A synchronous flash memory. (Supplementary note 21) In the synchronous flash memory according to supplementary note 20, the clock control circuit receives the external clock signal and the trigger signal, and generates a plurality of time delay trigger signals; A synchronous type comprising: a clock trigger signal generation circuit that receives a trigger signal to generate a clock trigger signal; and a clock buffer circuit that receives the external clock signal and the clock trigger signal to generate the internal clock signal. Flash memory. (Supplementary note 22) The synchronous flash memory according to supplementary note 21, wherein the shift register assembly includes a plurality of serially-coupled shift registers each receiving the external clock signal and generating one of the plurality of time delay trigger signals. Wherein the first of the serially coupled shift registers receives the trigger signal, and each subsequent shift register receives the time delay trigger signal generated by the immediately preceding shift register. Characteristic synchronous flash memory. (Supplementary note 23) The synchronous flash memory according to supplementary note 22, wherein each of the time delay trigger signals is deviated from all other time delay trigger signals by at least one cycle of the external clock signal. Type flash memory. (Supplementary note 24) The synchronous flash memory according to supplementary note 22, wherein the plurality of shift registers coupled in series include three shift registers coupled in series. (Supplementary Note 25) In the synchronous flash memory according to Supplementary Note 21, the clock trigger signal generation circuit includes a plurality of first-stage NOR gates that receive two input signals, and each of the first-stage NOR gates outputs an output signal. A first stage circuit for generating, and a second stage circuit having a second stage NOR gate for receiving a plurality of input signals, wherein each input signal is coupled to an output signal of each of the first stage NOR gates. Synchronous flash memory. (Supplementary note 26) In the synchronous flash memory according to supplementary note 25, one of the two input signals of each of the first stage NOR gates is one of the plurality of time delay trigger signals.
Wherein the time delay trigger signal and the first stage NOR gate have a one-to-one correspondence. (Supplementary note 27) The synchronous flash memory according to supplementary note 25, wherein one of the two input signals of each of the first stage NOR gates is one of a plurality of clock rejection signals. . (Supplementary note 28) The synchronous flash memory according to supplementary note 27, wherein the plurality of clock blocking signals are programmed in advance during manufacturing. (Supplementary Note 29) In the synchronous flash memory according to Supplementary Note 27, the number of clock cycles blocked from the external clock signal to generate the internal clock signal is determined by the plurality of clock blocking signals. Characteristic synchronous flash memory. (Supplementary note 30) The synchronous flash memory according to supplementary note 29, wherein a time during which the number of clock cycles is blocked from the external clock signal is determined by the clock trigger signal. (Supplementary note 31) In the synchronous flash memory according to supplementary note 21, the clock buffer circuit generates the internal clock signal by blocking some external clock signal cycles, and the clock buffer circuit generates the internal clock signal. Synchronous flash memory characterized by combining signals. (Supplementary Note 32) The synchronous flash memory according to supplementary note 21, further comprising a plurality of write amplifiers coupled to each of the plurality of memory cell blocks. (Supplementary Note 33) The synchronous flash memory according to supplementary note 21, further comprising a plurality of sense amplifiers coupled to each of the plurality of memory cell blocks. (Supplementary Note 34) A plurality of memory cells arranged in a memory cell array having rows and columns, a predetermined number of adjacent columns include one memory cell block, and the memory cell array includes a plurality of memory cell blocks;
A plurality of column control transistors each corresponding to a column of the memory cell, receiving a plurality of column control transistors coupled to a drain of the memory cell in the corresponding column, receiving an address signal, and generating a column decode signal. A column decoder circuit coupled to the gate of the transistor and receiving the address signal to generate a column decode signal, wherein each column decode signal is associated with a row of memory cells and is coupled to a control gate of a memory cell of the associated row; A row decoder circuit, a column buffer for receiving the address signal, buffering the address signal and providing the address signal to the column decoder circuit, a buffer circuit for receiving the address signal, buffering the address signal, and storing the address signal. To provide the row decoder circuit with Receiving the internal clock signal, generating the address signal, providing the address signal to the column buffer and the row buffer, and the address signal is transmitted from the last column of the current row memory cell block to the next row. When an address transition to the first column of the memory cell block is indicated, an address sequencer for generating a trigger signal, an external clock signal and the trigger signal are received to generate the internal clock signal, and the internal clock signal reads data. And a clock control circuit used to synchronize a program, a plurality of write amplifiers each coupled to one of the plurality of memory cell blocks, and a plurality of write amplifiers each coupled to one of the plurality of memory cell blocks A plurality of sense amplifiers and an external clock signal, each of which Of the write amplifier 1
A plurality of input / output buffers coupled to one of the plurality of sense amplifiers, a source power supply coupled to a source of the plurality of memory cells, and a column decoder circuit and a row decoder circuit; And a decoder power supply for providing a control gate voltage of the flash memory device. (Supplementary Note 35) A gate voltage providing circuit having a high voltage portion and a low voltage portion, wherein the high voltage portion is substantially separated from the low voltage portion, and receives a plurality of address signals and a gate voltage; A gate voltage selecting circuit for providing the gate voltage to the gate voltage providing circuit for use as an output of the circuit. (Supplementary note 36) In the address decoder circuit according to supplementary note 35, the gate voltage providing circuit provides the gate voltage as an output when the address signal indicates that a condition for generating the gate voltage output is satisfied. Address decoder circuit characterized in that: (Supplementary note 37) In the address decoder circuit according to supplementary note 36, the high voltage unit of the gate voltage providing circuit includes a plurality of high voltage transistors that provide a conduit from the gate voltage selecting circuit to an output of the gate voltage providing circuit. An address decoder circuit, comprising: (Supplementary Note 38) In the address decoder circuit according to Supplementary Note 36, the low voltage unit of the gate voltage providing circuit provides a conduit from the gate voltage selecting circuit to an output of the gate voltage providing circuit, and the gate voltage providing circuit An address decoder circuit comprising a plurality of low-voltage transistors for bypassing the high-voltage section. (Supplementary note 39) In the address decoder circuit according to Supplementary note 38, the low voltage portion of the gate voltage providing circuit includes a second low voltage portion coupled to an output of the gate voltage providing circuit and a high voltage portion of the gate voltage providing circuit. A voltage transistor, a first low voltage transistor coupled to a reference voltage and the second low voltage transistor and acting as a switch to turn on the second low voltage transistor, and a NAND coupled to the address signal A gate, a first inverter receiving a read signal, a second inverter coupled to the NAND gate and the first and second low voltage transistors, the first and second inverters, and the NAND A gate and the second
And a third low voltage transistor coupled to the low voltage transistor. (Supplementary note 40) In the address decoder circuit according to supplementary note 37, the high voltage portion of the gate voltage providing circuit includes a common ground, an output of the gate voltage providing circuit, a low voltage portion of the gate voltage providing circuit, and the common ground. A first high voltage transistor coupled to the output of the gate voltage selection circuit; a second high voltage transistor coupled to the output of the first high voltage transistor and the gate voltage providing circuit; An address decoder circuit comprising: an output of a voltage selection circuit; a third high voltage transistor coupled to the first and second high voltage transistors and an output of the gate voltage providing circuit. (Supplementary Note 41) A plurality of memory cells, a column decoder circuit that receives an address signal to generate a column decode signal, and receives an address signal to generate a column decode signal, and each of the column decode signals is related to a row of the memory cell. And a row decoder circuit coupled to a control gate of the associated memory cell of the row, wherein the column decoder circuit has a high voltage portion and a low voltage portion, and the high voltage portion is separated from the low voltage portion. A gate voltage providing circuit that receives a plurality of address signals and a gate voltage, and a gate voltage selecting circuit that provides the gate voltage to the gate voltage providing circuit for use as an output of the gate voltage providing circuit; A flash memory. (Supplementary note 42) In the flash memory according to supplementary note 41, the row decoder circuit has a high voltage portion and a low voltage portion, the high voltage portion is separated from the low voltage portion, and a plurality of address signals and a gate voltage are provided. And a gate voltage providing circuit for receiving the gate voltage from the gate voltage providing circuit for use as an output of the gate voltage providing circuit. (Supplementary note 43) The flash memory according to supplementary note 42, further comprising a plurality of write amplifiers coupled to each of the plurality of memory cell blocks. (Supplementary note 44) The flash memory according to supplementary note 42, further comprising a plurality of sense amplifiers coupled to each of the plurality of memory cell blocks.

[0095]

As described above in detail, according to the present invention, the delay due to a specific read operation and the delay due to the operation speed of the high voltage transistor of the decoder circuit are reduced.
A flash memory circuit which can operate at higher speed can be provided.

[Brief description of the drawings]

FIG. 1 is a top-level block diagram of a flash memory device according to the present invention.

FIG. 2 is a top-level block diagram of one embodiment of a clock control circuit.

FIG. 3 is a block diagram of one embodiment of a shift register assembly in the clock control circuit of FIG. 2;

FIG. 4 schematically illustrates one of the shift registers in the shift register assembly of FIG.

FIG. 5 is a diagram schematically showing an embodiment of a trigger signal generation circuit in FIG. 2;

FIG. 6 is a diagram schematically showing one embodiment of a clock buffer in FIG. 2;

FIG. 7 is a timing diagram illustrating the relationship between different signals using the clock control circuit of FIG. 2;

FIG. 8 is a diagram schematically showing one embodiment of a data timing circuit in FIG. 1;

FIG. 9 is a schematic diagram of one embodiment of a set extension sense buffer circuit and a diagram schematically showing one embodiment of a reset extension sense buffer circuit.

FIG. 10 is a timing diagram illustrating the interaction between different signals using the data timing circuit of FIG.

FIG. 11 is a block diagram of an address decoder circuit used for both a row decoder circuit and a column decoder circuit.

FIG. 12 is a diagram showing a gate voltage selection circuit and one gate voltage providing circuit in a conventional address decoder circuit.

FIG. 13 is a diagram showing one gate voltage providing circuit according to the present invention.

FIG. 14 is a diagram showing a conventional address sequencer.

FIG. 15 illustrates one embodiment of the improved address signal generator of the present invention for even address signals, one embodiment of the improved address signal generator of the present invention for odd address signals, and the address of the present invention. FIG. 4 is a diagram illustrating a signal delay path for generating an address signal using a signal generator.

FIG. 16 illustrates an embodiment of the address signal generator of the present invention for odd address signals, an embodiment of the address signal generator of the present invention for even address signals, and using the address signal generator of the present invention. FIG. 3 is a diagram showing a signal delay path for generating an address signal by using the same.

FIG. 17 is a block diagram of an embodiment of an address sequencer according to the present invention.

FIG. 18 is a block diagram of one embodiment of a data sensing scheme.

FIG. 19 is a schematic diagram of one embodiment of a high voltage comparator.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Synchronous flash memory 2 ... Clock control circuit 3 ... External clock 4 ... Address sequencer 5 ... Trigger signal 6 ... Column buffer 7 ... Internal clock signal 8 ... Row buffer 9 ... ATD circuit 10 ... Decoder power supply 12, 14 ... Input / Output buffer (I / O buffer) 15 Data timing circuit 16, 20 W / A (write amplifier) 18, 22 S / A (sense amplifier) 21 Shift register assembly 23 Clock trigger signal generator 24 ... column decoder circuit 25 ... clock buffer 26 ... row decoder circuit 52 ... source power supply 54 ... high voltage comparator 162 ... address selection circuit 200 ... gate voltage selection circuit 240 ... gate voltage supply circuit 301 ... trigger signal generator A ₀ ... address signal V ₀ ... column / row decode signal

Claims (4)

[Claims] 1. A clock control circuit for receiving an external clock signal and a trigger signal and generating an internal clock signal, the clock control circuit receiving the external clock signal and the trigger signal, each receiving at least one clock period from the trigger signal. A shift register assembly for generating a plurality of delayed time delay trigger signals, a clock trigger signal generation circuit for receiving the time delay trigger signal and generating a clock trigger signal, and receiving the external clock signal and the clock trigger signal A clock buffer circuit for generating the internal clock signal. 2. A method for generating an internal clock signal from an external clock signal and a trigger signal, the method comprising:
A clock control circuit having a shift register assembly, a clock trigger signal generation circuit, and a clock buffer circuit, wherein the shift register assembly receives the external clock signal and the trigger signal and generates a plurality of time delay trigger signals. Receiving the time delay trigger signal by the clock trigger signal generation circuit, generating a clock trigger signal by combining the time delay trigger signal, and receiving the external clock signal and the trigger signal by the clock buffer circuit; An internal clock signal generation method, wherein the internal clock signal is generated. 3. A semiconductor device comprising: a plurality of memory cells; and a clock control circuit receiving an external clock signal and a trigger signal to generate an internal clock signal, wherein the internal clock signal is used for reading synchronous data and programming. A synchronous flash memory. 4. A gate voltage providing circuit having a high voltage portion and a low voltage portion, wherein the high voltage portion is substantially separated from the low voltage portion and receives a plurality of address signals and a gate voltage; To use as the output of the providing circuit,
A gate voltage selection circuit for providing the gate voltage to the gate voltage providing circuit.