JP2000332969A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Problem] To provide an integrated image sensor capable of accurately performing black level correction without complicating a circuit configuration. A pixel signal output from a light receiving element array (1) is converted into a digital signal by an analog / digital conversion circuit (3), and a black level value serving as a reference value for black level correction is calculated and held.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a light receiving element array in which light receiving elements for converting an optical signal into an electric signal are arranged in an array, and an analog electric signal from the light receiving element array. The present invention relates to a semiconductor integrated circuit in which an analog / digital conversion circuit for converting a digital value is integrated.

[0002]

2. Description of the Related Art FIG. 12 is a diagram showing a functional configuration of an image sensor. In FIG. 12, the image sensor
A light receiving element array 500 that converts an optical signal into an electric signal,
It includes a signal reading unit 502 for reading a signal generated by the light receiving element array, and a signal output unit 504 for sequentially reading electric signals read by the signal reading unit 502 and providing the read signals to a processing unit.

In the light receiving element array 500, in the case of a two-dimensional image sensor, light receiving elements are arranged in a matrix, and each light receiving element converts an optical signal into an electric signal. The signal reading unit 502 differs depending on the configuration of the image sensor.
In the light receiving element array 500, the generated electric signal is read out in frame units or line units. The signal output unit 504 sequentially outputs the pixel data read by the signal reading unit 502 for each row (corresponding to one horizontal scanning line). Normally, the signal readout unit 502 and the signal output unit 50
4 is an electric signal (charge) sequentially in synchronization with the clock signal.
Are transferred in the vertical and horizontal directions, respectively.

FIG. 13 is a diagram showing an example of the configuration of a light receiving element. In FIG. 13, the light receiving element includes a photoelectric conversion unit 510 formed of, for example, a photodiode, and a read gate 512 for reading an electric signal generated by photoelectric conversion unit 510 in response to read clock signal φ. In the light receiving element shown in FIG. 13, a PN junction capacitance is used, and charges are accumulated in the PN junction capacitance according to the intensity (light amount) of the optical signal. The read gate reads the charge accumulated by photoelectric conversion unit 510 according to read clock signal φ. When the image sensor is a two-dimensional image sensor, the light receiving elements are arranged in an array of rows and columns corresponding to the respective pixels, and the electric signals read by the read gate 512 are arranged in a horizontal direction on the screen. (Operation of the signal reading unit 502).

[0005] The light receiving element includes a photodiode using a PN junction capacitance as a charge storage unit as a photoelectric conversion unit. For example, a MOS capacitor may be used in the photoelectric conversion unit.

As shown in FIG. 13, the amount of charge stored in the light receiving element changes in accordance with the amount of incident light.

FIG. 14 is a diagram showing the relationship between the charge accumulation time and the output potential in the image sensor. In FIG. 14, the horizontal axis indicates the accumulation time, and the vertical axis indicates the output potential.
A straight line group I indicates an output of a pixel (light receiving element) at a certain illuminance, a straight line II indicates a black level output, and a straight line II
I indicates an ideal black level output after correction.

As shown in FIG. 14, as the accumulation time t becomes longer, the amount of electric charge accumulated in the light receiving element increases, and the output potential thereof also increases. Therefore, the output voltage of the element that gives the reference value of the black level gradually increases due to light leakage or the like. That is, if the accumulation time t is increased to obtain a clear image under a dark condition, the “black”
Is also brightened, and an accurate image cannot be obtained. Therefore, in order to enhance the image quality of the image sensor, it is necessary to accurately output a black level that provides a reference for luminance.

Conventionally, a process called black level correction is performed in which the black level output from the pixel (light-shielding element) corresponding to "black" is clamped and the black level is subtracted from the output values of all the pixels. ing. In this case, as shown in FIG. 14, the black level indicated by the straight line II is clamped and subtracted from the original pixel output value, so that the ideal black level output is equivalent to the potential as indicated by the straight line III. Becomes 0. In this case, the output potential of the effective pixel changes from the straight line Ia in the straight line group I to the straight line Ib. As a result, the black portion of the target image is accurately processed as black, and a pixel output value based on this black is obtained.

FIG. 15 is a diagram schematically showing a configuration of a conventional image sensor having a black level correction function. Referring to FIG. 15, the image sensor includes a black level correction circuit 510 that performs black level correction of a pixel signal output from light receiving element array 500 in accordance with a black level reference signal read and output from light receiving element array 500. It includes a gamma correction circuit 512 for performing gamma correction on the output signal of the black level correction circuit 510, and an analog / digital (A / D) conversion circuit 514 for converting the output signal of the gamma correction circuit 512 into a digital signal.

In the light receiving element array 500, a light receiving element on which light is incident and a light receiving element on which light is shielded are arranged. The light-receiving element that blocks the incident light and generates a black-level reference signal is hereinafter referred to as a “light-shielded pixel”, and the light-receiving element that receives light and generates an electric signal according to imaging information is hereinafter referred to as an “effective pixel”. Pixel ".

A black level correction circuit 510 includes a clamp capacitor 510a for holding a potential corresponding to a black level, and an analog subtraction circuit for subtracting a charge potential of the clamp capacitor 510a from an analog electric signal output from the light receiving element array 500. 510b, a U / D control circuit 510c for generating a signal for adjusting the potential of the clamp capacitor 510a according to the output signal of the analog subtraction circuit 510b,
According to the output signal of the control circuit 510c, the clamp capacitance 5
Variable current source 510 for charging and discharging 10a, respectively
d and 510e.

The analog subtraction circuit 510b is constituted by, for example, a differential amplifier having a gain of 1, and has a signal corresponding to the difference between the charged potential of the clamp capacitor 510a and the analog electric signal output from the light receiving element array 500 in accordance with the imaging information. Is output. Before the output of the effective pixel signal, there is provided a period for reading the light-shielded pixel and correcting the black level. During this black level correction period, the U / D control circuit 510c is activated, and according to the output signal of the analog subtraction circuit 510b, the supply current amounts of the variable current sources 510d and 510e and the output signal level of the analog subtraction circuit 510b become 0. Adjust as follows. When the output signal level of the analog subtraction circuit 510b increases, the U / D control circuit 5
10c increases the amount of supply current of the variable current source 510d. On the other hand, when the output signal level of the analog subtraction circuit 510b decreases, the U / D control circuit 510c increases the amount of discharge current of the variable current source 510e. This allows
The clamp capacitor 510a holds a voltage corresponding to the output of the light-shielded pixel. In the effective pixel readout period (output period), U / D control circuit 510c is inactivated, and the voltage of clamp capacitor 510a is kept constant.

The gamma correction circuit 512 corrects the gamma characteristic of the light receiving element array 500, increases the gain of the analog electric signal in the low illuminance area, and converts the reproduced image so that the reproduced image looks natural to the human eye. I do.

The A / D conversion circuit 514 converts the analog signal output from the gamma correction circuit 512 into a digital value.

During effective pixel reading, the U / D control circuit 510c maintains the charging voltage of the clamp capacitor 510a at the end of the black level correction period (variable current source 51).
0d and 510e are stopped). The analog electric signal read out from the effective pixel and output is clamped by the analog subtraction circuit 502b.
The black level correction is performed on the analog electric signal read out from the effective pixel and output after being subtracted by the charging voltage a.

[0017]

The analog black level correction circuit shown in FIG. 15 can correct the black level of an analog electric signal read from an effective pixel. However, the gamma correction circuit 512 provided after the analog black level correction circuit 510
The gain is high in the low illuminance area, so that the black level changes in this low illuminance area. Therefore, it becomes necessary to correct the black level again in the subsequent stage of the gamma correction circuit 512.

In the A / D conversion circuit 514, the reference potential of the digital value is determined by the ladder resistance. Therefore, the zero level reference potential of the A / D conversion circuit 514 is determined by the characteristics of the ladder resistance. On the other hand, in the analog black correction circuit 510, the 0 level indicates the input / output characteristics of the analog subtraction circuit (subtraction amplifier) 510b,
It is mainly determined by the response characteristics of the / D control circuit 510c. These circuits are usually composed of MOS transistors (insulated gate field effect transistors), and their circuit characteristics are determined by characteristics such as the gate length, gate width, and threshold voltage of the MOS transistor. Since the manufacturing process of the ladder resistance of the A / D conversion circuit 514 is different from the manufacturing process of the MOS transistor of the analog black level correction circuit 510, and the variation of these parameters in the manufacturing process is different, the parameters of these processes are different. It is difficult to compensate for the variation and accurately match the 0-level signal potential output from the analog black level correction circuit with the 0-level reference potential of the A / D conversion circuit 514. This causes a problem that the black level cannot be accurately corrected.

Further, it is desirable that the image sensor be integrated as high as possible as a solid-state image sensor, and it is not preferable to increase the circuit scale.

An object of the present invention is to provide a semiconductor integrated circuit which can accurately correct the black level of an effective pixel signal and is suitable for high integration.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit which is arranged in an array and each of which receives a light receiving element for converting a light signal into an analog electric signal and a black level reference signal. A light receiving element array including a light shielding element, an analog / digital conversion circuit for converting an analog electric signal from the light receiving element array into a digital signal, and a digital signal corresponding to a black level reference signal from the analog / digital conversion circuit A black level holding circuit for generating and holding a black level reference digital signal in response to the reference signal; and an effective pixel digital signal corresponding to an analog electric signal output from the light receiving element from the analog / digital conversion circuit. A level correction circuit for level correcting the effective pixel digital signal according to the black level reference digital signal; Receiving a predetermined black level clamp value and a predetermined black level clamp value, and selecting and outputting one of the output value of the level correction circuit and the black level clamp value as a pixel digital signal according to the sign of the output value of the level correction circuit. Prepare.

In the semiconductor integrated circuit according to the second aspect, the black level clamp value of the first aspect is equal to zero.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit, wherein the black level holding circuit of the first aspect includes a circuit for calculating an average value of a plurality of black level reference digital signals and outputting the average value as a black level reference digital signal.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit, wherein the black level holding circuit according to the first aspect includes a circuit for obtaining an average value of a plurality of black level reference digital signals; an offset register for storing an offset value; An offset circuit for correcting the value with an offset value and outputting the corrected value as a black level reference digital signal.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the black level holding circuit according to the first aspect includes a two-input adding circuit receiving a digital reference signal at a first input, and accumulating an output value of the adding circuit. An accumulator circuit for applying the accumulated value to the second input of the adder circuit, and a divider circuit for dividing the accumulated value of the accumulator circuit by the number of accumulations of the accumulator circuit.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit, wherein the accumulation circuit according to the fifth aspect is constituted by a latch circuit, and the division circuit outputs a black level reference signal.

According to a seventh aspect of the present invention, the black level holding circuit of the fifth aspect further includes a latch for latching an output value of the division circuit and outputting a black level reference digital signal.

In the semiconductor integrated circuit according to the present invention, the black level holding circuit according to claim 1 is a latch circuit for latching an output value of an adder constituting a level correction circuit, and a sign of the output value of the latch circuit. A circuit for generating an inverted complement value;
A selection circuit that receives an output value of the analog / digital conversion circuit, selects a complement value when an effective pixel digital signal is applied, and selects an output value of the latch circuit when a digital reference signal is applied. The adder adds the output value of the analog / digital conversion circuit and the output value of the selection circuit.

According to a ninth aspect of the present invention, the semiconductor integrated circuit of the first aspect further receives an analog black level reference signal, clamps a black level for correcting a level of an input analog signal, and adjusts the black level. After the correction, an analog black level correction circuit that supplies the corrected analog signal to an analog / digital conversion circuit is further provided. The black level holding circuit starts the operation of generating a black level reference digital signal after the completion of the clamp operation of the analog black level correction circuit.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the black level holding circuit according to the first aspect accumulates digital reference signals from the power-of-two light-blocking elements, and an output of the accumulation circuit. And a shifter for dividing the value by a shift operation of the bit position.

The black level is calculated in accordance with the pixel output signal after the analog / digital conversion. The black level is not affected by the analog / digital conversion, and accurate black level correction can be performed.

Further, in order to process the analog / digital converted signal, this black level correction circuit is constituted by a digital circuit, and delicate circuit parameter adjustment for adjusting the response characteristics of an analog circuit such as an operational amplifier. Is unnecessary, and the circuit configuration is simplified.

[0033]

[First Embodiment] FIG. 1 schematically shows an entire configuration of a semiconductor integrated circuit according to the present invention. 1, a semiconductor integrated circuit (image sensor) according to the present invention includes a light receiving element array 1 for converting an optical signal into an electric signal, and a gamma correction circuit for performing gamma correction on an analog electric signal output from light receiving element array 1. 2
An analog / digital (A / D) conversion circuit 3 for converting an analog signal output from the gamma correction circuit 2 into a digital signal; and a digital black level for performing black level correction according to the digital value from the A / D conversion circuit 3. A correction circuit 4 is included.

The light-receiving element array 1 includes an effective pixel array 1a in which effective pixels are arranged in a matrix, and a light-shielded pixel section 1b in which a predetermined number of light-shielded pixels are arranged. In the light-shielded pixel section 1b, light-shielded pixels are arranged in one or more rows.

Gamma correction circuit 2 and A / D conversion circuit 3
Corresponds to the gamma correction circuit 512 and the A / D conversion circuit 514 shown in FIG.

In the present invention, the black level value is calculated and the black level is corrected using the pixel digital value converted into a digital value by the A / D conversion circuit 3.

The digital black level correction circuit 4 is therefore a digital circuit, and can perform accurate black level correction without having to adjust delicate circuit parameters for adjusting input / output response characteristics.

FIG. 2 is a diagram schematically showing the configuration of the digital black level correction circuit shown in FIG. In FIG. 2, a digital black level correction circuit 4 includes an adder 4a that receives a digitally converted pixel signal (AD output signal) from the A / D conversion circuit 3 at a first input, and an output value of the adder 4a. Accumulator 4b for storing and providing the stored value to the second input of adder 4a, right shifter 4c for shifting the bit position of the output value of accumulator 4b rightward, and right shifter 4c
And a subtractor 4e for subtracting the black level latched by the black level latch circuit 4d from the effective pixel digital signal from the A / D conversion circuit 3; And a literal zero circuit 4f for outputting a black level clamp value "0" (8 bits), and one of the output value of the subtractor 4e and the clamp value from the literal zero circuit 4f in accordance with the carry of the subtractor 4e. A selector 4g for generating a pixel digital output PD is included.

The A / D conversion circuit 3 generates an 8-bit digital signal as an example. The adder 4a is, for example, 1
Accumulator 4b is a 4-bit adder. Accumulator 4b has its stored value reset according to reset signal φRST, and stores the output value of adder 4a according to accumulation instruction signal φACM.

The right shifter 4c is connected to the accumulator 4b
Is shifted to the right (lower direction) by 6 bits, and a 1/64 division operation is executed.

The subtractor 4e subtracts the black level latched by the black level latch circuit 4d from the effective pixel digital signal from the A / D conversion circuit 3, and performs level correction on the effective pixel digital signal. .

When the output value of the subtractor 4e is negative, the selector 4g outputs the 8-bit 0 from the literal zero circuit 4f.
(00H) is selected. Therefore, the clamp value of the black level output from the selector 4g is 0 (00H). The selection path of the selector 4g is switched according to the carry of the subtractor 4e. For example, when the subtractor 4e is an absolute value subtractor, if the subtraction result is negative, the carry becomes "0". When the subtractor 4e is a two's complement subtractor, if the subtraction result is negative, the sign bit is output as a carry, and the value of the carry becomes zero. When the subtraction result is non-negative, the carry becomes "1". Next, the operation of the digital black level correction circuit shown in FIG. 2 will be described with reference to the timing chart shown in FIG.

In the light receiving element array 1, pixel signals are transferred in the vertical direction according to the clock signal CLK. Before reading and outputting an effective pixel signal from the effective pixel array 1a, a black level reference signal is output from a light-shielded pixel of the light-shielded pixel section 1b. The black level is corrected for each effective pixel stored in the effective pixel array 1a. Therefore, first, when reading / output of data of valid pixels in one frame or field is completed, reset signal φRST is activated and accumulator 4b
Is cleared to 0. Then, in response to the activation of the reset signal φRST, the black period signal is activated, and the charges stored in the light-shielded pixels of the light-shielded pixel portion 1b are read out according to the clock signal CLK. The black level reference analog signal of the light-shielded pixel output from the light receiving element array 1 is
The signal is converted into a digital signal in the A / D conversion circuit 3.
FIG. 3 shows that the 8-bit AD output signal from A / D conversion circuit 3 is output at twice the cycle of clock signal CLK.

The AD output signal from the A / D conversion circuit 3 is applied to an adder 4a. The adder 4a calculates the AD
The output signal is added to the value stored in the accumulator 4b, and the result of the addition is added to the accumulator 4b. When the accumulation signal φACM is activated, the accumulator 4b
The 14-bit output value from the adder 4a is stored and output. Therefore, as shown in FIG. 3, when the digital reference signal from the first light-shielded pixel is “12H”, accumulator 4b stores digital reference value “12H” in accordance with accumulated signal φACM. Next, when the AD output signal is “13H”, the adder 4a adds the pixel value “12H” stored in the accumulator 4b to the newly given AD output signal (digital reference signal). This addition result "25H" is stored again in accumulator 4b according to accumulation signal φACM. This accumulation operation is 6
Execute four times. That is, at least 64 light-shielded pixels in the light-shielded pixel section 1b are arranged to derive a black level reference signal. These 64 light-shielded pixels may be a part of a plurality of light-shielded pixels included in the light-shielded pixel portion 1b.

The output signal of accumulator 4b is applied to right shifter 4c, and a 6-bit right shift operation is performed to divide output value of accumulator 4b by coefficient 64. After performing the accumulation operation 64 times, the black latch signal φBL
Is activated, and the black level latch circuit 4d
The output value of c is latched. FIG. 3 shows a state where the value “0B” obtained by dividing the stored value “2C9” of the accumulator 4b by the coefficient 64 is latched as the black level value. The output value of the black level latch circuit 4d is, for example, 8 bits.

When the black latch signal φBL is activated, the black period signal is deactivated, the valid pixel period signal is activated, and the signal of the valid pixel from the valid pixel array 1a is read / output. . The A / D conversion circuit 3
Then, the black level value latched by the black level latch circuit 4d is subtracted from the AD output signal from the CPU. When the subtraction result is non-negative, the carry is "1", and the selector 4g selects the output value of the subtractor 4e and outputs it as a pixel digital output P2. On the other hand, when the AD output signal is 09, for example, the black level latched by the black level latch circuit 4d is “0B”, which is higher than the AD output signal. In this case, the carry of the subtractor 4e becomes "0", indicating that the subtraction result is negative. In this case, the selector 4e selects and outputs 8-bit 0 (00H) from the literal zero circuit 4f. Therefore, the minimum scale of the black level of the effective pixel is “00H”.
(Saturated). Thereby, the lowest level of the corrected digital pixel signal PD can be set to “00H”.

The A / D conversion circuit 3 is operated for both the light-shielded pixel and the effective pixel, and the black level reference signal from the light-shielded pixel is converted into a digital signal to set the black level. Therefore, the black level correction circuit 4 is a digital circuit, and does not require operations required for an analog circuit such as adjustment of circuit parameters when setting a black level, and performs accurate black level correction. Can be.

The digital black level correction circuit 4 is a digital circuit, and can set the same black level step of the digital signal of the A / D conversion circuit 3 to be stored in the black level latch circuit 4d. Black level correction can be performed.

In the above embodiment, A /
The D conversion circuit 3 generates an 8-bit AD output signal, and the adder 4a generates a 14-bit output value. However, the bit widths are not particularly limited to these values.

The subtractor 4e may be configured to perform the subtraction operation only when the effective pixel period signal is activated.

In order to calculate the black level, the output values of the light-shielding elements represented by a power of 2 of 64 are accumulated, and the dividing circuit is constituted by the right shifter 4c to simplify the circuit structure. However, even when the number of accumulations is not a power of 2, the average value of the digital reference signal from the light-shielded pixel can be similarly obtained by using a divider instead of the shifter.

FIG. 4 is a diagram schematically showing a configuration of a portion for generating a control signal used in the black level correction circuit. In FIG. 4, a black level correction control signal generation circuit 12
Is an effective pixel completion instruction signal φ from a readout control circuit 10 for controlling readout / output of a pixel signal from the light receiving element array 1.
It is started according to F. The read control circuit 10 controls reading of pixel data in the light receiving element array 1 according to a clock signal CLK. This read control operation includes:
There are operations of transferring pixel signals in the vertical direction and sequentially outputting pixel signals in the horizontal direction. At the time of vertical transfer, the selection of the light receiving element is performed for each row. When the selection operation of the last row in the vertical direction is performed and then the output circuit reads the pixel data of the last row, read control circuit 10
Activates the effective pixel completion instruction signal φF in accordance with the output of the pixel data of the last light receiving element in the last row.

A black level correction control signal generation circuit 12 generates a reset signal φRST in accordance with an effective pixel completion instruction signal φF from the read control circuit 10.
And reset signal φRS from reset circuit 12a.
In response to the activation of T, a black level control circuit 12b that generates a black period signal φBC and a black latch signal φBL, and activated in response to activation of a black period signal φBC from the black level control circuit 12b, An accumulation control circuit 12c for outputting an accumulation signal φACM in accordance with a clock signal CLK; an activation control circuit 12c which is activated in response to inactivation of a black period signal to activate an effective pixel period signal φVP;
Includes a correction control circuit 12d that resets in response to activation of.

The black level control circuit 12b counts the clock signal CLK, activates the black period signal φBC while supplying the output of the light-shielded pixel used for calculating the black level, and deactivates the black period signal φBC. The black latch signal φBL is activated in the clock cycle of the activation. When the black period signal φBC is activated, the accumulation control circuit 12c
An accumulation signal φACM is generated according to a clock signal CLK. Correction control circuit 12d is formed of, for example, a set / reset flip-flop, is set in response to inactivation of black period signal φBC, and outputs valid pixel completion instruction signal φ.
It is reset in response to the activation of F, and activates the effective pixel period signal φVP while the pixel signal from the effective pixel is supplied from the A / D conversion circuit.

The black level correction control signal generating circuit shown in FIG. 4 does not consider the delay of the number of clock cycles due to the timing delay in the gamma correction circuit and the A / D conversion circuit. The generation period of each control signal of the black level correction control signal generation circuit 12 is adjusted in consideration of these factors.

[Second Embodiment] FIG. 5 is a diagram showing a configuration of a digital black level correction circuit according to a second embodiment of the present invention. The digital black level correction circuit shown in FIG. 5 differs from the configuration shown in FIG. 2 in the following points. That is, the reset signal φ is output to the output of the adder 4a.
A black level latch circuit 4d whose storage content is updated according to RST and accumulation signal φACM is provided. The output value of the black level latch 4b is output to the right shifter 4c and the adder 4
a to the input. The right shifter 4c shifts the output signal of the 14-bit black level latch circuit 4d rightward by 6 bits to generate 8-bit data, and generates the 8-bit data.
Give to. The other configuration is the same as the configuration shown in FIG.
Corresponding parts have the same reference characters allotted, and detailed description thereof will not be repeated.

In the digital black level correction circuit shown in FIG. 5, a black level latch circuit 4d is provided instead of the accumulator 4b. The black level latch circuit 4d
In response to activation of reset signal φRST, the contents of the latch are reset to 0, and the output value of adder 4a is latched in accordance with accumulation signal φACM.

Therefore, the operation of the digital correction circuit shown in FIG. 5 is the same as the operation shown in the timing chart of FIG. By giving the output value of the black level latch circuit 4d to the right shifter 4c, the output value of the right shifter 4c is latched accordingly, so that the black level value is stably held for valid pixels. Normally, right shifter 4c
Is realized by wiring, and if a latch circuit is provided at the input portion, the output signal is also in the latch state. Therefore, since the accumulator 4b is also used as a black level latch circuit, the number of circuit components is reduced, and a circuit configuration suitable for high integration can be realized.

The control signal generation circuit for the digital black level correction circuit shown in FIG. 5 uses the black latch instruction signal φBL from the black level control circuit 12b in the configuration of the black level correction control signal generation circuit shown in FIG. What is necessary is just to delete the generated part.

As described above, according to the second embodiment of the present invention, the circuit for latching the output value of the adder is shared with the circuit for latching the black level value applied to the input of the subtractor. The number of circuit components can be reduced, and accordingly the circuit occupation area and power consumption can be reduced.

[Third Embodiment] FIG. 6 is a diagram schematically showing a configuration of a digital black level correction circuit according to a third embodiment of the present invention. In FIG. 6, a digital black level holding circuit includes an adder 4a for receiving an 8-bit digital pixel signal from the A / D conversion circuit 3, a black level latch circuit 4d for latching an output value of the adder 4a, Right shifter 4h that shifts the output value of latch circuit 4d rightward
And an inverting circuit 4i for inverting all output bit values of the right shifter 4h, a literal one circuit 4n for generating a one-bit fixed value "1", and a literal zero circuit 4m for outputting a one-bit fixed value "0". And a selection circuit 4j for selecting one of the black level value and its complement according to the black period signal φBC and the effective pixel period signal φVP.

The selection circuit 4j outputs the effective pixel period signal φVP
And a switch circuit SW2 for selecting an output value of the inversion circuit 4i and supplying the same to the adder 4a according to the following equation: a switch circuit SW2 for selecting an output signal of the black level latch circuit 4d according to the black period signal φBC and providing the same to the adder 4a; A switch circuit SW3 for selecting a 1-bit fixed value “1” output from the literal one circuit 4n according to the period signal φVP and supplying the same to the carry-in input of the adder 4a, and a black period signal φBC
And a switch circuit SW4 for selecting a fixed value "0" output from the literal zero circuit 4n in response to the activation of the adder 4a and applying the same to the carry input of the adder 4a.

The digital black level correction circuit 4 further includes
A selector 4g for selecting one of the output value of the adder 4a and one of the literal zero circuits 4f according to the carry of the adder 4a to generate a pixel digital output PD is included. Next, the operation will be described.

The operation of the digital black level correction circuit 4 shown in FIG. 6 is substantially the same as the waveform diagram shown in FIG.

A new image (frame or field,
Before reading the effective pixel array), the reset signal φR
ST is activated, and the black level value latched by the black level latch circuit 4d is reset to 0. Further, switch circuits SW2 and SW4 conduct according to black period signal φBC, apply fixed value “0” from literal zero circuit 4m to carry input of adder 4a, and apply black level latch circuit 4m.
The output value of d is selected and given to the adder 4a. Therefore, when the black period signal φBC is activated, the adder 4a
The digital pixel signals supplied from the A / D conversion circuit 3 are added and stored in the black level latch circuit 4d. Therefore, the accumulation signal φAC is applied to the black level latch circuit 4d.
The digital reference signal of the light-shielded pixel is accumulated according to M.

In accordance with final accumulation signal φACM, the latch operation in black level latch circuit 4d is completed.

Next, when the effective pixel period starts, the switch circuits SW1 and SW are switched according to the effective pixel period signal φVP.
3, the output value of the inverting circuit 4i and the output value of the literal one circuit 4n are selected and supplied to the adder 4a. The right shifter 4h divides the accumulated value of the digital reference signal output from the 64 light-shielded pixels stored in the black level latch circuit 4d by the accumulation count. Inverting circuit 4i
Inverts each bit of the output value of the right shifter 4h. Accordingly, the inversion circuit 4i outputs the black level value of 1
Is output. On the other hand, the fixed value "1" from the literal one circuit 4n is added to the adder 4 via the switch circuit SW3.
a to the carry input. That is, the inversion circuit 4
Since one is added to the one's complement value from i, the two's complement value of the black level value is given to the adder 4a. The adder 4 a adds the two's complement value of the black level and the digitally converted AD output signal of the effective pixel from the A / D conversion circuit 3. That is, the adder 4a subtracts the black level value from the signal output from the effective pixel. When the result of the addition is negative, ie, the subtraction value is minus, the carry becomes "0", and the selector 4g selects 8-bit 0 from the literal zero 4f and outputs it as a pixel digital output PD. When the output value of the adder 4a is non-negative, the carry is "1", and the selector 4g selects the output value of the adder 4a. Therefore, the effective pixel data corrected for the black level is obtained as a pixel digital output.

In the configuration shown in FIG. 6, an adder for calculating the black level is also used as a subtractor for correcting the black level. Therefore, the circuit scale can be further reduced, and an arrangement suitable for high integration can be realized.

In the black level correction circuit shown in FIG. 6, when processing the effective pixel signal, the adder 4a is used.
Are given a fixed value "0" from the literal zero. However, image processing such as adding a predetermined offset value using the carry input can also be realized.

As described above, according to the third embodiment of the present invention, since the adder for calculating the black level and the subtractor for correcting the black level are shared, the circuit scale can be reduced. Can be.

[Fourth Embodiment] FIG. 7 is a diagram schematically showing a configuration of a digital black level correction circuit according to a fourth embodiment of the present invention. In the digital black level correction circuit 4 shown in FIG. 7, an offset register 4p for storing an externally applied offset value and an offset register 4 based on an output value of a right shifter 4c for calculating a black level value.
Further provided is a subtractor 4q for subtracting the offset value stored in p and providing the subtraction result to the subtractor 4e. The other configuration is the same as that shown in FIG. 5, and the corresponding parts are denoted by the same reference numerals and detailed description thereof will not be repeated.

The operation of the digital black level correction circuit shown in FIG. 7 is the same as the operation shown in the timing chart shown in FIG. Further, the black level value subtracted from the output value of the effective pixel in the subtractor 4e is corrected by the offset value stored in the offset register 4p. The black level value output from the right shifter 4c is an average value of the output values of the plurality of light-shielded pixels. Normally, the black level signal has a statistically Gaussian distribution, and centered around 0,
The value of the black level signal is also distributed in the negative direction. A variation similar to the variation of the black level signal of the light-shielded pixel also occurs in the black level signal of the effective pixel (since they are integrated on the same substrate and these elements have the same characteristics). Therefore, when the variation of the black level signal is large, if the black level signal smaller than the average value of the black level signal is saturated to “0” by the selector 4g,
In the Gaussian distribution, the distribution of the black level signal distributed in the negative direction is ignored, and the variation of the black level signal cannot be reflected on the captured image.

Therefore, an estimated value of, for example, a half width of the variation of the black level signal is calculated and stored as an offset value in the offset register 4p. Therefore, the black level reference value used for correcting the black level in the subtractor 4e is a value that is smaller than the average value of the black level signal by the offset value, and can reflect the signal distribution of the black level signal. . This enables more accurate black level correction.

This offset value is written into the offset register 4p from a control circuit provided outside (outside the semiconductor integrated circuit on which the image sensor is formed). As this offset value, for example, one offset value may be selected from a plurality of offset values prepared in advance according to the imaging conditions and written into the offset register 4p. The user may selectively set the imaging conditions under the conditions for actually imaging. Further, the control circuit may detect the illuminance or the like in the use environment, and the offset value may be calculated according to a predetermined calculation rule in accordance with the detected imaging condition. Also, when imaging is performed for a long time, such as in measurement applications,
For example, a variation in the black level signal during the black level correction period may be detected for each of a plurality of frames, and the offset value may be corrected according to the detected variation.
As a parameter indicating the variation, detection of a maximum value and a minimum value, and their subtraction value (width of variation)
May be used.

As described above, according to the fourth embodiment of the present invention, since the black level correction is performed by offsetting the black level value, even if the variation in the black level signal is large. , A black level signal reflecting this variation can be generated.

[Fifth Embodiment] FIG. 8 shows a structure of a black level correction circuit according to a fifth embodiment of the present invention. In the configuration shown in FIG. 8, in addition to digital black level correction circuit 4, an analog black level correction circuit 20 for performing analog black level correction on analog pixel signals read from the light receiving element array is provided. Can be

The analog black level correction circuit 20 compares the analog pixel signal read from the light receiving element array with the potential charged in the clamp capacitor 20a, and activates the clamp signal φCLP. And a control circuit 20c that is activated and generates a control signal according to the output signal potential of differential amplifier 20b, and variable current sources 20d and 20e that adjust the charging potential of clamp capacitor 20a according to the output signal of control circuit 20c. . The control circuit 20c adjusts the supply current of the variable current sources 20d and 20e so that the output signal of the differential amplifier 20b has the potential 0 when the clamp φCLP is activated, and adjusts the charging potential of the clamp capacitor 20a. I do.

The digital black level correction circuit 4 has the same configuration as the configuration shown in FIG. 5. Corresponding portions have the same reference characters allotted, and detailed description thereof will not be repeated.

Next, the operation of the black level correction circuit shown in FIG. 8 will be described with reference to a timing chart shown in FIG.

Prior to reading out the effective pixel signal, the black level is adjusted. First, the reset signal φRST is activated, and the black level value latched by the black level latch circuit 4d is reset to 0. Next, the black period signal φBC
Is activated, and a signal is read from the light-shielded pixel. Along with the activation of the black period signal φBC, the clamp signal φCLP is activated, and the analog black level correction circuit 20 is activated. During this period, the accumulation signal φACM is in the inactive state, and the digital black level correction circuit 4 maintains the initial state. In the analog black level correction circuit 20, the control circuit 20c operates the differential amplifier 20b in accordance with a black level reference analog signal read from the light-shielded pixel.
The charging potential of the clamp capacitor 20a is adjusted so that the output potential of the clamp capacitor 20a becomes zero. When the analog black level potential is determined by a black level reference signal from a predetermined number of light shielding elements, the clamp signal φCLP is deactivated, and the control circuit 20 c
The black level adjustment operation is stopped, and the charged potential of the clamp capacitor 20a is held. This is realized by simply stopping the charge / discharge operation of the unit current sources 20d and 20e. Through a series of these operations, the analog black level potential is determined.

When the clamp signal φCLP is deactivated, the digital black correction signal φDBC is subsequently activated. The digital black level correction circuit 4 is activated according to the digital black correction signal φDBC. In the analog black level correction circuit 20, the differential amplifier 20b generates an analog correction signal obtained by subtracting the charging potential of the clamp capacitor 20a from the analog pixel signal, and supplies the analog correction signal to the A / D conversion circuit 3. During the activation period of the digital black correction signal φDBC, as in the previous embodiment, after the black level reference signals from the 64 light-shielded pixels are subjected to analog black level correction by the analog black level correction circuit 20, A The digital reference signal is supplied to the digital black level correction circuit 4 via the / D conversion circuit 3 as a digital reference signal.

Adder 4a and black level latch circuit 4d
As a result, a digital reference signal whose black level has been corrected in an analog manner is accumulated. When the accumulation signal φACM is activated 64 times, the sum of the digital reference signals from the 64 light shielding elements is latched by the black level latch circuit 4d. The right shifter 4c sets the output value of the black level latch circuit 4d to 6
Bits are shifted rightward to perform division by a coefficient of 64. Therefore, a digital black level value is output from the right shifter 4c. In FIG. 9, “11B” is latched in the black level latch circuit 4d, and the right shifter 4
A state where the black level value from c is set to “04” is shown as an example.

When this digital black level value is determined,
The digital black correction signal φDBC is deactivated, the valid pixel period signal φVP is subsequently activated, and the reading of the signal of the valid pixel from the valid pixel array and the black level correction are performed.

In the analog black level correction circuit 20, black level correction is performed in an analog manner, and subsequently, in the digital black level correction circuit 4, the black level is further digitally corrected. In the digital black level correction circuit 4, when the digital signal value of the effective pixel is smaller than the black level value from the right shifter 4c, the subtracter 4e
Becomes "0", the selector 4g selects "0" from the literal zero circuit 4f, and the black level value is clamped to "00H".

The analog black level correction circuit 20 performs analog black level correction and then digitally performs black level correction, so that the black level correction can be accurately performed. Further, by performing analog black level correction, the black level value can be set close to the minimum value, and the number of effective bits of the digital black level value in the digital black level correction circuit can be reduced. The scale can be reduced.

FIG. 10 is a diagram schematically showing a configuration of a portion for generating a signal used in the black level correction circuit shown in FIG.

In FIG. 10, the black level correction control signal generating section 22 reads out the light receiving element array 1 with a clock signal C.
A reset control circuit 22a that outputs a one-shot reset signal φRST in response to an effective pixel read completion instruction signal φF from a read control circuit 10 that controls according to LK;
A black level control circuit 22b that counts clock signal CLK in response to activation of reset signal φRST and outputs a black period signal φBC that is active for a predetermined period, and responds to activation of black period signal φBC , Clock signal C
An analog clamp control circuit 22c that counts LK and outputs an analog clamp signal φCLP that is active for a predetermined period, and a digital black correction that is active for a predetermined period (64 pixels) in response to the inactivation of the clamp signal φCLP. Digital clamp control circuit 2 for outputting signal φDBC
2d and an effective pixel period signal φVP that is activated in response to the inactivation of the digital black correction signal φDBC output from the digital clamp control circuit 22d and reset in response to the activation of the effective pixel completion instruction signal φF. Is output.

The digital clamp control circuit 22d outputs an accumulation signal φACM according to the clock signal CLK when the digital black correction signal φDBC is activated.

Each of the black level control circuit 22b and the analog clamp control circuit 22c is formed of, for example, a counter for counting the clock CLK. The digital clamp control circuit 22d is also formed of a counter for counting the clock signal CLK. Correction signal φ
Output DBC. Accumulation signal φACM is generated, for example, by a T flip-flop whose output value changes at the rise of clock signal CLK, for example, when digital black correction signal φDBC is activated.

In the digital black correction circuit 4, the addition operation of the adder 4a may be configured to be stopped when the effective pixel period signal φVP is activated. Further, A / D conversion circuit 3 may be configured to be inactivated during an analog clamp period in which clamp signal φCLP is in an active state. During the analog clamp period, the light-shielded pixel portion 1b
Are appropriately determined according to the number of light-shielded pixels used for the analog black level correction among the light-shielded pixels included in.
The light-shielded pixel used for the analog black level correction and the light-shielded pixel used for the digital black level correction need only read other signals continuously, may be arranged in one row, or may be arranged in a plurality of rows. It may be arranged as.

In the fifth embodiment, the digital black level correction circuit has the same configuration as that shown in FIG. However, a digital black level correction circuit used in combination with this analog black level correction circuit is:
The digital black level correction circuit shown in FIGS. 2, 6, and 7 may be provided.

The light-shielded pixel section 1b is disposed at the head of the effective pixel array 1a in the vertical direction.
The black level correction may be performed in units of a. However, as shown in FIG. 11, a light-shielding pixel portion 1c is further provided,
A predetermined number of light-shielded pixels may be arranged corresponding to each row of the effective pixel array 1a, and the digital black level may be corrected for each row. The black level correction may be performed using the light-shielded pixels of the light-shielded pixel portion 1c during the horizontal period erasing period of the so-called captured video signal.

The light receiving pixels included in the light receiving element array 1 only need to have a function of converting an optical signal into an electric signal.

In the fifth embodiment, no particular reference is made to the position of the gamma correction circuit. However, this gamma correction circuit may be provided either before or after the analog black level correction circuit 20.

[0095]

As described above, according to the present invention, since the black level correction of the signal read from the light receiving element array is performed digitally, fine adjustment of circuit parameters for black level adjustment is performed. There is no need to perform this operation, and the black level value can be accurately set and the black level correction can be easily performed accurately.

That is, according to the first aspect of the present invention,
Generating and holding a black level reference digital signal based on the digital pixel signal from the analog / digital conversion circuit,
The level of the effective pixel digital signal from the light receiving element is corrected by the black level reference digital signal, and one of the output value of the level correction circuit and a predetermined clamp value is selectively output according to the sign of the output value of the level correction circuit. With this configuration, black level saturation processing can be easily performed with a simple circuit configuration, and since digital black level correction is performed, adjustment of circuit parameters such as response characteristics is unnecessary. Thus, accurate black level correction can be performed.

According to the invention of claim 2, the black level clamp value is set to 0, and the black level saturation value can be set to the lowest level.

According to the third aspect of the present invention, since the average value of the black level reference digital signals from the plurality of light-shielded pixels is output as the black level value, almost accurate black level values can be set. .

According to the fourth aspect of the invention, since the black level reference value is corrected by the offset value, when the variation in the black level value is large, the black level correction reflecting the variation can be performed. Image quality can be improved.

According to the fifth aspect of the present invention, the black level reference digital signal is composed of an adder circuit, an accumulator (accumulation register) and a division circuit, and can accurately calculate the black level value with a simple circuit configuration. Can be generated.

According to the sixth aspect of the present invention, a latch is provided at the output of the adder circuit, and the latch output is applied to a divider circuit so that the divider circuit outputs a black level reference digital signal, that is, a black level value. With this configuration, the register for latching the output of the adder circuit and the register for latching the output value of the divider circuit can be shared, and the circuit scale is reduced.

According to the seventh aspect of the present invention, since the output value of the division circuit is latched and the black level reference digital signal is output, the black level reference digital signal is stably held and output. can do.

According to the eighth aspect of the present invention, the adder is used in common for black level correction and black level reference digital signal generation, and a circuit for latching the output value of the adder is provided. Complementary values with inverted signs are generated, and when an effective pixel digital signal and a light-shielded pixel digital signal are applied, the complementary circuit and the output of the latch circuit are applied to the addition circuit. An adder for generating a black level value can be shared, and the circuit scale is reduced.

According to the ninth aspect of the present invention, a circuit for performing analog black level correction is further provided in the preceding stage of the analog / digital conversion circuit, and the analog black level correction circuit performs black level correction based on the output value of the light-shielded pixel. The configuration is such that the variation of the black level value in the digital level correction circuit is small, the number of effective bits can be reduced, and the scale of the digital black level correction circuit can be reduced.

According to the tenth aspect of the present invention, the black level value, that is, the number of light-shielded pixels used for generating the black level reference digital signal is a power of two, and the accumulation result of the digital reference signal of this light-shielded element is calculated. Because it is given to the shifter,
The division circuit can be realized by a shifter that simply performs a bit shift operation, high-speed division can be realized, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram schematically showing a configuration of a digital black level correction circuit according to Embodiment 1 of the present invention.

FIG. 3 is a timing chart showing an operation of the digital black level correction circuit shown in FIG. 2;

4 is a diagram schematically showing a configuration of a generation unit of a black level correction control signal shown in FIG. 3;

FIG. 5 is a diagram schematically showing a configuration of a digital black level correction circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram schematically showing a configuration of a digital black level correction circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram schematically showing a configuration of a digital black level correction circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram schematically showing a configuration of a digital black level correction circuit according to a fifth embodiment of the present invention.

FIG. 9 is a timing chart showing an operation of the digital black level correction circuit shown in FIG. 8;

10 is a diagram schematically showing a configuration of a generation unit of a black level correction control signal shown in FIG. 9;

FIG. 11 is a diagram schematically showing another configuration of the light receiving element array.

FIG. 12 is a diagram schematically showing a configuration of a conventional light receiving element array.

FIG. 13 is a diagram illustrating an example of a configuration of a conventional light receiving element.

FIG. 14 is a diagram illustrating a relationship between a charge accumulation time and an output potential in an image sensor.

FIG. 15 is a diagram schematically showing a configuration of a conventional image sensor.

[Explanation of symbols]

1 light receiving element array, 1a effective pixel array, 1b, 1
c light-shielded pixel section, 2 gamma correction circuit, 3 A / D conversion circuit, 4 digital black level correction circuit, 4a adder, 4b
Accumulator, 4c right shifter, 4d black level latch circuit, 4e subtractor, 4f literal zero circuit, 4c
g selector, 4h right shifter, 4i inversion circuit, SW
1 to SW4 switch circuit, 4j selection circuit, 4p offset register, 4q subtractor, 20 analog black level correction circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C051 AA01 BA03 DA06 DB01 DC03 DC07 DE03 DE15 DE17 5C072 AA01 BA17 DA15 EA05 EA08 FB15 FB21 FB25 FB27 LA15 RA15 UA06 UA11

Claims (10)

[Claims] 1. A light-receiving element array that is arranged in an array and includes a light-receiving element that converts an optical signal into an analog electric signal, and a light-blocking element that generates a black level reference signal. An analog / digital conversion circuit for converting an analog electric signal into a digital signal, receiving a digital reference signal corresponding to the black level reference signal from the analog / digital conversion circuit, generating and holding a black level reference digital signal A black level holding circuit, receiving an effective pixel digital signal corresponding to an analog electric signal output from the analog / digital conversion circuit from the light receiving element, and correcting the level of the received effective pixel digital signal according to the black level reference digital signal A level correction circuit for correcting the output value of the level correction circuit and a predetermined black level. A semiconductor integrated circuit comprising a saturation processing unit for receiving one of the output value of the level correction circuit and selecting one of the output value of the level correction circuit and the black level clamp value according to the sign of the output value of the level correction circuit and outputting the selected digital value as a pixel digital signal . 2. The semiconductor integrated circuit according to claim 1, wherein said black level clamp value is equal to zero. 3. The semiconductor according to claim 1, wherein the black level holding circuit includes a circuit that calculates an average value of the plurality of black level reference digital signals and outputs the average value as the black level reference digital signal. Integrated circuit. 4. The black level holding circuit, a circuit for calculating an average value of the plurality of black level reference digital signals, an offset register for storing an offset value, and correcting the average value with the offset value. 2. The semiconductor integrated circuit according to claim 1, further comprising: an offset circuit that outputs the black level reference digital signal. 5. The black level holding circuit, comprising: a two-input adding circuit receiving the digital reference signal at a first input; accumulating an output value of the adding circuit; 2. The semiconductor integrated circuit according to claim 1, further comprising: an accumulating circuit that supplies the input to the second input; and a dividing circuit that divides the accumulated value of the accumulating circuit by the number of accumulations of the accumulating circuit. 6. The semiconductor integrated circuit according to claim 5, wherein said black level reference digital signal is output from said division circuit, and said accumulation circuit has a latch function. 7. The semiconductor integrated circuit according to claim 5, wherein said black level holding circuit further comprises a latch circuit for latching an output value of said division circuit and outputting said black level reference digital signal. 8. The level correction circuit includes an adder, the black level holding circuit includes a latch circuit for latching an output value of the adder, and a complement circuit that inverts a sign of the output value of the latch circuit. A circuit for generating a numerical value, receiving an output value of the analog / digital conversion circuit, selecting the complement value when applying the effective pixel digital signal,
And a selection circuit that selects an output value of the latch circuit when the digital reference signal is applied, wherein the adder adds an output value of the analog / digital conversion circuit and an output value of the selection circuit. 2. The semiconductor integrated circuit according to 1. 9. A black level reference signal is received from the light shielding element, a black level correction signal for an input valid pixel analog electric signal is generated and held, and the valid pixel analog electric signal is subjected to black level correction to perform the analog / digital conversion. An analog black level correction circuit provided to a digital conversion circuit, wherein the black level holding circuit starts an operation of generating the black level reference digital signal after a black level clamping operation of the analog black level correction circuit is completed. 2. The semiconductor integrated circuit according to 1. 10. A black level holding circuit, comprising: an accumulating circuit for accumulating digital reference signals from power-of-2 light-shielding elements; and dividing an output value of the accumulating circuit by a shift operation of its bit position. 2. The semiconductor integrated circuit according to claim 1, further comprising: a shifter.