JP2000332111A - Wiring forming method, multilayer wiring board, and semiconductor device - Google Patents

Abstract

(57) Abstract: In a method of forming wiring using a damascene process, a polishing end can be easily detected without being influenced by mechanical factors, and a surface of a polishing target is easily machined. An object is to realize a highly conductive wiring. SOLUTION: A wiring groove 12 patterned into a required shape and a via hole 13 reaching the lower wiring layer 10 are formed in an interlayer insulating film 11 formed on a lower wiring layer 10 by a damascene process. Forming a first conductor layer 14, further forming a second conductor layer 15 so as to fill the wiring groove 12 and the via hole 13, and polishing and flattening the surface of the conductor layer 15 by mechanical polishing. First conductor layer 14
When the surface of the first conductive layer 14 is exposed, the polishing is stopped, and only the exposed first conductive layer 14 is removed by etching.
6 and 17 are left as the wiring 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming technique, and more particularly to a method for forming a wiring using a damascene process, in which a wiring material is buried in a wiring groove of an interlayer insulating film and then polished for planarization. The present invention relates to a technique useful for facilitating detection of the polishing end when performing the polishing.

[0002]

2. Description of the Related Art In recent years, multi-layered wiring and finer wiring have been developed due to higher integration and higher speed of LSI. In particular, in logic devices, in order to realize high performance transistor characteristics, it is necessary to reduce the minimum pitch of wiring in accordance with the gate length, and furthermore, a wiring structure that can withstand use conditions at high current density is required. Is done. When the wiring pitch is reduced, the signal delay caused by the inter-wiring capacitance and wiring resistance, which has not been considered so much, cannot be ignored. In order to avoid this, it is necessary to use a wiring material having a low resistivity and an interlayer insulating film having a low dielectric constant.

Conventionally, aluminum (Al) has been used as a wiring material. Recently, however, copper (C) capable of realizing a low wiring resistance with the same wiring cross-sectional area as compared with Al has been used.
u) is used. Cu can have the same wiring pitch and the same wiring resistance as Al and can reduce the thickness of the wiring, and as a result, the capacitance between wirings can be reduced. But C
When a multilayer wiring is formed using u, it is necessary to etch Cu or bury an interlayer insulating film, and there is a problem that such processing cannot be easily performed with the current technology.

Therefore, as a technique for forming a wiring, a "damascene" which does not require Cu etching instead of the dry etching technique used in the conventional Al wiring technique.
Is becoming mainstream. There are single damascene and dual damascene. Single damascene
A groove serving as a wiring is formed in the interlayer insulating film by etching,
Further, a barrier metal layer as a diffusion prevention layer is deposited, and a Cu film is deposited thereon. Then, Cu and the barrier metal on the upper part of the wiring groove are removed by chemical mechanical polishing (CMP) to be flattened to form a wiring. Method. On the other hand, in the dual damascene, via holes for making electrical contact with the lower wiring layer are formed at the same time as the wiring grooves, and the barrier metal layer, the Cu film, and the CMP are performed once, respectively, to form the wiring and the via plug. Are simultaneously formed.
Then, by repeating these steps until the required number of layers is reached, a multilayer wiring can be formed.

[0005] As described above, in the damascene process, regardless of whether the damascene process is single damascene or dual damascene, when the wiring material (Cu) is buried in the wiring groove and the via hole,
Processing for flattening by mechanical processing such as CMP is required.

[0006]

As described above, in the conventional method of forming a wiring by the damascene process, after embedding a wiring material in an interlayer insulating film, polishing for flattening (CM).
Although P) is performed, the current technology has a problem that the polishing end cannot be easily detected. Specifically, since the apparatus for performing CMP has a rotating system structure, noise due to mechanical vibration occurs, and this noise hinders detection of the polishing end.

Further, since the polishing end cannot be easily detected, it is extremely difficult to stop the polishing end point within an appropriate level. Therefore, for example, in the case of over-polishing (excessive shaving), there is a problem that the wiring becomes thin (that is, the wiring cross-sectional area becomes small) and the wiring resistance increases. This leads to a decrease in the conductivity of the wiring, and loses the meaning of employing Cu as the wiring material. On the other hand, in the case of underpolishing (remaining shaving), a problem arises in that a leak current is generated due to the remaining part of the barrier metal layer, and in some cases, a short circuit is caused.

Further, since Cu and the barrier metal are simultaneously polished, a difference in hardness between Cu and the barrier metal (in general, Cu is softer) is called "dishing" on the wiring (Cu). Depressions (recesses) occur. If the wiring width is relatively wide, dishing similarly occurs on the wiring due to mechanical factors such as the rotational speed of the pad and the bending due to the soft pad.

As described above, in the conventional wiring forming method using the damascene process, it is difficult to detect the end of polishing, so that the end point of polishing cannot be stopped at an appropriate level, and the surface of the object to be polished is flattened. However, there is a problem that patterning can be performed only on a fairly flat substrate. The present invention has been made in view of the problems in the related art, and makes it possible to easily detect the end of polishing without being influenced by mechanical factors, thereby facilitating machining of the surface to be polished, An object of the present invention is to provide a wiring forming method capable of realizing high wiring.

Another object of the present invention is to provide a multilayer wiring board and a semiconductor device manufactured by using the above wiring forming method.

[0011]

According to one aspect of the present invention, an interlayer insulating film formed on a lower wiring layer is patterned into a required shape. A first step of forming a wiring groove having a bottom by a damascene process, a second step of forming a first conductive layer on the interlayer insulating film including the wiring groove, and filling the wiring groove. A second layer on the first conductor layer.
A third step of forming a conductive layer of the second conductive layer, and a fourth step of polishing and flattening the surface of the second conductive layer by mechanical polishing to expose the surface of the first conductive layer on the interlayer insulating film. And a fifth step of etching and removing the exposed first conductive layer.

According to the wiring forming method of the present invention, the second
In the process of polishing and flattening the surface of the conductor layer by mechanical polishing, when the surface of the first conductor layer is exposed, the polishing is stopped, and only the exposed first conductor layer is etched away. As a result, only the intended wiring portion can be left. That is, the first conductor layer (portion that has not been removed by etching) embedded in the wiring groove patterned into a required shape and the second conductor layer (portion that has not been removed by etching) laminated thereon 2 The conductor layer having a layer structure can be left as a wiring.

Here, the first conductor layer is used as a layer for detecting the end of polishing in the process of polishing and flattening the surface of the second conductor layer by mechanical polishing, and finally, the selective etching is performed. Is used as a part of the wiring. As described above, according to the present invention, since the first conductor layer is used as the polishing end detection layer, the end of polishing can be easily detected, and the end point of polishing can be stopped within an appropriate level. That is, when flattening, the degree of freedom (margin) can be given by the thickness of the end detection layer in the timing of stopping polishing by mechanical processing, the size of fine abrasive grains used for polishing, and the like. by this,
The surface of the second conductor layer to be polished is easily machined.

Further, if the timing of stopping the polishing is delayed due to a mechanical factor or the like, the polishing is terminated by the end detection layer (first conductor layer).
And the surface of the second conductor layer, the excessively shaved portion can be stopped within the range of the thickness of the termination detection layer, so that the second conductor layer is unnecessarily sharpened. Such inconveniences can be avoided. As a result, the problem that the wiring cross-sectional area decreases and the wiring resistance increases as in the related art can be solved. This contributes to the realization of highly conductive wiring.

According to another aspect of the present invention, there is provided a multilayer wiring board manufactured by using the above-described wiring forming method. Further, according to another aspect of the present invention, there is provided a semiconductor device in which a semiconductor element is mounted on a multilayer wiring board manufactured using the above-described wiring forming method.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a wiring according to an embodiment of the present invention will be described below with reference to FIG. First, in the first step (Fig. 1
(See (a)), a wiring groove 12 patterned into a required shape and a via hole 13 reaching the lower wiring layer 10 are formed in the interlayer insulating film 11 formed on the lower wiring layer 10 by a dual damascene process. .

As a dual damascene process, a method in which the wiring groove 12 is etched first and then the via hole 13 is etched, and a method in which the via hole 13 is etched first and then the wiring groove 12 is etched. Or a method in which the wiring groove 12 and the via hole 13 are formed by etching at a time by a self-alignment method.

The interlayer insulating film 11 preferably has a low dielectric constant as described above, and is preferably made of, for example, an inorganic material such as a plasma SiO ₂ film or a SiOF film. And an organic coating film typified by a fluorocarbon polymer or polyimide that can be formed by plasma CVD. In the next step (see FIG. 1B), a metal layer of aluminum (Al) is formed as a first conductive layer 14 on the entire surface by vapor deposition so as to cover the wiring groove 12 and the via hole 13. First conductor (Al) layer 14
Is used as a termination detection layer for polishing performed in a later stage, and constitutes a part of a finally formed wiring (layer).

In the next step (see FIG. 1C), copper (C) is formed as a second conductor layer 15 on the first conductor (Al) layer 14 so as to fill the wiring groove 12 and the via hole 13.
The metal layer of u) is formed by sputtering. Second
The conductor (Cu) layer 15 constitutes a main part of a finally formed wiring (layer). At the end of this step, the surface of the second conductor (Cu) layer 15 is not flat as shown in the figure, since only Cu deposition processing by sputtering has been performed.

In the next step (see FIG. 1D), the surface of the second conductor (Cu) layer 15 is polished and flattened by mechanical polishing, and the termination detection layer, that is, the first conductor (Al) layer 14 is formed.
Stop mechanical polishing when the surface of is exposed. As a result, the second conductor (Cu) layer whose surface has been flattened is left as the conductor layer 16 constituting the main part of the wiring (layer).

The mechanical polishing is performed by processing the surface of the object to be polished by mechanically pushing and scratching fine abrasive grains. Instead of this mechanical polishing, chemical mechanical polishing (CMP) may be used. In the last step (Fig. 1
(E), the exposed first conductor (A) which does not affect the exposed conductor (Cu) layer 16 (second conductor layer).
1) Selective etching is performed using a chemical solution that can dissolve only the layer 14. As the chemical solution, for example, hydrochloric acid can be used. By this step, of the first conductor (Al) layer,
Only the exposed portion is removed by etching, and the portion buried in the wiring groove 12 and the via hole 13 is not removed by etching as shown in FIG. Will be left as
Note that the exposed conductor (Cu) layer 16 remains as it is because it is not affected by the selective etching.

In this manner, a wiring (layer) 18 having a two-layer structure composed of the conductor (Cu) layer 16 and the conductor (Al) layer 17 so as to fill the wiring groove 12 and the via hole 13 patterned in a required shape. Is formed. As described above, according to the wiring forming method of the present embodiment, when the surface of the second conductor layer 15 is polished and flattened by machining, the end of the first conductor layer 14 is detected by polishing. Because it is used as a layer, it is easy to detect the polishing end,
The end point of polishing can be stopped within an appropriate level. That is, when flattening, the degree of freedom in selection of timing for stopping polishing by mechanical processing, the size of fine abrasive grains used for mechanical polishing, and the like is determined by the thickness of the end detection layer (first conductive layer 14). (Margin). This makes it easy to machine the surface of the second conductor layer 15 to be polished.

For example, at the stage of flattening by mechanical polishing (step of FIG. 1D), ideally, the first conductor layer 1 is formed.
4 and the surface of the conductor layer 16 (the second conductor layer) are completely flattened in the same plane, but in actuality, mechanical polishing is performed by mechanical pressing and scratching of fine abrasive grains. There is a possibility that the surface of the conductor layer 16 may have scratches or the like at the time of stopping, and the surface may not be strictly flattened. In such a case, a slight uneven portion is formed on the surface of the conductor layer 16 constituting the main portion of the wiring (layer), and the final thickness of the wiring (layer) 18 depends on the uneven portion. Will fluctuate. On the other hand, in the present embodiment, since the first conductor layer 14 is provided as the termination detection layer, a variation in the thickness of the wiring (layer) can be absorbed by the thickness of the termination detection layer.

Further, if the timing of stopping the polishing is delayed due to mechanical factors or the like, the polishing is stopped and the polishing is terminated.
4) Even if it reaches the surface of the conductor layer 16, the excess shaving can be stopped within the range of the thickness of the termination detection layer, and the conductor layer constituting the main part of the wiring (layer) 16
Can be avoided. As a result, it is possible to solve a problem (a problem that a wiring cross-sectional area is reduced and a wiring resistance is increased to cause a decrease in conductivity) due to overpolishing as in the related art.

In the above-described embodiment, the case where Al is used as a material for forming the first conductor layer (termination detection layer) 14 and Cu is used as a material for forming the second conductor layer 15 has been described. It is also possible to use each metal to be used in reverse. In this case, for example, sulfuric acid can be used as a chemical solution for selectively etching Cu used for the termination detection layer (first conductor layer 14).

In the above-described embodiment, the first and second conductor layers 1 for forming the wiring (layer) 18 having a two-layer structure are formed.
Although the case where Al and Cu are used as materials constituting 4 and 15 (processed into conductor layers 17 and 16 respectively) has been described, it goes without saying that the combination of materials constituting each conductor layer is not limited to this. is there. In short, unless the respective conductor layers are simultaneously dissolved by the chemical solution used in the step of forming the final wiring (layer) 18 (that is, only the terminal detection layer (first conductor layer 14) is selectively etched away). B), it is also possible to use a combination of materials other than Al and Cu. In this case, it is necessary to appropriately select a combination of materials constituting each conductor layer according to the chemical used. In addition to Al and Cu, silver (Ag), nickel (Ni), or gold (Au) can be used for the first conductor layer 14, and Ag can be used for the second conductor layer 15.

For example, an end detection layer (first conductor layer 14)
When a two-layer structure using Ag for the second conductor layer and Cu for the second conductor layer 15 is adopted, an additional advantage is obtained. In other words, Ag has a property of being higher in conductivity than Cu, and has a property that when the frequency is higher, the current can easily pass through only the surface portion due to the skin effect of the Ag layer (first conductor layer 14). The conductor layer having the two-layer structure (16, 1
7) When viewed as a whole, the conductivity can be relatively increased. However, the combination of Ag and Cu cannot be reversed. If the combination is reversed, Ag dissolves not only in hydrochloric acid but also in sulfuric acid. Therefore, when sulfuric acid is used to selectively etch the terminal detection layer (Cu layer) in the final stage, the conductor layer ( This is because the Ag layer is also removed by etching.

Further, in the above-described embodiment, the first and second
Although vapor deposition and sputtering are used as a method of forming the conductor layers 14 and 15 of the above, it is needless to say that the film forming method is not limited to this. In short, an appropriate film forming method may be appropriately selected according to the type of metal used as a material constituting each conductor layer. For example, in the case of Cu, electrolytic plating, electroless plating, CVD, or the like may be used. it can.

When Cu is used as a material for forming the second conductor layer 15, if plating is used as the film forming method, the plating is performed sufficiently and securely before forming the Cu plating film. It is necessary to form a metal thin film (plating base film) for the purpose. However, when the first conductor layer (termination detection layer) 14 is made of a metal that can also function as a plating base film, it is not necessary to form a plating base film.

FIG. 2 shows an example in which a semiconductor device is configured by applying the wiring forming method according to the above-described embodiment to a build-up multilayer wiring substrate. That is, in the illustrated example, the wiring forming method of the above-described embodiment is applied to a build-up multilayer wiring board provided as a plastic type semiconductor package, and in particular, a large number of pins serving as external connection terminals are erected on one surface of the board. Pin grid
FIG. 3 schematically shows an example of a configuration in the case of realizing an array (PGA) type wiring board, in which a semiconductor element (shown in the drawing) is provided on the surface of the wiring board opposite to the side where the pins 30 are provided. The example shows a configuration of a semiconductor device on which the semiconductor chip 31) is mounted.

In the drawing, reference numeral 20 denotes a core substrate made of an insulating material serving as a base of the wiring substrate, 21 denotes a Cu wiring (layer) patterned on both surfaces of the core substrate 20, and this wiring (layer) 21 denotes a core substrate. Together with 20, the first layer (core layer) of the build-up multilayer wiring board is constituted. As a material of the core substrate 20, for example, glass-epoxy resin, glass BT
(Bismaleimide-triazine) resin or the like is used.
The Cu wiring (layer) 21 corresponds to the lower wiring layer 10 in FIG. Reference numerals 22 and 23 denote a second interlayer insulating film and a wiring (layer), respectively.
Reference numeral 5 denotes a third interlayer insulating film and a wiring (layer). Each of the interlayer insulating films 22 and 24 corresponds to the interlayer insulating film 11 in FIG. 1, and each of the wirings (layers) 23 and 25 corresponds to the wiring (layer) 18 having a two-layer structure in FIG.

Reference numeral 32 denotes a solder bump provided on the semiconductor chip 31, reference numeral 33 denotes an underfill agent such as an epoxy resin, reference numeral 34 denotes a solder resist layer made of a resin having a property of being cured by irradiation of ultraviolet (UV) light, and reference numeral 35 denotes a solder resist layer. Solder 36 indicates a through hole provided in the core substrate 20. The joining of the pins 30 is performed, for example, as follows. First, a portion of the solder resist layer 34 corresponding to a region of a conductor layer (that is, a wiring (layer) defined as a pad) to which the pins 30 are to be bonded is irradiated with UV, and is exposed and developed to perform opening and closing. Is formed, and then an appropriate amount of solder 35 is placed on the pad in the opening,
The head of the T-shaped pin 30 having a large-diameter head is disposed thereon, and reflow is performed to solidify the solder 35 and fix the pin 30. On the other hand, the connection between the semiconductor chip 31 and the wiring board is performed by pressing the solder bumps 32 against the pads of the wiring board by thermocompression or the like.

In the configuration example shown in FIG. 2, the case where the wiring forming method of the above-described embodiment is realized in the form of a PGA type wiring board has been described, but such a wiring forming method is a ball grid array (BGA) type. It will be apparent to those skilled in the art that the same can be applied to a case where the present invention is implemented in the form of a wiring board.

[0034]

As described above, according to the present invention, after a wiring material having a two-layer structure is buried in an interlayer insulating film by a damascene process, the lower wiring material is terminated when polishing for planarization is performed. By using it as a detection layer, the end of polishing can be easily detected, and the end point of polishing can be stopped within an appropriate level range. This makes it easy to machine the surface of the object to be polished, and realizes highly conductive wiring.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a wiring forming method according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing one application example of a wiring forming method according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Lower wiring layer 11 ... Interlayer insulating film 12 ... Wiring groove 13 ... Via hole 14 ... 1st conductor layer (polishing end detection layer) 15 ... 2nd conductor layer 16 ... Main part of wiring (layer) Constituent conductor layer 17: Conductive layer constituting a part of wiring (layer) 18: Wiring (layer)

Claims (7)

[Claims] A first step of forming, by a damascene process, a wiring groove having a bottom and patterned into a required shape in an interlayer insulating film formed on a lower wiring layer; A second step of forming a first conductor layer on the interlayer insulating film; a third step of forming a second conductor layer on the first conductor layer so as to fill the wiring groove; A fourth step of polishing and flattening the surface of the second conductor layer by mechanical polishing to expose the surface of the first conductor layer on the interlayer insulating film; And a fifth step of removing by etching. 2. The method according to claim 1, wherein in the first step, a via hole reaching the lower wiring layer is formed at the bottom of the wiring groove together with the wiring groove by a dual damascene process. Wiring formation method. 3. In the fifth step, the etching of the first conductor layer is selected by using a chemical solution capable of dissolving only the first conductor layer without affecting the second conductor layer. 3. The method for forming a wiring according to claim 1, wherein the method is performed in an automated manner. 4. The wiring forming method according to claim 1, wherein in the fourth step, chemical mechanical polishing is used instead of the mechanical polishing. 5. The method according to claim 1, wherein the first conductor layer and the second conductor layer are
The method according to claim 1, wherein the wiring is formed by vapor deposition, sputtering, plating, or a CVD method. 6. A multilayer wiring board manufactured by using the wiring forming method according to claim 1. 7. A semiconductor device, wherein a semiconductor element is mounted on a multilayer wiring board manufactured by using the wiring forming method according to claim 1.