JP2000331830A - Planar magnetic element integrated semiconductor device - Google Patents
Planar magnetic element integrated semiconductor deviceInfo
- Publication number
- JP2000331830A JP2000331830A JP11138014A JP13801499A JP2000331830A JP 2000331830 A JP2000331830 A JP 2000331830A JP 11138014 A JP11138014 A JP 11138014A JP 13801499 A JP13801499 A JP 13801499A JP 2000331830 A JP2000331830 A JP 2000331830A
- Authority
- JP
- Japan
- Prior art keywords
- coil
- contact hole
- planar
- magnetic element
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Coils Of Transformers For General Uses (AREA)
- Thin Magnetic Films (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】
【課題】 製造工程が少なく、良品率の高い平面型磁気
素子一体型半導体素子を提供する。
【解決手段】 集積回路21上に平面型磁気素子22を
電気的に接続して一体型にするために、両者をコンタク
トホール6を有する絶縁膜を介して接合するとき、その
コンタクトホール6の側壁形状が順傾斜を持つようにす
ることで、工程を減らし良品率を高める。
(57) [Problem] To provide a planar magnetic element-integrated semiconductor element having a small number of manufacturing steps and a high yield rate. SOLUTION: In order to electrically connect a planar magnetic element 22 to an integrated circuit 21 to form an integrated type, when both are joined via an insulating film having a contact hole 6, a side wall of the contact hole 6 is provided. By making the shape have a forward inclination, the number of processes is reduced, and the yield rate is increased.
Description
【0001】[0001]
【発明の属する技術分野】この発明は、サーフェイスマ
イクロマシーニング技術、IC製造技術を活用すること
により平面型に製作される平面インダクタ(薄膜インダ
クタ)や平面トランスのような平面型磁気素子、特にこ
のような平面型磁気素子が集積回路と電気的に接続され
た平面型磁気素子一体型半導体デバイスに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar magnetic element such as a planar inductor (thin film inductor) or a planar transformer manufactured by utilizing a surface micromachining technology and an IC manufacturing technology, and more particularly, to a planar magnetic device. The present invention relates to a planar magnetic element integrated semiconductor device in which such a planar magnetic element is electrically connected to an integrated circuit.
【0002】[0002]
【従来の技術】近年、ノート型パソコンや携帯電話に代
表されるマルチメディア機器を始め、各種電子機器の小
型化が盛んに進められている。これに伴い、その電源部
の小型化の研究も活発に行なわれており、その主要部品
であるインダクタやトランスなどの磁気素子の小型化実
現のために、それらの磁気素子をサーフェイスマイクロ
マシーニング技術、IC製造技術を利用して平面型,薄
膜型に製造する試みが多くなされている。2. Description of the Related Art In recent years, miniaturization of various electronic devices such as multimedia devices typified by notebook personal computers and mobile phones has been actively promoted. Along with this, research on the miniaturization of the power supply section is also being actively conducted, and in order to realize the miniaturization of magnetic elements such as inductors and transformers, which are the main components, these magnetic elements are surface micromachining technology. Many attempts have been made to produce flat and thin film types using IC manufacturing technology.
【0003】平面型インダクタの最も一般的な例とし
て、例えば図4に示すものがある。なお、同図(a)は
組立分解図、(b)は断面図を示す。すなわち、シリコ
ン(Si)等の基板上に絶縁膜を形成し(図示なし)、
その上に下部磁性膜4,下部絶縁膜5,平面コイル(導
体部)8,絶縁膜10,上部磁性膜11の順に形成す
る、いわゆる平面コイルを磁性膜でサンドイッチ状に挟
み込んだ構造のものであり、積層平面型インダクタとい
われる。また、磁性体がコイルよりも外側にあり、コイ
ルが磁性膜の中にあることから、外鉄型または内部コイ
ル型インダクタとも呼ばれている。The most common example of a planar inductor is shown in FIG. 1A shows an exploded view, and FIG. 1B shows a sectional view. That is, an insulating film is formed on a substrate such as silicon (Si) (not shown),
The lower magnetic film 4, the lower insulating film 5, the planar coil (conductor portion) 8, the insulating film 10, and the upper magnetic film 11 are formed in this order, and a so-called planar coil is sandwiched between magnetic films. Yes, it is called a laminated planar inductor. Further, since the magnetic material is located outside the coil and the coil is inside the magnetic film, it is also called an outer iron type or an inner coil type inductor.
【0004】平面コイルの形状としては、つづら折り
型,ミアンダー(meander)型,スパイラル型な
ど様々なパターンが用いられる。これらのコイルパター
ンのうち、単位面積当たりのインダクタンス値を最も大
きくできるのはスパイラル型であることから、同じイン
ダクタンス値を得るためには、より小型化が可能なスパ
イラル型が最も適しているといえる。このような構成の
平面型インダクタは、使用する周波数帯域において充分
高いQ値を持つことが必要である。平面型インダクタの
Q値は、コイル抵抗をR、インダクタをL、ω=2πf
(f:周波数)とすると、 Q=ωL/R で表わされる。インダクタのQ値を高くするためにはコ
イルの抵抗を低く(小さく)し、インダクタンスを大き
くすることが必要である。As the shape of the planar coil, various patterns such as a zigzag type, a meander type, and a spiral type are used. Among these coil patterns, since the spiral type can maximize the inductance value per unit area, it can be said that the spiral type that can be further reduced is the most suitable to obtain the same inductance value. . The planar inductor having such a configuration needs to have a sufficiently high Q value in a used frequency band. The Q value of the planar inductor is represented by R for the coil resistance, L for the inductor, and ω = 2πf.
(F: frequency), it is represented by Q = ωL / R. In order to increase the Q value of the inductor, it is necessary to lower (reduce) the resistance of the coil and increase the inductance.
【0005】インダクタンスを決定する要素としては、
コイルの大きさとターン数が重要であり、平面インダク
タの場合、一般的には数mm角以上の大きさを必要とさ
れる。また、抵抗を小さくするためには、コイルの大き
さとターン数が一定の場合、コイルの厚さを厚くする必
要がある。近年、このような要望にこたえる平面インダ
クタとして、コイルの一辺が4mm角以上であり、コイ
ルの直流抵抗を低減するために、スパイラル型に電解め
っきで銅を成膜し、30μm以上の厚いコイル導体を持
ったメッキ方式のインダクタが多く報告されている(例
えば、特開平4−363006号公報,信学技報PE9
6−14など参照)。The factors that determine the inductance are:
The size of the coil and the number of turns are important, and a planar inductor generally requires a size of several mm square or more. Further, in order to reduce the resistance, it is necessary to increase the thickness of the coil when the size and the number of turns of the coil are constant. In recent years, as a planar inductor that meets such demands, one side of the coil is 4 mm square or more, and in order to reduce the DC resistance of the coil, a copper film is formed in a spiral type by electrolytic plating, and a thick coil conductor of 30 μm or more is formed. There have been many reports of plating-type inductors having the following characteristics (for example, Japanese Patent Application Laid-Open No. 4-363006, IEICE Tech.
6-14).
【0006】平面インダクタは、例えば電源回路を構成
する主要素子であるが、従来のバルク磁性体を用いたイ
ンダクタ素子に代えて平面インダクタを使用すること
で、電源回路の薄膜化,小型化を図った例が報告されて
いる。このような平面インダクタを電源回路に用いる場
合、電源回路を構成する制御IC,MOSFET,ダイ
オード,コンデンサなどを、例えばプラスチック基板上
に外付けし、平面インダクタも他の素子と同様に外付け
する方法(ハイブリッド方式)をとるのが一般的であ
る。A planar inductor is, for example, a main element of a power supply circuit. By using a planar inductor instead of a conventional inductor element using a bulk magnetic material, the power supply circuit is made thinner and smaller. Examples have been reported. When such a planar inductor is used in a power supply circuit, a method of externally mounting a control IC, a MOSFET, a diode, a capacitor, and the like that constitute the power supply circuit on, for example, a plastic substrate, and externally attaching the planar inductor in the same manner as other elements. (Hybrid method) is generally used.
【0007】電源回路をさらに小型化するには、制御I
CやMOSFETなどの集積回路と磁気素子を一体で形
成する必要がある。このような磁気素子一体型半導体デ
バイスとして、アルミニウム(Al)をスパッタで成膜
し、エッチングでコイル形状に加工したコイル膜厚6.
1μm、磁性膜膜厚1.4μmの積層型平面インダクタ
を、集積回路上に形成した発振回路の例も報告されてい
る(第22回応用磁気学会学術講演概要集22aB−4参
照)。To further reduce the size of the power supply circuit, the control I
It is necessary to integrally form a magnetic element with an integrated circuit such as C or MOSFET. 5. As such a magnetic element integrated semiconductor device, a film thickness of a coil formed by forming a film of aluminum (Al) by sputtering and processing it into a coil shape by etching.
An example of an oscillation circuit in which a laminated planar inductor having a thickness of 1 μm and a magnetic film thickness of 1.4 μm is formed on an integrated circuit has also been reported (see the 22nd Annual Meeting of the Applied Magnetic Society, 22aB-4).
【0008】[0008]
【発明が解決しようとする課題】上述のように、平面イ
ンダクタには、直流抵抗を低減するため、コイル導体の
厚さは厚いことが望まれる。しかし、上記のAlスパッ
タ膜のエッチング法で膜厚の厚いコイル導体を形成する
ことは、スパッタ膜の応力による基板の反りや、エッチ
ング法によるためのコイル占有率の低下などを生じるた
め、電源用の平面インダクタ形成法としては適していな
い。厚いコイル導体を形成するためには、メッキのシー
ド層を薄膜でスパッタした基板上に、厚膜のフォトレジ
ストや感光性ポリイミドなどをパターニングし、それを
メッキの型とした電解メッキ法で形成する方法が適切で
ある。その場合、集積回路と磁気素子とは、その間に絶
縁膜が必要であり、また、両素子を電気的に接続するた
めに、コンタクトホールを形成する必要がある。図5に
コンタクトホール形成手順の従来を示す。これは、マス
ク13を用いたエッチング法などによってコンタクトホ
ール14を形成し、そのコンタクトホール部にメッキを
することで、電気的に接続するものである。なお、1は
半導体基板、2は電極、3は絶縁膜、4は磁性膜を示
す。As described above, in order to reduce the DC resistance of the planar inductor, it is desired that the coil conductor be thick. However, forming a thick coil conductor by the above-described etching method of the Al sputtered film causes warpage of the substrate due to the stress of the sputtered film and a reduction in coil occupancy due to the etching method. It is not suitable as a planar inductor forming method. To form a thick coil conductor, a thick-film photoresist or photosensitive polyimide is patterned on a substrate on which a plating seed layer has been sputtered with a thin film, and is formed by an electrolytic plating method using the same as a plating mold. The method is appropriate. In this case, an insulating film is required between the integrated circuit and the magnetic element, and a contact hole needs to be formed to electrically connect the two elements. FIG. 5 shows a conventional contact hole forming procedure. In this method, a contact hole 14 is formed by an etching method using a mask 13 or the like, and the contact hole is plated to be electrically connected. 1 denotes a semiconductor substrate, 2 denotes an electrode, 3 denotes an insulating film, and 4 denotes a magnetic film.
【0009】しかし、図5のような方法では、次のよう
な問題がある。 マスクパターンを形成するための工程が新たに必要で
ある。 集積回路上の電極材料によってマスク材料が限定され
る。 コンタクトホールの側壁が、図5(4)または(5)の
ように曲線的なRを持つ形状となるため、特にその上部
でスパッタのつきまわりが悪く、集積回路上の電極への
メッキ液の回り込みによる電極腐食が生じ、良品率が低
下する。 したがって、この発明の課題は少ない工程で良品率の高
い平面型磁気素子一体型半導体デバイスを提供すること
にある。However, the method shown in FIG. 5 has the following problem. A new process for forming a mask pattern is required. The mask material is limited by the electrode material on the integrated circuit. The side wall of the contact hole has a curved R shape as shown in FIG. 5 (4) or (5). Electrode corrosion due to wraparound occurs, and the yield rate decreases. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a planar magnetic element integrated semiconductor device having a high yield rate with a small number of steps.
【0010】[0010]
【課題を解決するための手段】このような課題を解決す
るため、請求項1の発明では、半導体基板上に形成され
た集積回路上に、スパイラル平面型コイル,絶縁体およ
び前記スパイラル平面コイルを挟み込む軟磁性体薄膜を
積層してなる平面型磁気素子を、コンタクトホールを有
する絶縁膜を介して形成し、そのコンタクトホールの側
壁形状が順傾斜をもつことを特徴とする。この請求項1
の発明では、前記コンタクトホールを感光性絶縁材料の
ドライエッチング法により形成することができる(請求
項2の発明)。According to the first aspect of the present invention, a spiral planar coil, an insulator and the spiral planar coil are formed on an integrated circuit formed on a semiconductor substrate. A planar magnetic element formed by laminating soft magnetic thin films sandwiched therebetween is formed via an insulating film having a contact hole, and the sidewall shape of the contact hole has a forward slope. Claim 1
According to the invention, the contact hole can be formed by a dry etching method of a photosensitive insulating material (the invention of claim 2).
【0011】[0011]
【発明の実施の形態】図1はこの発明の第1の実施の形
態を示す構成図で、同図(a)は斜視図、(b)は断面
図を示す。すなわち、図1(a)に示すような半導体基
板の上面に形成した集積回路21の上に、電気的に接続す
るための、図1(b)に符号6で示すコンタクトホールを
持つ絶縁膜3を介して平面型磁気素子22を形成するに
あたり、そのコンタクトホール6の側壁形状に順傾斜を
持たせ、コンタクトホール部へのメッキ用シード層とな
るスパッタ膜のつきまわりを良好にするものである。FIG. 1 is a structural view showing a first embodiment of the present invention. FIG. 1 (a) is a perspective view and FIG. 1 (b) is a sectional view. That is, an insulating film 3 having contact holes indicated by reference numeral 6 in FIG. 1B for electrically connecting to an integrated circuit 21 formed on the upper surface of a semiconductor substrate as shown in FIG. When the planar magnetic element 22 is formed through the through hole, the side wall shape of the contact hole 6 is formed to have a forward inclination to improve the coverage of the sputtered film serving as a plating seed layer on the contact hole. .
【0012】図2は製造手順の説明図である。まず、集
積回路を形成した基板1上に、絶縁膜3を形成する。絶
縁膜としては、シリコン酸化膜や、シリコン窒化膜など
の、スパッタリングや真空蒸着などの成膜方法で形成で
きる絶縁膜や、ポリイミド樹脂などを適用する。これら
の絶縁膜は後工程でエッチングできる材料であることが
必要である。次に、下部磁性膜4を成膜し、エッチング
などでパターニングする。次にコンタクトホール6を形
成する。FIG. 2 is an explanatory diagram of the manufacturing procedure. First, an insulating film 3 is formed on a substrate 1 on which an integrated circuit has been formed. As the insulating film, an insulating film such as a silicon oxide film or a silicon nitride film, which can be formed by a film formation method such as sputtering or vacuum evaporation, or a polyimide resin is used. These insulating films need to be made of a material that can be etched in a later step. Next, the lower magnetic film 4 is formed and patterned by etching or the like. Next, a contact hole 6 is formed.
【0013】図3はコンタクトホールの形成手順の詳細
図である。まず、感光性ポリイミドなどの感光性絶縁材
料をパターニングし、絶縁膜5を形成する。このとき、
集積回路の電極2とインダクタを電気的につなぐための
コンタクトホール6を形成する穴パターン6aを形成す
る。穴パターン6aの側壁形状は、露光時間を短くする
ことで、順テーパ(順傾斜)を持つ形状にすることがで
きる。このあと、等方性のドライエッチングを行なうこ
とにより、コンタクトホール形成用の穴パターンの下部
にある絶縁膜3をエッチングし、コンタクトホール6b
を形成する。FIG. 3 is a detailed diagram of a procedure for forming a contact hole. First, a photosensitive insulating material such as photosensitive polyimide is patterned to form an insulating film 5. At this time,
A hole pattern 6a for forming a contact hole 6 for electrically connecting the electrode 2 of the integrated circuit and the inductor is formed. The side wall shape of the hole pattern 6a can be formed into a shape having a forward taper (forward inclination) by shortening the exposure time. Thereafter, by performing isotropic dry etching, the insulating film 3 below the hole pattern for forming a contact hole is etched to form a contact hole 6b.
To form
【0014】コンタクトホールの側壁の傾斜は、絶縁膜
5の穴パターン6aの傾斜をそのまま反映し、また、上
部のエッジ部分6cには等方性のエッチングであること
から、必然的にRが形成される。加えて、このコンタク
トホール形成方法では、絶縁膜5の膜厚を厚くしておけ
ば、そのまま下部磁性膜4とコイル導体8の層間絶縁膜
として使用できるため、マスク材料の剥離などの必要が
ない。つまり、省工程となるだけでなく、集積回路上の
電極材料もほとんど限定されることもない。The inclination of the side wall of the contact hole reflects the inclination of the hole pattern 6a of the insulating film 5 as it is, and since the upper edge portion 6c is isotropically etched, R is necessarily formed. Is done. In addition, in this contact hole forming method, if the thickness of the insulating film 5 is increased, the insulating film 5 can be used as an interlayer insulating film between the lower magnetic film 4 and the coil conductor 8, so that there is no need to peel off the mask material. . That is, not only is the process saved, but also the electrode material on the integrated circuit is hardly limited.
【0015】次に、コイル導体8を電解メッキで形成す
る。まず、電解メッキの通電層7を成膜,パターニング
し、コイル形状にパターニングする。次に、感光性ポリ
イミドをパターニングし、メッキ型9を形成し、電解メ
ッキでコイル導体8を形成する。コイル導体を形成する
方法としては、感光性ポリイミドではなく、フォトレジ
ストをメッキ型とするメッキ法でも良い。次いで、コイ
ル導体8上にポリイミドなどを塗布し、上部絶縁膜10
を形成する。コイルから電極取り出しが必要な場合は、
パターニングして電極取り出し口12を形成する。この
とき、感光性ポリイミドなどを用いると、電極取り出し
口と絶縁膜を同時に形成することができる。最後に、下
部絶縁膜と同様の工程で、上部絶縁膜を形成して平面イ
ンダクタ一体型半導体デバイスが形成される。以上のよ
うなコンタクトホール形成方法を用いることにより、集
積回路上へ平面型磁気素子を形成する際、電解メッキ法
を用いても電極材料への腐食などを生じず、少ない工程
で、安定したデバイスを得ることができる。Next, the coil conductor 8 is formed by electrolytic plating. First, a current-carrying layer 7 of electrolytic plating is formed and patterned to form a coil shape. Next, the photosensitive polyimide is patterned, a plating mold 9 is formed, and the coil conductor 8 is formed by electrolytic plating. As a method for forming the coil conductor, a plating method using a photoresist as a plating type may be used instead of the photosensitive polyimide. Next, polyimide or the like is applied on the coil conductor 8 to form an upper insulating film 10.
To form If you need to remove the electrode from the coil,
The electrode outlet 12 is formed by patterning. At this time, if a photosensitive polyimide or the like is used, the electrode outlet and the insulating film can be formed simultaneously. Finally, the upper insulating film is formed by the same process as the lower insulating film to form a planar inductor integrated semiconductor device. By using the above-described contact hole forming method, when forming a planar magnetic element on an integrated circuit, even when using an electrolytic plating method, corrosion of an electrode material does not occur, and a stable device can be formed in a small number of steps. Can be obtained.
【0016】〔実施例〕次に、実施例について説明す
る。まず、半導体基板を用いて、集積回路を形成する。
ここでは、電源用の制御ICとMOSFETを形成した
基板を用いた。IC製作終了後の半導体基板上に絶縁膜
として、ポリイミドを塗布・焼成する。膜厚は任意で良
いが、IC基板の表面を平坦にするため、ここでは5μ
mとした。[Embodiment] Next, an embodiment will be described. First, an integrated circuit is formed using a semiconductor substrate.
Here, a substrate on which a control IC for a power supply and a MOSFET are formed is used. Polyimide is applied and baked as an insulating film on the semiconductor substrate after the completion of IC fabrication. The film thickness may be arbitrary, but in order to make the surface of the IC substrate flat, 5 μm is used here.
m.
【0017】次に、磁性膜をスパッタ法で成膜し、エッ
チングでパターニングする。磁性膜の膜厚は9μmであ
る。次いで、感光性ポリイミドなどの感光性絶縁材料を
パターニングし、磁性膜とコイル導体間の絶縁膜とコン
タクトホール形成用の穴パターンとを形成する。膜厚は
15μmとした。このときの穴パターンの側壁形状は、
約45度の順テーパを持つように条件を設定した。続け
て、酸素とフロンを用いたプラズマエッチングでドライ
エッチングすることで、集積回路上に形成された電極上
に、平面インダクタと集積回路を電気的に接続するため
のコンタクトホールを形成する。このときの側壁形状も
同様の約45度であった。Next, a magnetic film is formed by sputtering and patterned by etching. The thickness of the magnetic film is 9 μm. Next, a photosensitive insulating material such as photosensitive polyimide is patterned to form an insulating film between the magnetic film and the coil conductor and a hole pattern for forming a contact hole. The film thickness was 15 μm. The side wall shape of the hole pattern at this time is
Conditions were set to have a forward taper of about 45 degrees. Subsequently, a contact hole for electrically connecting the planar inductor to the integrated circuit is formed on the electrode formed on the integrated circuit by performing dry etching by plasma etching using oxygen and chlorofluorocarbon. The side wall shape at this time was also about 45 degrees.
【0018】コイル導体の電解メッキ時のシード層とな
るチタンおよび金をスパッタで成膜し、エッチングでコ
イル形状にパターニングする。このときのスパッタ膜の
つきまわりは、良好であった。メッキシード層のコイル
パターンにあわせて感光性ポリイミドをパターニング
し、コイル導体のメッキ型を形成する。メッキ型の膜厚
は35μmである。電解メッキでコイル導体を形成す
る。コイルの膜厚はメッキ型とあわせ約35μmとし
た。その上に感光性ポリイミドをパターニングし、上部
磁性膜との層間絶縁膜を形成する。層間絶縁膜の膜厚は
10μmである。その上に上部磁性膜をスパッタし、エ
ッチングでパターニングする。以上で、薄膜リアクトル
が完成する。リアクトルと電気的に接続されていないA
lパッドは、プラズマによるポリイミドの深堀エッチン
グを行なって、露出させた。Titanium and gold serving as a seed layer at the time of electrolytic plating of the coil conductor are formed by sputtering, and are patterned into a coil shape by etching. At this time, the throwing power of the sputtered film was good. The photosensitive polyimide is patterned according to the coil pattern of the plating seed layer to form a coil conductor plating mold. The plating mold has a thickness of 35 μm. A coil conductor is formed by electrolytic plating. The film thickness of the coil was about 35 μm including the plating type. A photosensitive polyimide is patterned thereon to form an interlayer insulating film with the upper magnetic film. The thickness of the interlayer insulating film is 10 μm. An upper magnetic film is sputtered thereon and patterned by etching. Thus, the thin-film reactor is completed. A not electrically connected to reactor
The l pad was exposed by performing deep etching of polyimide by plasma.
【0019】最後に、磁性膜のウエハー内の場所による
磁性膜特性のバラツキを抑制するために、回転磁場中熱
処理を行ない、また、一軸磁気異方性を誘導するため
に、静止磁場中熱処理を行なった。製作したインダクタ
のターン数は16ターン、コイル導体幅93μm、コイル
厚35μm、コイル間隔幅20μm、コイル部の大きさ
4×4mm、コイル部の全厚さ53μm、制御IC,M
OSFETを含む半導体デバイスの大きさは4×5mm
である。平面インダクタと集積回路の電極との電気的接
続は良好であり、電極腐食などの現象は生じなかった。
小型化と薄膜化が同時に達成されている。Finally, heat treatment in a rotating magnetic field is performed to suppress variations in the magnetic film characteristics depending on the location of the magnetic film in the wafer, and heat treatment in a static magnetic field is performed to induce uniaxial magnetic anisotropy. Done. The number of turns of the manufactured inductor is 16 turns, the coil conductor width is 93 μm, the coil thickness is 35 μm, the coil interval width is 20 μm, the size of the coil portion is 4 × 4 mm, the total thickness of the coil portion is 53 μm, control IC, M
The size of the semiconductor device including the OSFET is 4 × 5 mm
It is. The electrical connection between the planar inductor and the electrodes of the integrated circuit was good, and phenomena such as electrode corrosion did not occur.
Miniaturization and thinning have been achieved at the same time.
【0020】本実施例では平面インダクタを例とした
が、平面トランスなども同様の製造方法で形成すること
ができる。また、磁性膜の有無に関係なく、電解メッキ
法でコイルを形成するすべての素子に適用可能である。
さらに、電源用の集積回路に限定されることなく、フィ
ルタ回路をはじめとする、磁気素子を必要とする半導体
デバイス一般に適用できることは勿論である。In this embodiment, a planar inductor is used as an example, but a planar transformer and the like can be formed by the same manufacturing method. Further, the present invention can be applied to all devices that form a coil by an electrolytic plating method regardless of the presence or absence of a magnetic film.
Further, it is needless to say that the present invention is not limited to an integrated circuit for a power supply, but can be applied to a general semiconductor device requiring a magnetic element such as a filter circuit.
【0021】[0021]
【発明の効果】この発明によれば、集積回路上に平面イ
ンダクタを形成するに当たり、両者を電気的に接続する
ためのコンタクトホールの側壁形状に順傾斜を持たせた
ので、少ない工程で、良品率の良い磁気素子一体型半導
体デバイスを得ることが可能となる。According to the present invention, when a planar inductor is formed on an integrated circuit, the shape of the side wall of the contact hole for electrically connecting the two is made to have a forward slope. A highly efficient magnetic element integrated semiconductor device can be obtained.
【図1】この発明の実施の形態を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of the present invention.
【図2】図1の製造工程説明図である。FIG. 2 is an explanatory view of a manufacturing process of FIG. 1;
【図3】図2におけるコンタクトホールの形成手順の詳
細図である。FIG. 3 is a detailed view of a procedure for forming a contact hole in FIG. 2;
【図4】平面型磁気素子の一般的な例を示す構成図であ
る。FIG. 4 is a configuration diagram illustrating a general example of a planar magnetic element.
【図5】図4の製造工程説明図である。FIG. 5 is an explanatory view of a manufacturing process in FIG. 4;
1…半導体基板、2…電極、3,5,10…絶縁膜、
4,11…磁性膜、6,6b…コンタクトホール、6a
…穴パターン、6c…エッジ部分、7…メッキの通電
層、8…コイル導体、9…メッキ型、12…電極取り出
し口、21…集積回路、22…平面型磁気素子。DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Electrode, 3, 5, 10 ... Insulating film,
4,11 ... magnetic film, 6,6b ... contact hole, 6a
... hole pattern, 6c ... edge part, 7 ... conductive layer of plating, 8 ... coil conductor, 9 ... plating type, 12 ... electrode outlet, 21 ... integrated circuit, 22 ... planar magnetic element.
フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 27/04 H01L 27/04 L 21/822 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 27/04 H01L 27/04 L 21/822
Claims (2)
に、スパイラル平面型コイル,絶縁体および前記スパイ
ラル平面コイルを挟み込む軟磁性体薄膜を積層してなる
平面型磁気素子を、コンタクトホールを有する絶縁膜を
介して形成し、そのコンタクトホールの側壁形状が順傾
斜をもつことを特徴とする平面型磁気素子一体型半導体
デバイス。A planar magnetic element comprising a spiral planar coil, an insulator, and a soft magnetic thin film sandwiching the spiral planar coil is laminated on an integrated circuit formed on a semiconductor substrate, and has a contact hole. A planar magnetic element-integrated semiconductor device formed through an insulating film and having a contact hole having a forward slope in a side wall shape.
のドライエッチング法により形成することを特徴とする
請求項1に記載の平面型磁気素子一体型半導体デバイ
ス。2. The planar magnetic element-integrated semiconductor device according to claim 1, wherein said contact hole is formed by a dry etching method of a photosensitive insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13801499A JP3765366B2 (en) | 1999-05-19 | 1999-05-19 | Planar magnetic element integrated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13801499A JP3765366B2 (en) | 1999-05-19 | 1999-05-19 | Planar magnetic element integrated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000331830A true JP2000331830A (en) | 2000-11-30 |
| JP3765366B2 JP3765366B2 (en) | 2006-04-12 |
Family
ID=15212051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13801499A Expired - Lifetime JP3765366B2 (en) | 1999-05-19 | 1999-05-19 | Planar magnetic element integrated semiconductor device |
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| Country | Link |
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| JP (1) | JP3765366B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332138A (en) * | 2002-05-14 | 2003-11-21 | Jfe Chemical Corp | Planar magnetic element |
| WO2005024949A1 (en) * | 2003-08-28 | 2005-03-17 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| JP2005534184A (en) * | 2002-07-25 | 2005-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Planar inductance |
| JP2010040701A (en) * | 2008-08-04 | 2010-02-18 | Jfe Mineral Co Ltd | Planar magnetic element |
| KR101792469B1 (en) | 2017-09-07 | 2017-10-31 | 삼성전기주식회사 | Common mode filter and method of manufacturing the same |
| CN110619988A (en) * | 2019-09-25 | 2019-12-27 | 深圳振华富电子有限公司 | Surface-mounted electronic component and preparation method thereof |
| CN110875424A (en) * | 2018-08-31 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device structure |
-
1999
- 1999-05-19 JP JP13801499A patent/JP3765366B2/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003332138A (en) * | 2002-05-14 | 2003-11-21 | Jfe Chemical Corp | Planar magnetic element |
| JP2005534184A (en) * | 2002-07-25 | 2005-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Planar inductance |
| WO2005024949A1 (en) * | 2003-08-28 | 2005-03-17 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| JPWO2005024949A1 (en) * | 2003-08-28 | 2006-11-16 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| CN100461410C (en) * | 2003-08-28 | 2009-02-11 | 株式会社日立制作所 | Semiconductor device and its manufacturing method |
| US7629667B2 (en) | 2003-08-28 | 2009-12-08 | Hitachi, Ltd. | Semiconductor device including an on-chip coil antenna formed on a device layer which is formed on an oxide film layer |
| JP4497093B2 (en) * | 2003-08-28 | 2010-07-07 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| JP2010040701A (en) * | 2008-08-04 | 2010-02-18 | Jfe Mineral Co Ltd | Planar magnetic element |
| KR101792469B1 (en) | 2017-09-07 | 2017-10-31 | 삼성전기주식회사 | Common mode filter and method of manufacturing the same |
| CN110875424A (en) * | 2018-08-31 | 2020-03-10 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device structure |
| CN110875424B (en) * | 2018-08-31 | 2025-03-18 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device structure |
| CN110619988A (en) * | 2019-09-25 | 2019-12-27 | 深圳振华富电子有限公司 | Surface-mounted electronic component and preparation method thereof |
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