JP2000330961A - Multiple cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten delay time of one-to-one information communication by providing a second line to be used for transmission of instruction information from a host CPU to each terminal CPU and state change notification information from each terminal CPU to the host CPU. SOLUTION: A line (a) is used for transfer of information on the one-to-one communication between the host CPU and a specified terminal CPU. A line (b) is used for transmission of the instruction information from the host CPU to each terminal CPU and the state change notification information from each terminal to the host CPU. A right of the one-to-one communication (information about communication destination) between the host CPU and the specified terminal CPU is managed by the host CPU. High speed one-to-one (one-to-N as a whole) information exchange which is conventionally impossible by such structure is performed by controlling connection information by using the line (b) and using the line (a) for actual large quantity of data communication by such algorithm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU system for controlling an entire control target while transmitting information between cascaded devices via a transmission line, and more particularly, to a multi-CPU system using a twisted pair transmission line. Information communication system between the devices.

[0002]

2. Description of the Related Art A system using an inexpensive twisted pair wire or other electric transmission line as a medium for transmitting information between devices, and under one host server CPU device (hereinafter referred to as a host CPU). Multiple client terminals C
When constructing a system in which PU devices (hereinafter referred to as terminal CPUs) are arranged in a cascade, and realizing this with the current technology, the configuration is as shown in FIG.

In FIG. 2, 000 denotes a host server C
PU, 100, (n-1) 00, n00 are a terminal CPU1, a terminal CPU (n-1), and a terminal CPUn, respectively. 002 is a lower communication modem (# 0L) attached to the host CPU, 101 is an upper communication modem (# 1U) attached to the terminal CPU1, and 102 is a lower communication modem (# 1L) attached to the terminal CPU1. The same applies to n0
1 is an upper communication modem (#n) attached to the terminal CPUn.
U).

The inside of the terminal CPU device is connected as shown in FIG. FIG. 3 shows terminal CPU # 1 in FIG. 2 as an example. In the figure, 100 is a terminal C
The entire PU1 device, 110 is a portion that executes software (S / W) processing in a CPU portion in the device, and 111 is a C
This is a PU bus. 112 is a communication modem # 1U with the upper side
Serial port # 1U, 113 connected to the serial port # 1L connected to the lower communication modem # 1L.
1L. The same applies to other terminal CPU units.

In the configuration shown in FIG. 2, in the case of downward communication from the host, information sent from the modem # 0L temporarily
The upper communication modem # 1U of the terminal CPU1 receives it, the CPU1 receives it via the serial port # 1U, performs S / W processing, and flows down through the serial port # 1L and the modem # 1L ( Relay processing) is performed. Thus, for example, if the target terminal CPU is the terminal #n, (n-1) relay processes will be interposed, and the information transmission time will be extremely long. The S / W relay processing delay time generated in each terminal CPU unit increases in proportion to the size of the information transfer packet. (If the information amount of one packet is small, it may be offset by the delay of the modem.) This is the same in the reverse case, and the relay processing time in each terminal CPU is also required for information transmission in the uplink direction. Is added.

[0006]

In the above-described configuration (FIG. 2), it is assumed that the host CPU and the terminal CPU perform one-to-n information communication.

Here, "at a certain time, the host C
I want to connect a PU and one specific terminal CPU to exchange information at high speed (one-to-one communication). The amount of information exchange is very large. At other terminals, a state change (hereinafter, state change) occurs at a certain frequency. The state change that occurs in each terminal CPU is small in size and relatively infrequent, but when it occurs, the host CPU must recognize it in a short time. If the condition "" must be satisfied, it is impossible to realize this in the configuration of FIG.

This is due to the following reasons.

(1) If the terminal that performs one-to-one communication with the host CPU is the terminal # 1, high-speed data transmission / reception can be performed. In the intervening terminal, it is necessary to perform S / W-like relay processing for each communication packet, and the farther the terminal is, the greater the added delay becomes. Therefore, high-speed information exchange cannot be performed even though the communication is one-to-one. This is true for bidirectional information transmission.

[0010] (2) The status change information generated on the terminal CPU side is also sequentially transmitted upward after receiving the relay processing of each terminal. However, here, the delay due to the relay processing is small because the packet is small. However, since it is not known when the state change occurs, there is a possibility that the state change information may overlap with the one-to-one information transmission communication performed between the host and the specific terminal. When this overlap occurs, the state change information is transmitted. In this case, it is necessary to wait until a packet break of one-to-one communication occurs. It is sufficient that the packet break occurs within the allowable delay value, but there is a great risk of exceeding this.

The problem (2) is that the number of lines is increased,
The problem can be solved by using a system in which the state change information is transmitted through a line different from the one-to-one communication. This is shown in FIG. The inside of each terminal CPU device in FIG. 4 is connected as shown in FIG.

In FIG. 4, 000 is a host server C
PU, 100, (n-1) 00, n00 are a terminal CPU1, a terminal CPU (n-1), and a terminal CPUn, respectively. 002 is one channel (# 0AL) of the downward communication modem attached to the host CPU, and 101 is the terminal CPU.
1 channel (# 1A) of the upper communication modem attached to
U) and 102 are one channel (# 1AL) of the downward communication modem attached to the terminal CPU1. The same applies to n0
1 is one channel (#nAU) of the upper communication modem attached to the terminal CPUn. 004 is the host CP
The second channel (# 0B) of the downward communication modem attached to U
L), 103 is the second channel (# 1BU) of the upward communication modem attached to the terminal CPU1, and 104 is the terminal CPU1.
The second channel (# 1B) of the downward communication modem attached to
L). Similarly, n03 is the second channel (#nBU) of the upper communication modem attached to the terminal CPUn.

In FIG. 5, reference numeral 100 denotes the entirety of the terminal CPU 1; 110, a portion for executing S / W in a CPU portion of the device; 111, a CPU bus. Reference numeral 112 denotes a first channel # 1AU of a serial port connected to the upper communication modem # 1AU, and reference numeral 113 denotes a first channel # 1AL of a serial port connected to the lower communication modem #IA. Reference numeral 114 denotes a second channel # 1BU of a serial port connected to the upper communication modem # 1BU, and reference numeral 115 denotes a second channel # 1BL of a serial port connected to the lower communication modem # 1BL.
It is. The same applies to other terminal CPU units.

In the case of a system having such a configuration, each CPU device uses the one channel for one-to-one information exchange and the second channel for notification of state change, thereby solving the above problem (2). Can be avoided. In other words, since a dedicated line is increased for information exchange at the time of state change detection, a state change notification that occurs asynchronously at each terminal is notified between the host CPU and any terminal CPU within the system. Regardless of the state of the one-to-one information communication performed between them, processing can be performed within a fixed delay time.

However, in this case, as is apparent from FIGS. 4 and 5, the modem and serial port of the host CPU unit require 2 channels, and each terminal CPU unit requires 4 channels of modem and serial port. I understand. Furthermore,
Even when this method is adopted, only the above problem (2) is solved, and the problem (1) (the host CP) is solved.
However, the effect of one-to-one information communication between U and any of the terminal CPUs becomes large).

An object of the present invention is to provide a multi-CPU system that can reduce the delay time of one-to-one information communication.

[0017]

SUMMARY OF THE INVENTION The present invention uses an inexpensive electric transmission line such as a twisted pair wire as a medium for transmitting information between devices, and uses a plurality of terminal CPU devices under one host CPU device. Are arranged in a cascade, the host CPU and any one terminal CPU
High-speed one-to-one communication (large capacity) between the host C and the host C.
The present invention realizes an information transmission method that enables a PU to recognize this in as short a time as possible, and is characterized by the following configuration.

(First invention) A plurality of terminal CPU units are cascaded from one host CPU unit via a transmission line, and one-to-one communication between the host CPU unit and one terminal CPU unit is performed. From the host CPU device to each terminal CP
In a multi-CPU system for performing collective communication with the U-device, a first line used for exchanging information in one-to-one communication between the host CPU and the terminal CPU;
Command information from the device to each terminal CPU device and each terminal CP
The second line used for transmitting the state change notification information from the U device to the host CPU device, and connection control using the second line, the host CPU device specifies one terminal CPU device, and this designation is performed. And a means for performing one-to-one communication by connecting a port on the transmission side to the host CPU device to the first line.

(Second Invention) Each of the terminal CPU devices includes:
It is characterized in that it is provided with means for taking in downlink information from the host CPU device and sending it directly to the next terminal CPU device.

(Third invention) The uplink information from each of the terminal CPU units to the host CPU unit selects whether to connect to the own station or to bypass the information from below only for the first line. And means for bypassing and transmitting the station except when the own station is selected.

(Fourth invention) A plurality of terminal CPU devices are cascaded from one host CPU device via a transmission line, so that one-to-one communication between the host CPU device and one terminal CPU device can be performed. From the host CPU device to each terminal CP
In a multi-CPU system that performs collective communication with U devices, one-to-one communication is performed between the host CPU device and the terminal CPU device using one line, and the host C
A first channel for information communication that handles a large amount of data between the PU device and the terminal CPU device, and a second channel for controlling the entire system are provided.

(Fifth invention) A communication partner is designated between the host CPU device and the terminal CPU device by connection control using the second channel, and the host CPU is used by using the first channel in accordance with the designation. One-to-one communication is performed between the device and the terminal CPU device.

(Sixth invention) The host CPU device and the terminal CPU device store the information of the first channel and the second channel information.
Channel information is multiplexed in a time-division manner, transmitted over one line, and internally separated into two pieces of channel information.

(Seventh invention) The host CPU device and the terminal CPU device store the information of the first channel and the second channel information.
Channel information is multiplexed in a time-division manner, a FIFO buffer memory is provided before the multiplexer of the channel to be prioritized, and time queuing is performed. When the data packet of the other channel is detected as empty, the own data packet is A transmission means, or a means for forcibly transmitting a data packet when the other channel is not vacant within a predetermined time is provided.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows an embodiment of an information transmission system according to the present invention. The figure shows a state of a circuit configuration in each terminal CPU device (an example of terminal CPU # 1). The connection state between CPUs in the entire system is the same as that in FIG.

In FIG. 1, reference numeral 100 denotes a terminal CPU # 1.
The entire apparatus, 110, is a section for executing S / W in a CPU section in the apparatus, and 111 is a CPU bus. Reference numeral 112 denotes a first channel “# 1AU” of the serial port connected to the communication modem “# 1AU” with the upper part.
114 is the second channel of the serial port connected to the communication modem “# 1BU” with the upper channel “# 1BU”, 11
Reference numeral 5 denotes a second channel “# 1BL” of the serial port connected to the communication modem “# 1BL” with the lower side. Reference numeral 116 denotes a DO register capable of changing the state of an output bit by a write operation by S / W.
16a is the output signal "Sel". 116 D
It is assumed that the O register is initialized to “L” level at the time of initial reset. Reference numeral 117 denotes a buffer circuit whose output is enabled when the “Sel” signal input is “H” level, and reference numeral 118 denotes a buffer circuit whose output is enabled when the “Sel” signal input is “L” level. This configuration is the same for the other terminal CPU units.

Now, terminal C having such a circuit configuration will be described.
It is assumed that a system similar to that shown in FIG. 4 is constructed with n PUs and one host CPU. Here, the operation of the system is defined as follows.

(1) The line a is used for exchanging information of one-to-one communication between the host CPU and the specific terminal CPU.

(2) The line b is used for transmitting command information from the host CPU to each terminal CPU and transmitting state change notification information from each terminal to the host CPU.

(3) The right of one-to-one communication (communication destination information) between the host CPU and the specific terminal CPU is managed by the host CPU.

(4) It is assumed that a packet for information transmission using each line contains address information indicating a unique station number of a destination. This information defines not only a single station address but also an all-station address for specifying all stations.

Now, it is assumed that an "initialization command" has been issued from the host CPU using the line b to specify the address of all stations in order to initialize the entire system. Line b
The information transmitted above is taken into the terminal CPU via the modem “# 1BU”. The fetched information is transmitted to the CP of the terminal CPU device via the serial port “# 1BU”.
It is provided to the U main unit and also to the transmitting side of the modem "# 1BL", transmitted to the down line b, and transmitted to the terminal device physically connected to the next lower level.

As described above, the control information sent from the host CPU to the line b is taken in by each terminal CPU station and simultaneously sent to the next terminal station (bypassed), so that the physical nesting is performed. Although there is a time delay, it is short,
It reaches the terminal CPU at the terminal.

Now, since the "initialization command" is sent with the address of all stations added, all terminal CPU stations take this in and initialize (reset) each terminal device. Thereby, the DO register corresponding to 116 in FIG. 1 is cleared, and the “Sel” signal becomes “L” level. In this state, the reception data of the modem “# 1AL” on the line a is given to the transmission side of the modem “# 1AU”, and the transmission data of the serial port “# 1AU” is
It is separated from the modem "# 1A @".

In this state, all the terminal CPUs are in a mode in which information on the line a from the lower station is transmitted to the next higher station.

Here, consider a case where the host CPU determines that it is necessary to perform one-to-one communication with the terminal CPUm.
The host CPU sends out a packet of a "communication start command" to which the station address of the terminal CPUm is added to the line b.
This command flows through the line b and reaches the terminal station, but only the terminal CPUm obtains the right of one-to-one information communication with the host CPU.

The terminal CPUm device operates the DO register (116 in FIG. 1) to change the level of the "Sel" signal to "H" level in a software manner. At this time, the other terminals do not change.

Thus, the serial communication of the terminal CPU device is performed.
The port “# 1AU” is connected to the line a (up).

The downstream information of the line a is taken into the modem "# 1 AU" of each terminal CPU, and then given to each CPU via the serial port "# 1 AU". , It arrives at the terminal CPU in a short time, although there is a time delay of physical nesting.

Thereafter, the host CPU and the terminal CPUm
A one-to-one information communication operation between the devices is possible.

The host CPU terminates communication with the terminal CPUm device and starts communication with another terminal device.
This is notified using a command on the line b. This command is determined by each terminal CPU, and the terminal CPUm
The device returns the “Sel” signal of the DO register to the “L” level, and disconnects the serial port “# 1AU” from the upstream line a.

The terminal CPU device to which the connection is designated connects its own station to the upstream line of line a by operating the "Sel" signal, as in the case of the connection between the terminal CPUm and the terminal CPUm.

With such an algorithm, the connection information is controlled using the line b and the line a is used for actual large-scale data communication. Such a one-to-one (one-to-N in total) information exchange can be performed. That is, the conventional problem (1) can be solved.

On the other hand, such host CPU and terminal C
It is assumed that an emergency state change occurs in any of the terminal CPU devices during one-to-one information transmission between PUs.
In this case, the signal may be transmitted to the host CPU using the up line of the line b. In the line b, there is a possibility that the host CPU issues a control command of connection information and batting, but since the amount of information is small, It is possible to communicate this to the host CPU in a time well within the regulation. Thereby, the conventional problem (2) can be solved at the same time.

(Second Embodiment) In the embodiment shown in FIG. 1, the amount of hardware in the terminal CPU device is greatly reduced and the performance of information transmission in the system is improved. Although it is possible, when the whole system is viewed, its configuration basically increases the number of lines.

That is, the host CPU requires two modem devices, the cascaded intermediate terminal CPU device requires four modems each, and the terminal terminal requires two modem devices. This would require a very large number of modem devices as a whole system.

Further, in order to realize the desired function, the number of lines is increased (two lines), and there is a disadvantage that it is difficult to introduce the line into a place where the number of lines is restricted.

The present embodiment makes it possible to derive the merit in a system using only one line without increasing the number of lines, which will be described in detail below.

This embodiment is a system using an inexpensive electric transmission line such as a twisted pair wire as a medium for transmitting information between devices, and a plurality of terminal CPUs under one host CPU device. In a system in which devices are arranged in a cascade, high-speed (less delay) one-to-one communication (large capacity) between a host CPU and one specific terminal CPU is realized, and at the same time, any terminal can be used. This is an information transmission method that enables the host CPU to recognize a state change that occurs as needed as quickly as possible.

FIG. 6 shows an information transmission method according to the present embodiment, and shows a circuit configuration (terminal CP) in each terminal CPU device.
U # 1). The connection state between CPUs in the entire system is the same as in FIG.

In FIG. 6, reference numeral 100 denotes the terminal CPU # 1 as a whole, 110 denotes a CPU portion in the device for executing S / W, and 111 denotes a CPU bus. Reference numeral 112 denotes an upper serial port “# 1AUL” for channel 1 having a large amount of information such as multimedia data.
Reference numeral 114 denotes an upper serial port “# 1BU” of channel 2 having a relatively small amount of information such as control information.
Reference numeral 5 denotes a serial port “# 1BL” below the channel 2 having a small amount of information. Further, 116 is S /
This is a DO register capable of changing the state of an output bit by a write operation by W, and its output signal "Sel" 116a. It is assumed that the DO register 116 is initialized to “L” level at the time of initial reset.

Reference numeral 117 denotes a buffer circuit whose output is enabled when the "Sel" signal input is at "H" level.
Reference numeral 8 denotes a buffer circuit whose output is enabled when the "Sel" signal input is at "L" level. Further, 119
Inputs the received signal from the IN terminal (119a signal),
This is a demultiplexer circuit that sorts the content of information and obtains and outputs it to either the OUT _A side (119b signal) or the OUT _B side (119c signal).

Conversely, the transmission signal 120 is input to the IN _A terminal (120a signal) or the transmission signal supplied to the IN _B terminal (120b signal), and one of them is input to the OUT terminal (120 signal).
c signal).

The input 121 receives a received signal from an IN terminal (121a signal), selects the contents of information, and
∪T _A side (121b signal) or, OUT _B side (121c
Signal) to output the signal.

Further, reference numeral 200 denotes a modem "# 1U" for an upper line connected to an upper server or a terminal CPU;
Reference numeral 01 denotes a modem "# 1L" for a lower line connected to a lower terminal CPU. Such a configuration is different from other terminal CPUs.
The same applies to the section.

In FIG. 6, the upper line and the lower line are:
It can be seen that both lines are one line, and the number of lines is reduced as compared with the system configuration shown in FIG. Therefore, the information that has been transmitted over two lines in FIG. 1 is transmitted in a time-division multiplexed form over this line.

Next, FIG. 7 shows an example of a circuit configuration on the host CPU side when the system is configured according to the present embodiment. On the host CPU side, there is no upper line and only the lower line, so that the circuit configuration is simplified. In the figure, 000
Is the entire host CPU # 0 device, 010 is a portion for executing S / W in a CPU portion in the device, and 011 is a CPU bus. Reference numeral 012 denotes a lower serial port “# 0AL” for channel 1 having a large amount of information such as multimedia data. Reference numeral 013 denotes a lower serial number of the channel 2 having a relatively small amount of information such as control information.
Port “# 0BL”.

Further, at 014, a received signal is inputted from the IN terminal (014a signal), the contents of information are selected, and O
UT _A-side (014B signal) or, O∪T _B side (014C
Signal) to output the signal.

015, on the other hand, receives the transmission signal given to the IN _A terminal (015a signal) or IN _B terminal (015b signal), and connects one of them to the OUT terminal (015 signal).
c signal).

A system corresponding to FIG. 2 includes a circuit configuration on the terminal CPU side shown in FIG. 6 and a host CP shown in FIG.
This is realized in combination with the U-side circuit configuration. Here, the terminal CPU having the circuit configuration as shown in FIG.
And a host CPU having a circuit configuration as shown in FIG.
It is assumed that a system similar to that of FIG.

Here, the operation of the system is defined as follows.

(1) Channel 1 is used for exchanging information (“up information” and “down information”) of one-to-one communication between a host CPU and a specific terminal CPU. A dedicated flag (start flag and end flag) is added to the information packet on channel 1.

(2) Channel 2 is used to transmit command information ("control information") from the host CPU to each terminal CPU and notification information ("notification information") from each terminal to the host CPU. , The amount of information is smaller than that of channel 1. A dedicated flag (start flag and end flag) is added to the information packet on channel 2. Note that channels 1 and 2 use different flags.

(3) The right of one-to-one communication (communication destination information) between the host CPU and the specific terminal CPU is managed by the host CPU.

(4) It is assumed that the information transmission packet on each channel contains address information indicating the unique station number of the destination. This information defines an all-station address that designates all stations in addition to a single-station address.

Under the above operating conditions, since all information transmitted from the host CPU device is processed by a single CPU, it is impossible for the information of channel 1 and channel 2 to flow on the line at exactly the same time. Because there is no
The multiplexer of the 015 circuit performs a multiplex operation (multiplexes and transmits two pieces of information to one line) as shown in FIG. The “downlink information” of one channel and the “control information” of two channels are transmitted over one line in order.

In the terminal CPU device, the information on the line is received by the demultiplexer of the 119 circuit in FIG. Here, it is determined whether the packet is a “downlink information” packet or a “control information” packet by a dedicated flag defined for each channel.
b terminal side (112 circuit serial port # 1 AU side)
The "control information" packet is distributed to the 119c terminal side (serial port # 1 BU side of 114 circuits) and transmitted. FIG. 9 shows the state of demultiplexing.

Similarly, the "multiplexer" and "demultiplexer" in the host CPU and each terminal CPU unit function to multiplex / demultiplex information of channel 1 and channel 2. The state is the same as the state shown in FIGS.

As a result, in the terminal CPU device, “downlink information” is given to the channel 1 side and “control information” is given to the channel 2 side. At the same time, the line information (119a signal) given from the host CPU is bypassed in the terminal CPU unit and given to the transmitting side of the lower line modem 201 in the multiplexed signal state, and is also sent to the lower terminal. It is sent as the same signal. As a result, the same information is sequentially provided to the lower terminal CPU device and thereafter.

As described above, in this configuration, all terminals C
Since the same information can be given to all PUs, the information to be sent to each channel is specified in advance by adding a unique station address of the partner.
The specified specific terminal CPU device can fetch necessary information packets.

On the other hand, the “notification information” sent from the lower terminal CPU device to the host CPU device is as follows:
It is transmitted by the upper serial port for channel 2 (corresponding to 114 circuits in FIG. 6) in the terminal CPU device. This information packet is sent to the 120
The signal is input to the terminal b, multiplexed with the input of the terminal 120a on the channel 1 side, and transmitted to the upper line. Regarding the multiplexing method in this case, it is assumed that the information of channel 2 has higher priority than the information of channel 1, and when the information of channel 2 flows, the information of one of the channels is destroyed. Shall be good.

Since the generation of the information on the channel 1 side and the generation of the information on the channel 2 side are completely asynchronous, if there is a collision between the two information and the amount of the information on the channel 1 is larger, In that case, there is a strong possibility that the information of channel 1 will be destroyed. However, from the viewpoint of the operation of the entire system, it is possible to recover the loss of information for each channel by using a higher-level software protocol and retransmitting the information.

Now, with such means, a certain terminal CPU
"Notification information" of channel 2 sent to another terminal CPU device (or server device) one level above the device
Is received by the demultiplexer circuit 121 in FIG. 6 (or the demultiplexer circuit 015 in FIG. 7), and from the type of the flag attached to the information packet, is the “uplink information” of the channel 1 or the “uplink information” of the channel 2 It is determined whether it is "notification information", and is distributed to each channel. This operation is performed by the host CPU in each terminal CPU device.
The same applies to the device.

In the terminal CPU device, the data determined as "notification information" is received by the lower serial port # 1BL for channel 2 in FIG. It is transmitted to the terminal CPU or host CPU further upward using the upper serial port # 1B # 2 for # 2. In the host CPU device, the serial port # 0BL for channel 2 in FIG. 7 receives the data, and the host CPU itself receives and processes the data.

In a system performing such an operation,
Now, in order to initialize the entire system, using the channel 2 and specifying the address of all stations from the host CPU,
It is assumed that an “initialization command” has been issued.

As described above, the "control information" sent from the host CPU to the line is taken in by each terminal CPU station and simultaneously sent to the next terminal station (bypassed). Although there is a time delay of the nest, it reaches the terminal CPU in a short time.

Now, since the "initialization command" is sent with the address of all stations added, all terminal CPU stations take in the same and initialize (reset) each terminal CPU device.

As a result, DO corresponding to 116 in FIGS.
The register is cleared and the "Sel" signal goes to "L" level. In this state, 118 buffers are active,
Since buffer 117 is inactive,
The data on the 121b terminal side of the demultiplexer of the circuit is 1
20 multiplexer circuits. Therefore,
In this state, all the terminal CPU devices are in a mode in which channel 1 information "uplink information" from the lower station is transmitted to the next higher station.

Here, consider a case where the host CPU determines that it is necessary to perform one-to-one communication with the terminal CPUm.
The host CPU sends out a “communication start command” packet to the channel 2 to which the station address of the terminal CPUm is added. This command flows through the line and reaches the terminal station.
The right of one-to-one information communication with U is obtained.

The terminal CPUm device operates the DO register (116 in FIG. 6) to change the level of the "Sel" signal to the "H" level in S / W (the other terminals do not change). Thus, the serial port “# 1AU” of the terminal CPUm device is connected to the 120 multiplexer.

The downlink information on the line is taken into the modem “# 1U” of each terminal CPU, demultiplexed and given to the serial port “# 1BU”, and transmitted to each CPU. Since it is bypassed to the sending side of the modem “# 1L”, it reaches the terminal CPU in a short time although there is a physical nest time delay.

Thereafter, the host CPU and the terminal CPUm
A one-to-one information communication operation between the devices is possible.

The host CPU terminates communication with the terminal CPUm device and starts communication with another terminal device.
That effect is notified using “control information” on channel 2. This "control information" is determined by each terminal CPU, and the terminal CPUm device returns the "Sel" signal of the DO register to the "L" level and outputs the serial port "# 1A".
U "is disconnected from the multiplexer for upstream information.

The terminal CPU device to which the connection is designated connects its own station to the multiplexer for uplink information by operating the "Sel" signal, as in the case of the connection between the terminal CPUm and the terminal CPUm.

According to such an algorithm, connection information is controlled using channel 2 and channel 1 is used for actual large-volume data communication.
High-speed one-to-one (one-to-N in total) information exchange that was impossible with such a configuration can be performed, and the conventional problem (1) can be solved.

On the other hand, such host CPU and terminal C
Consider the case where an emergency state change occurs in any terminal CPU device during one-to-one information transmission between PUs.
The channel 2 may be transmitted to the host CPU, and in the channel 2, there is a possibility that the host CPU issues “control information” of connection information and batting, but since the amount of information is small, the time within the prescribed This is the host CPU
It is possible to communicate to. Thereby, the conventional problem (2) can be solved at the same time. Further, in the present system, in order to solve these problems, it is possible to realize a mode in which only one line is used without increasing the number of lines used.

(Third Embodiment) In the second embodiment, the desired superiority can be secured in the system using the circuit configuration examples shown in FIGS. 6 and 7. "Notification information" on channel 2 transmitted upward from the CPU device, and "Up information" transmitted from any one terminal CPU in the system to the host CPU.
Occur completely asynchronously, so that both may occur at the same time in the transmission multiplexer circuit portion in a certain terminal CPU device. In this case, if one of the information is prioritized, the other information may be lost. In this case, it is assumed that the amount of data is large and the amount of information of channel 2 is smaller than that of channel 1 in which one packet is large, and that channel 2 includes information that is important and cannot be lost, such as state change information. If so, it is necessary to give priority to channel 2.

In this case, when there is a collision between the two,
Even if the information on channel 1 is destroyed, it is necessary to transmit the information on channel 2 accurately.

Here, if the information on channel 1 always collide with the information on channel 2 and the information on channel 1 is destroyed, the frequency of data loss increases. Think of a way.

FIG. 10 shows a circuit example of the present embodiment for realizing this in the case of a circuit in a terminal CPU device. In this figure, parts other than 122 and 123 are equivalent to FIG.

Reference numeral 122 denotes a signal for inputting the transmission signal (signal 122a) from the upper serial port "# 1BU" for channel 2 to the IN terminal, sequentially storing the signal, and sequentially outputting the signal to the OUT terminal (signal 122b). FIFO (Fi
rstinFirstout) buffer memory. Reference numeral 123 denotes a time-out detection timer circuit which generates a time-out signal of 123b unless reset for a certain period of time after receiving a trigger by the signal 123a.

The operation of this circuit is basically the same as that of the second embodiment except that the transmission multiplexer circuit 12
The operation in the case where data of channel 1 and channel 2 are simultaneously inputted to both input terminals 120a and 120b of 0 is different.

For example, in this circuit configuration, it is assumed that data of channel 1 has already started to be transmitted from the multiplexer before data of channel 2 is generated. This possibility is very high.

Here, when data of channel 2 is generated, the multiplexer circuit sequentially stores the data of channel 2 in the FIFO memory, and
When a data packet break occurs, the data of channel 2 is extracted from the stored FIFO and transmitted.

Then, the data of channel 1 which has been started to be transmitted earlier is multiplexed with the data of channel 2 without being destroyed. This is shown in FIG.

Here, if the “notification information” of channel 2 is such as state change information that needs to be detected within a certain period of time, the process waits for a break of the channel 1 packet. If there is, there is a possibility that this time will be exceeded. In this case, it is necessary to force the channel 2 information to flow even if the channel 1 information is destroyed.

Therefore, a time-out timer is provided as 123. When a data transmission request of channel 2 occurs while data of channel 1 is being transmitted, information of channel 2 is started to be stored in the FIFO, and a timeout timer circuit of 123 is activated by a signal of 123a. In the timeout timer 123, the maximum time during which the information of the channel 2 can be set is set. If a break in the data packet of the channel 1 occurs within this time, the channel 2 is transferred from the FIFO to the channel 2. The transmission is started while reading out the data.

On the other hand, if the data of channel 1 continues for a very long time and there is no break in the packet even if the time-out timer 123 times out, the transmission multiplexer uses the time-out signal of 123b to send the FI
The data of channel 2 is read from the FO, and the transmission of the data of channel 2 is forcibly switched.

As a result, channel 1 being transmitted
Is destroyed, but as described above, this can be recovered by the upper software.

As in the second embodiment, even if data collide between channels and data is destroyed, a soft recovery can be expected, but if the system is busy with extra recovery processing, the system throughput drops. Therefore, it is certainly better to destroy as little data as possible. Therefore, the measure according to the present embodiment for minimizing this is effective. Theoretically, if the total throughput is appropriate, the countermeasures of the present embodiment should be able to minimize the data of the channel 1 to be damaged.

[0101]

As described above, according to the present invention, an electric transmission line such as an inexpensive twisted pair line is used as a medium for transmitting information between devices, and a plurality of terminals are provided under one host CPU device. In a system in which CPU devices are arranged in a cascade, the following effects are obtained.

(1) "At a certain time, the host CP
I want to connect U and one specific terminal CPU to exchange information at high speed (one-to-one communication). The amount of information exchange is very large. At other terminals, a state change occurs at a certain frequency. The state change that occurs in each terminal CPU is small in size and relatively infrequent, but when it occurs, the host CPU must recognize it in a short time. ".

(2) As described above, a cascade-connected 1-to-N host-terminal system is constructed even under the condition of using an electric transmission line such as an inexpensive twisted pair line, and large-scale transmission of multimedia information and the like is performed. Bidirectional information transmission including capacity data can be realized.

(3) The system having the above-mentioned features can be realized by a circuit of one circuit (two pairs) of a metallic cable without adding a line. Compared to a two-circuit system, the number of modem devices required for relay can be reduced by half.

(4) In the second embodiment, there is data that is destroyed and lost at a certain rate in order to reduce the number of lines, and it is necessary to perform recovery by software.
In order to minimize this, in the third embodiment, it is possible to minimize the destruction of data packets.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a terminal CPU device according to an embodiment of the present invention.

FIG. 2 is a cascade connection configuration diagram of a CPU device.

FIG. 3 is an example of the internal configuration of a conventional terminal CPU device.

FIG. 4 is a cascade connection configuration diagram of a conventional CPU device.

FIG. 5 is a configuration example of a conventional terminal CPU device.

FIG. 6 is a configuration diagram of a terminal CPU device according to another embodiment of the present invention.

FIG. 7 is a configuration diagram of a host CPU device according to another embodiment of the present invention.

FIG. 8 shows data multiplex processing in another embodiment.

FIG. 9 illustrates a demultiplex process according to another embodiment.

FIG. 10 is a configuration diagram of a terminal CPU device showing another embodiment of the present invention.

FIG. 11 shows multiplex processing of data according to another embodiment.

[Explanation of symbols]

 000 host server 100, (n-1) 00, n00 terminal CPU device 110 CPU 101-104, 200, 201 modem 012, 012, 113-115 serial port 116 DO register 014, 015 119, 121 ... demultiplexer 015, 120 ... multiplexer 122 ... FIFO 123 ... timer

Claims (7)

[Claims] 1. A cascade connection of a plurality of terminal CPU devices from one host CPU device via a transmission path, one-to-one communication between the host CPU device and one terminal CPU device, and communication from the host CPU device. In a multi-CPU system that performs collective communication with each terminal CPU device, a first line used for exchanging information in one-to-one communication between the host CPU device and the terminal CPU device; And a second line used for transmitting state change notification information from each terminal CPU device to the host CPU device, and connection control using the second line, the host CPU
The device designates one terminal CPU device, and in response to the designation, the terminal CPU device connects a port on the transmission side to the host CPU device to the first line to perform one-to-one communication. A multi-CPU system, comprising: 2. Each of the terminal CPU devices includes a host CPU.
In addition to taking down information from the device, the next terminal CPU
2. The multi-CPU system according to claim 1, further comprising means for directly sending the data to the apparatus. 3. The host C from each of the terminal CPU devices.
The uplink information to the PU device allows the user to select whether to connect to the own station or to bypass the information from below only for the first line, except when the own station is selected. The multi-CPU system according to claim 1, further comprising a unit that performs transmission by bypassing. 4. A cascade connection of a plurality of terminal CPU devices from one host CPU device via a transmission path, one-to-one communication between the host CPU device and one terminal CPU device, and communication from the host CPU device. In a multi-CPU system for performing collective communication with each terminal CPU device, one-to-one communication is performed between the host CPU device and the terminal CPU device using one line, and the host CPU device is connected to the one line.
A first channel for information communication that handles a large amount of data between the device and the terminal CPU device, and a second channel for controlling the entire system.
A multi-CPU system comprising: 5. A communication partner between the host CPU device and the terminal CPU device is designated by connection control using the second channel, and the host CPU device and the terminal CPU device are used by using the first channel in accordance with the designation. The multi-CP according to claim 4, wherein one-to-one communication is performed between the devices.
U system. 6. The host CPU device and the terminal CPU device multiplex information of the first channel and information of the second channel in a time-division manner and transmit the multiplexed information over one line, and internally convert the information into two channel information. The multi-CPU system according to claim 4, wherein the multi-CPU system is separated. 7. The host CPU device and the terminal CPU device multiplex information of the first channel and information of the second channel in a time-division manner, and provide a FIFO buffer memory in front of a multiplexer of a channel to be prioritized. Means to send out its own data packet when it detects a vacancy of the data packet of the other channel, or forcibly removes the data packet when the vacancy of the other channel does not occur within a certain time. 7. The multi-CPU system according to claim 6, further comprising a sending unit.