JP2000323985A - Charge pump circuit, pll frequency synthesizer circuit, and mobile communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reference noise of a local signal from becoming worse without losing current balance. SOLUTION: The charge pump circuit 60 is equipped with a CP current correcting circuit 90 which applies correcting currents IupH and IdownH corresponding to a charge pump output current CP (control voltage) for an increase or decrease of a charge pump output current IP (IUP, IDOWN) caused by the variation of the charge pump output voltage CP. Consequently, the variation of the charge pump current IP can be suppressed to improve the current balance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL frequency synthesizer circuit, and more particularly, to a PLL frequency synthesizer circuit used as a local oscillator for selecting a mobile communication device.

[0002]

2. Description of the Related Art As described in, for example, Japanese Patent No. 2877196 and known in the art, a PLL frequency synthesizer circuit generally includes a loop filter (LF) including a capacitor and a voltage controlled oscillator (VCO). When,
It has a variable frequency divider, a phase comparator (PFD), and a charge pump circuit (hereinafter also referred to as a “CP circuit”). The loop filter operates as a low-pass filter, and generates a voltage between terminals of the capacitor as a control voltage. The voltage controlled oscillator generates an output signal having an output frequency in response to the control voltage. The variable frequency divider divides the output signal based on the variable frequency division ratio to generate a divided signal. The phase comparator receives the input signal having the input frequency and the divided signal, detects a phase frequency difference between the input signal and the divided signal,
A pulse-like rising instruction signal and a falling instruction signal indicating the phase frequency difference are generated. In response to the rising instruction signal, the charge pump circuit discharges a control current (rising constant current) to the loop filter and charges the capacitor. Further, the charge pump circuit responds to the falling instruction signal by flowing a control current (constant falling current) from the loop filter and discharging the charge stored in the capacitor. The control current is also called a charge pump output current. Regardless, the charge pump circuit applies the charge pump output voltage to the loop filter.

[0003] Such a PLL frequency synthesizer circuit is used, for example, as a local oscillator for selecting a mobile communication device, in which case the output signal is used as a local signal. And PLL for it
In a frequency synthesizer circuit, it is necessary to reduce reference noise of a local signal and to realize a high-speed setup.

Here, "reference noise" will be described. The charge pump state when the PLL loop is locked is basically high impedance. However, if no signal is output, a dead zone occurs and the VCO
It also causes the generation of residual FM in the spectrum. In order to prevent this, a small error pulse is generally output from the output of the charge pump even when the PLL loop is locked. When the current balance between the ascending P-channel MOS transistor (described later) and the descending N-channel MOS transistor (described later) constituting the charge pump circuit is lost, the minute error pulse output increases. This "current balance" means that the power supply voltage is Vcc, and in terms of product specifications, the charge pump output voltage is in the range of 0.5 V to (Vcc-0.5 V), and the rising / falling DC The current is specified within 5%. Next, what happens when the error pulse becomes large will be described. Normally, since a very small error pulse to be dropped by the loop filter cannot be completely dropped, a pulse having a reference cycle enters the control terminal of the VCO. That is VC
Since the signal is cross-modulated in O, a noise component is generated in the VCO spectrum at a position separated from the carrier (local signal) by the reference frequency. This noise component is called “reference noise”.

As a charge pump circuit for outputting such an error pulse, a current drive type configuration is often used. At that time, when switching channels, the charge pump output current of the charge pump circuit is increased so that the capacitor of the loop filter can be charged and discharged at high speed. It is common to lower the charge pump output current and lower the loop gain of the PLL frequency synthesizer circuit.

FIG. 5 shows a configuration of a conventional charge pump circuit 60 '. As shown in FIG.
0 'is a rising instruction signal U from a phase comparator (not shown).
A first input terminal 61 for inputting P, and a second input terminal 62 for inputting a down instruction signal DOWN from the phase comparator.
When a pump output terminal 63 to the inlet / outlet control current I _P with respect to the loop filter (not shown), the power supply voltage Vcc
, And a ground terminal 65.
The rising instruction signal UP is an active low signal, and the falling instruction signal DOWN is an active high signal. First
Is called an ascending instruction input terminal, and the second input terminal 62 is called a descending instruction input terminal.

The charge pump circuit 60 ′ comprises a first P-channel metal oxide semiconductor field effect transistor (MOSFET) 71 connected as a first transistor switching means connected to a rising instruction input terminal 61, and a falling instruction input terminal 62. N-channel MOSFET 81 acting as second transistor switching means connected to
If, and an increase in the constant current source and lowering the constant current source for determining, as described below, the rise constant current I _'UP and down the constant current I' _DOWN. The first P-channel MOSFET 7
The drains of the first and first N-channel MOSFETs 81 are connected to each other, and are connected to the pump output terminal 63. The first MOSFET 71 is the above-mentioned rising P-channel MOS transistor, and is provided with a first N-channel MOS transistor.
The FET 81 is a descending N-channel MOS transistor.

Specifically, the charge pump circuit 60 '
Are a constant current source 70 for flowing a constant current I, and second to fourth
P-channel MOSFETs 72, 73, 74, and second and third N-channel MOSFETs 82, 83.

One end of the constant current source 70 is connected to the ground terminal 65, and the other end is connected to the drain of the second P-channel MOSFET 72. Second P-channel MOSFET
72 has a source connected to the power supply terminal 64 and a gate connected to the second terminal.
Of the P-channel MOSFET 72 and the gate of the third P-channel MOSFET 73. Third
The source of the P-channel MOSFET 73 is a power supply terminal 64.
It is connected to the. That is, the second and third P-channel MOSFETs 72 and 73 function as a first current mirror circuit. The drain of the third P-channel MOSFET 73 is connected to the source of the first P-channel MOSFET 71. Therefore, the constant current source 70 and the first current mirror circuit (the second and third P-channel MOSFs)
Combination of ET72 and 73) operates as the rise constant current source for determining the rise constant current I _'UP. Also,
The first P-channel MOSFET 71 has this rising constant current.
It operates as a first driving transistor for driving the I _{'U P.}

The second P-channel MOSFET 72
Is connected to the gate of the fourth P-channel MOSFET 74, and the source of the fourth P-channel MOSFET 74 is connected to the power supply terminal 64. That is, the second and fourth P-channel MOSFETs 72 and 74
Works as a current mirror circuit. Fourth P channel M
The drain of the OSFET 73 is a second N-channel MOSF
Connected to the drain of ET82. The source of the second N-channel MOSFET 82 is connected to the ground terminal 65, and the gate is connected to the drain of the second N-channel MOSFET 82 and the gate of the third N-channel MOSFET 83. The source of the third N-channel MOSFET 83 is connected to the ground terminal 65. That is, the second
And the third N-channel MOSFETs 82 and 83
Works as a current mirror circuit. Third N channel M
The drain of the OSFET 83 is a first N-channel MOSF
Connected to the source of ET81. Therefore, the constant current source 70, the second current mirror circuits (second and fourth P-channel MOSFETs 72 and 74) and the third current mirror circuit (second and third N-channel MOSFETs)
Combination of 82 and 83) operates as the descending constant current source for determining the descending constant current I _'DOWN. The first N-channel MOSFET 81 is connected to the falling constant current I ′.
_It operates as a second drive transistor for driving _DOWN .

In any case, the charge pump circuit 60 '
Third P-channel MOS forming a part of rising constant current source
FET 73 and a first driving transistor serving as a first driving transistor.
A P-channel MOSFET 71, a first N-channel MOSFET 81 acting as a second drive transistor,
Third N-channel MOS forming part of falling constant current source
The FET 83 has a configuration in which four elements are connected in series between a power supply terminal 64 and a ground terminal 65.

In such a configuration, the first P-channel MOSFET 71 and the first N-channel MOSFET
The T81 of the on / off operation, increased by controlling the flow of constant current I _'UP outflow and falling constant current I' _DOWN, the control current to the loop filter (the charge pump output current) I _'P outflow / Inflowing. In other words, according to the pulse widths of the rising instruction signal UP and the falling instruction signal DOWN supplied from the phase comparator (not shown), the charge pump circuit 60 ′ sends charges to the loop filter or transfers charges to the loop filter. Or take it out of An output frequency of an output signal generated from a voltage controlled oscillator (not shown) changes according to a control voltage output from a filter output terminal of the loop filter.

Anyway, the conventional charge pump circuit 6
When the output signal of the VCO is different from the set output frequency, the operation of 0 ′ is performed by using a control current (charge pump output current) corresponding to the frequency difference (phase difference) as a control voltage via a loop filter to control the VCO. It is supplied to the terminal and takes three-state output of rising / falling / high impedance.

On the other hand, as an element which determines the reference noise of the local signal, the rise / fall current balance of the charge pump output voltage CP is involved in addition to the above-mentioned loop gain. When the selected channel is on the high “High” side,
That is, when the output frequency of the output signal is set to increase, the charge pump output voltage CP of the charge pump circuit 60 'also increases. When the selected channel is set to the low “Low” side, that is, the side for decreasing the output frequency of the output signal, the charge pump circuit 6
The charge pump output voltage CP of 0 'also decreases. Therefore, the current balance between the rising constant current I ' _{UP and the} falling constant current I' _DOWN is broken. As a result, the reference noise of the local signal deteriorates.

In order to reduce the influence of the reference noise, the sizes of the driving transistors 71 and 81 are determined so as to minimize the current balance. However, MOSFETs manufactured by common processes
In this case, the linearity of the charge pump output current with respect to the drain-source voltage cannot be obtained, and a current balance difference of about 10% occurs.

FIG. 6 shows an example of the characteristics of the charge pump output current of the conventional charge pump circuit 60 '. In FIG. 6, the horizontal axis represents the charge pump output voltage CP, and the vertical axis represents the charge pump output current I _P (rising constant current I ′ _UP (m
A) and the falling constant current I ′ _{DOW N} (mA)). As is clear from this figure, the current amount (magnitude) of the rising constant current I ′ _UP gradually decreases as the charge pump output voltage CP increases, and the current amount (magnitude) of the falling constant current I ′ _DOWN increases. ) Gradually increases as the charge pump output voltage CP increases. Therefore, a specific point (the rising constant current _I'UP and the falling constant current I '
Except) where the _DOWN intersect, increases the constant current I 'the current amount of the _UP (magnitude) and a lowered constant current I' the current amount of the _DOWN (size) and do not match. That is, it can be seen that the current balance has been lost.

In order to reduce the worst case reference noise of the local signal, the conventional problem is addressed by adjusting the loop filter band of the PLL frequency synthesizer circuit.

Various prior arts related to the present invention are also known. For example, Japanese Patent Application Laid-Open No. 7-106959 (hereinafter referred to as “prior art 1”) discloses a phase locked loop circuit including a charge pump circuit so as to shorten the synchronization pull-in time without impairing jitter characteristics after synchronization. A "phase-locked loop" is described. That is, in the phase synchronization circuit described in the prior art 1, the charge pump circuit includes a comparator, a first AND circuit, an inverter, a second AND circuit, a PMOS transistor, and an NMOS transistor. I have. The comparator compares the output voltage of the loop filter with a reference voltage and outputs a level determination signal. The first AND circuit is
The logical AND of the output UP of the phase comparator and the level determination circuit is output. The inverter inverts and outputs the output DOWN of the phase comparator. The second AND circuit outputs a logical product of the output signal of the inverter and the level determination signal. In the PMOS transistor, a source is connected to a power supply via a first constant current source, an output signal of the first AND circuit is input to a gate, and a drain is connected to an input side of the loop filter. In the NMOS transistor, the drain is connected to the input side of the loop filter, and the second AND gate is connected to the gate.
The output signal of the circuit is input, and the source is connected to the ground via a second constant current source.

Japanese Patent Application Laid-Open No. 8-204549 (hereinafter referred to as "prior art 2") describes a "charge pump circuit" which suppresses variations in gain. In the prior art 2, the first current source generates a current for charging up the voltage of the output terminal, outputs the generated current to the first switch circuit, and charges the output circuit in accordance with a signal applied to the first input terminal. Outputs the current that increases. The second current source generates a current for discharging the voltage of the output terminal, outputs the generated current to the second switch circuit, and outputs a current for discharging to the output circuit in accordance with a signal applied to the second input terminal. A first switch circuit and an output circuit,
Are connected to each other by a current mirror circuit. With such a configuration, variation in the gain of the charge pump circuit due to constituent elements can be suppressed to variation in the current source.

Further, Japanese Patent Application Laid-Open No. 8-307254 (hereinafter referred to as "prior art 3") discloses a "synchronous clock generation circuit" in which the lock-in time is short and the jitter after locking is small. . That is, in Prior Art 3,
The lock detection circuit outputs the signals / UP, DO from the phase comparator.
Based on WN, the absolute value of the phase difference between external clock signal REF and internal clock signal OSC is detected, and a signal corresponding to the absolute value of the phase difference is output to the current conversion circuit. The current conversion circuit sets the current value of the current source of the charge pump circuit to a large value when the absolute value of the phase difference is large, and sets the current value to a small value when the absolute value is small. Therefore, the output potential (control voltage) of the loop filter sharply increases before locking, and stabilizes after locking.

Furthermore, Japanese Patent Application Laid-Open No. Hei 9-116430 (hereinafter referred to as "prior art 4") discloses that the output current gain is automatically switched without increasing the number of charge pumps, thereby achieving fast lock-up. Possible "frequency synchronization circuit"
Is disclosed. That is, in the prior art 4, the gain of the output current is controlled in the gain control section of the current control means by the signal of the gain control signal generation means, and the basic operation section of the current control means is controlled by the output of the phase comparator. High-speed lockup is achieved by performing an operation or a sink operation.

[0022]

However, in digital communication systems in recent years, the requirements for both the definition of reference noise of local signals and the definition of lock-up time, which is a trade-off item, have become strict. Therefore, it is difficult to satisfy these requirements only by adjusting the loop filter band as described above.

Accordingly, an object of the present invention is to provide a PLL frequency synthesizer circuit having a charge pump circuit, which can satisfy the requirement for defining reference noise of a local signal.

Another object of the present invention is to provide a PLL frequency synthesizer circuit provided with a charge pump circuit, which can satisfy a requirement for a lock-up time, which is a trade-off item.

In the prior art 1 described above, the synchronous pull-in is performed by controlling the rising and falling instruction signals supplied to the PMOS transistor and the NMOS transistor, which are switching means, according to the control voltage output from the loop filter. It only discloses a technical idea for reducing the time, but does not describe anything about reducing reference noise of a local signal (output signal).

The above-mentioned prior art 2 discloses only the technical idea of suppressing the variation in the gain of the charge pump circuit due to the variation in the threshold level of the transistor and reducing the dead band. There is no description about reducing the reference noise of the output signal).

Further, in the prior art 3 described above, at the time of unlocking, the control voltage of the loop filter sharply rises (or falls) by setting the current value of the current source constituting the charge pump circuit to a large value. It merely discloses a technical idea for shortening the lock-in time, but does not describe anything about reducing reference noise of a local signal (output signal).

Furthermore, the above-mentioned prior art 4 only discloses the technical idea of controlling the gain of the output current of the charge pump circuit, which is the current control means, and merely discloses the reference noise of the local signal (output signal). Nothing is said about reducing the amount of waste.

[0029]

The present invention employs the following technical structure to achieve the above object. That is, according to the present invention, in the above-described PLL current output type charge pump circuit, a circuit for correcting a current balance deviation according to a charge pump output voltage (or control voltage) is provided in a current source portion constituted by a current mirror circuit. It is characterized by having been provided.

More specifically, according to the first aspect of the present invention, there is provided a charge pump circuit used in a PLL frequency synthesizer circuit, wherein an output terminal is provided in response to a rising instruction signal supplied from a phase comparator. Out of the control current to the loop filter to charge a capacitor constituting the loop filter, and in response to a falling instruction signal supplied from the phase comparator, a control current is supplied from the loop filter to the output terminal. A charge pump circuit that applies a charge pump output voltage from the output terminal to the loop filter by discharging the charge stored therein and discharging the charge stored in the capacitor. A rising constant current source flowing; connected between the rising constant current source and the output terminal, the rising in response to the rising instruction signal; First transistor switching means for controlling the flow of current to the output terminal; a constant current source connected to the ground terminal for flowing a constant current to the ground terminal; a constant current source and the output terminal; A second transistor switching means connected between the output terminal, the output terminal, the rising constant current source, and the falling constant current, for controlling the inflow of the falling constant current from the output terminal in response to the falling instruction signal. And a rising correction current corresponding to a variation of the rising constant current and the falling constant current, respectively, with respect to the rising constant current source and the falling constant current source in accordance with the charge pump output voltage. And current correction means for applying a falling correction current; and in almost all fluctuation ranges of the charge pump output voltage, the rising constant current and the falling constant current The charge pump circuit is obtained, wherein substantially it has the same the of can.

According to a second aspect of the present invention, a loop filter including a capacitor and generating a voltage between terminals of the capacitor as a control voltage; an output signal having an output frequency in response to the control voltage A variable frequency divider that divides the output signal based on a variable frequency division ratio to generate a frequency-divided signal; and an input signal having an input frequency and the frequency-divided signal. A phase comparator for detecting a phase frequency difference between the input signal and the frequency-divided signal to generate a rising instruction signal and a falling instruction signal indicating the phase frequency difference; To charge the capacitor and discharge the control current from the loop filter to discharge the charge stored in the capacitor in response to the descending instruction signal. And a charge pump circuit for applying a charge pump output voltage to the loop filter. The charge pump circuit is connected to a power supply terminal and has a rising constant current flowing from the power supply terminal. A first transistor switching means connected between the rising constant current source and the output terminal for controlling the rising constant current to flow to the output terminal in response to the rising instruction signal; A falling constant current source connected to the terminal and flowing a falling constant current to the ground terminal; connected between the falling constant current source and the output terminal;
Second transistor switching means for controlling inflow of the falling constant current from the output terminal in response to the falling instruction signal; connected to the output terminal, the rising constant current source, and the falling constant current source; A rise correction current and a fall correction current corresponding to the fluctuations of the rise constant current and the fall constant current are respectively applied to the rise constant current source and the fall constant current source in accordance with the charge pump output voltage. And a current correcting means; wherein the magnitudes of the rising constant current and the falling constant current are substantially the same in almost all fluctuation ranges of the charge pump output voltage. Is obtained.

Further, according to a third aspect of the present invention, there is provided a mobile communication device characterized in that the PLL frequency synthesizer circuit is used as a local oscillator that oscillates the output signal as a local signal.

According to a fourth aspect of the present invention, there is provided a charge pump circuit used in a PLL frequency synthesizer circuit, wherein a loop filter is provided from a pump output terminal in response to a rising instruction signal supplied from a phase comparator. The control current flows out to charge the capacitor constituting the loop filter with electric charge, and in response to the falling instruction signal supplied from the phase comparator, the control current flows from the loop filter to the pump output terminal. A charge pump circuit that outputs a control voltage from a filter output terminal of the loop filter by discharging the electric charge stored in the capacitor. A source connected between the rising constant current source and the pump output terminal, the rising in response to the rising instruction signal; First transistor switching means for controlling the flow of current to the pump output terminal; a falling constant current source connected to the ground terminal for flowing a falling constant current to the ground terminal; the falling constant current source and the pump output A second transistor switching means connected between the pump output terminal and the filter output terminal, the filter output terminal and the rising constant current source; The rising constant current source is connected to the falling constant current source, and the rising constant current source and the falling constant current source rise in response to the control voltage, respectively. Current correction means for applying a correction current and a fall correction current; and in a case where the rise constant current and the fall constant current are large in almost all fluctuation ranges of the control voltage. The charge pump circuit is obtained, wherein substantially it has the same the of.

According to a fifth aspect of the present invention, there is provided a loop filter including a capacitor, wherein a voltage between terminals of the capacitor is generated as a control voltage from a filter output terminal;
A voltage controlled oscillator that generates an output signal having an output frequency in response to the control voltage; a variable frequency divider that divides the output signal based on a variable frequency division ratio to generate a divided signal; An input signal having an input frequency and the divided signal are received, a phase frequency difference between the input signal and the divided signal is detected, and a rising instruction signal and a falling instruction signal indicating the phase frequency difference are detected. In response to the rising instruction signal, discharging a control current from a pump output terminal to the loop filter to charge the capacitor, and in response to the falling instruction signal, A control circuit that outputs a control voltage from the filter output terminal of the loop filter by discharging a charge stored in the capacitor by flowing a control current from the filter to the pump output terminal. PLL having a; and charge pump circuit
In the frequency synthesizer circuit, the charge pump circuit is connected to a power supply terminal, and a rising constant current source for flowing a rising constant current from the power terminal; connected between the rising constant current source and the pump output terminal; First transistor switching means for controlling the flow of the rising constant current to the pump output terminal in response to a rising instruction signal; a falling constant current source connected to a ground terminal and flowing a falling constant current to the ground terminal; A second transistor switching means connected between the falling constant current source and the pump output terminal for controlling inflow of the falling constant current from the pump output terminal in response to the falling instruction signal; Connected to a filter output terminal, the rising constant current source, and the falling constant current source, and according to the control voltage, for the rising constant current source and the falling constant current source, Current correction means for adding a rise correction current and a fall correction current corresponding to the fluctuations of the rise constant current and the fall constant current, respectively, in the entire range of fluctuation of the control voltage. A PLL frequency synthesizer circuit characterized in that the magnitudes of the constant current and the falling constant current are substantially the same.

Further, according to a sixth aspect of the present invention, there is provided a mobile communication device characterized in that the PLL frequency synthesizer circuit is used as a local oscillator that oscillates the output signal as a local signal.

[0036]

The charge pump circuit according to the present invention is different from the conventional charge pump circuit in that a current correction circuit (feedback circuit) having a charge pump output voltage (or control voltage) as an input is provided. Is configured to supply a correction current to the current source. This current correction circuit (feedback circuit) corrects positive feedback on the rising side and negative feedback correction on the falling side with respect to the output voltage (or control voltage) of the charge pump, and outputs the charge pump output voltage (or control voltage). Charge pump output voltage (or control voltage) for rising / falling charge pump output current fluctuations caused by fluctuations
By adding a correction current according to the above, an operation of suppressing the fluctuation of the charge pump output current is performed. Therefore, in the charge pump circuit according to the present invention, the current balance of the charge pump output current is greatly improved as compared with the conventional charge pump circuit. As a result, the effect of improving the reference noise of the local signal generated between the selected channels can be obtained.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a PLL frequency synthesizer circuit to which the charge pump circuit according to the present invention is applied will be described with reference to FIG.

The PLL frequency synthesizer circuit shown in FIG.
A loop filter (LF) 20 and a voltage-controlled oscillator (V
CO) 30, a variable frequency divider 40, and a phase comparator (PF)
D) 50 and a charge pump circuit (hereinafter also referred to as a “CP circuit”) 60.

The loop filter 20 includes a capacitor 21 and operates as a low-pass filter. The voltage between the terminals of the capacitor 21 is supplied from the filter output terminal 20a to the control voltage Vc
Generate as The voltage-controlled oscillator 30 has a control voltage Vc
Generates an output signal S _out having an output frequency f _out . The variable frequency divider 40 divides the frequency of the output signal S _{out based} on the variable frequency division ratio (1 / N) to generate a frequency-divided signal S _{1 / N.} Phase frequency difference Δf between the phase comparator 50 the input frequency f _in the input signal receiving an S _in a divided signal S _{1 / N} with the input signal S _{i n} a divided signal S _{1 / N} To generate a pulse-like rising instruction signal UP and a falling instruction signal DOWN indicating the phase frequency difference Δf.

The charge pump circuit 60 has a rising instruction signal U
In response to P, the control current Ip (rising constant current I _UP ) flows out to the loop filter 20 to charge the capacitor 21. Further, the charge pump circuit 60 receives the control current Ip (falling current I _DOWN ) from the loop filter 20 in response to the falling instruction signal DOWN, and supplies the capacitor 2
The electric charge stored in 1 is discharged. The control current Ip is also called a charge pump output current. Anyway, the charge pump circuit 60 applies the charge pump output voltage CP from the pump output terminal 63 to the loop filter 20.

The PLL frequency synthesizer circuit having such a configuration is used as a local oscillator for selecting a mobile communication device. In this case, the output signal S _out
Are used as local signals. And P for it
In the LL frequency synthesizer circuit, as described above, it is necessary to reduce the reference noise of the local signal S _out and realize a high-speed setup.

Referring to FIG. 1, a charge pump circuit 60 according to the first embodiment of the present invention will be described. The illustrated charge pump circuit 60 includes a CP current correction circuit unit 9.
It has basically the same configuration as that shown in FIG. Therefore, those having the same functions as those shown in FIG. 5 are denoted by the same reference numerals.

The charge pump circuit 60 includes the phase comparator 5
0 (FIG. 4), a first input terminal 61 for inputting a rising instruction signal UP, and a falling instruction signal DO from the phase comparator 50.
A second input terminal 62 for inputting the WN, the pump output terminal 62 to the inlet / outlet, the power supply voltage Vcc is supplied to the control current (charge pump output current) I _P loop filter 20 (FIG. 4) A power terminal 64 and a ground terminal 65
With The rising instruction signal UP is an active low signal, and the falling instruction signal DOWN is an active high signal. The first input terminal 61 is called a rising instruction input terminal, and the second input terminal 62 is called a falling instruction input terminal.

The charge pump circuit 60 includes a first P-channel MOSFET 71 connected to a rising instruction input terminal 61 and serving as first transistor switching means;
A first N-channel MOSF connected to a falling instruction input terminal 62 and serving as second transistor switching means
The ET 81 includes a rising constant current source and a falling constant current source for determining a rising constant current I _UP and a falling constant current I _DOWN, which will be described later, and a CP current correction circuit 90. Note that the first P-channel MOSFET 71 and the first N-channel M
The drains of the OSFET 81 are connected to each other and are connected to the pump output terminal 63.

More specifically, the charge pump circuit 60 includes:
First and second constant current sources 70-1 and 70-2 for flowing a constant current I, and second to fifth P-channel MOSFETs
72, 73, 74, and 75, and second and third N-channel MOSFETs 82 and 83.

One end of the first constant current source 70-1 is connected to the ground terminal 65, and the other end is a second P-channel MOSFET.
72 drain, i.e., is connected to the first connection point N _1. The source of the second P-channel MOSFET 72 is connected to the power supply terminal 64, and the gate is connected to the drain of the second P-channel MOSFET 72 and the third P-channel MOSFET.
It is connected to the gate of the FET 73. The source of the third P-channel MOSFET 73 is connected to the power supply terminal 64. That is, the second and third P-channel MOSFs
ETs 72 and 73 serve as first current mirror circuits. The drain of the third P-channel MOSFET 73 is connected to the source of the first P-channel MOSFET 71. Therefore, the first constant current source 70-1 and the first current mirror circuit (the second and third P-channel MOSFs)
The combination with the ETs 72 and 73) operates as the rising constant current source for determining the rising constant current I _UP . Further, the first P-channel MOSFET 71 is connected to the rising constant current I _UP
Operate as a first drive transistor for driving the transistor.

One end of the second constant current source 70-2 is connected to the ground terminal 65, and the other end is connected to a fifth P-channel MOS
The drain of FET 75, that is, is connected to the second connecting point N _2. The source of the fifth P-channel MOSFET 75 is connected to the power supply terminal 64, and the gate is connected to the drain of the fifth P-channel MOSFET 75 and the gate of the fourth P-channel MOSFET 74. 4th P
The source of the channel MOSFET 74 is connected to the power supply terminal 64. That is, the fifth and fourth P-channel M
OSFETs 75 and 74 serve as a second current mirror circuit.

The drain of the fourth P-channel MOSFET 73 is connected to the drain of the second N-channel MOSFET 82. The source of the second N-channel MOSFET 82 is connected to the ground terminal 65, and the gate is connected to the drain of the second N-channel MOSFET 82 and the gate of the third N-channel MOSFET 83. Third N
The source of the channel MOSFET 83 is connected to the ground terminal 65. That is, the second and third N channels M
OSFETs 82 and 83 serve as a third current mirror circuit. The drain of the third N-channel MOSFET 83 is connected to the source of the first N-channel MOSFET 81. Therefore, the second constant current source 70-2 and the second current mirror circuit (the fifth and fourth P-channel M
OSFETs 75 and 74) and a third current mirror circuit (second and third N-channel MOSFETs 82 and 8).
The combination with 3) operates as the falling constant current source for determining the falling constant current I _DOWN . The first N-channel MOSFET 81 operates as a second drive transistor for driving the falling constant current I _DOWN .

In any case, charge pump circuit 60 is provided with a third P-channel MOSF which forms a part of a rising constant current source.
ET73, a first P-channel MOSFET 71 acting as a first driving transistor, a first N-channel MOSFET 81 acting as a second driving transistor, and a third N-channel MOSFET forming a part of a falling constant current source.
It has a configuration in which four elements ET83 are connected in series between a power supply terminal 64 and a ground terminal 65.

The CP current correction circuit 90 supplies a rising constant current I _UP and a falling constant current I _UP to a rising constant current source and a falling constant current source, respectively, according to the charge pump output voltage CP.
_This is a circuit for adding a rise correction current I _upH and a fall correction current I _downH for correcting a deviation of the _DOWN current balance.

More specifically, the CP current correction circuit 90 includes a bias input terminal 91 to which the bias voltage Bias is supplied,
First and second amplifiers 92 and 93, first and second NPN bipolar transistors 94 and 95,
And second resistors 96 and 97.

The first amplifier 92 has a bias input terminal 91
Input terminal 92a connected to the pump output terminal 6
3 and a non-inverting input terminal 92b. The second amplifier 93 has an inverting input terminal 93a connected to the pump output terminal 63 and a non-inverting input terminal 93b connected to the bias input terminal 91. An output terminal 92c of the first amplifier 92 is connected to a first NPN bipolar transistor 94.
Output terminal 93 of the second amplifier 93
c is connected to the base of the second NPN bipolar transistor 95. The collector of the first NPN bipolar transistor 94 is a second P-channel MOSFET.
The first constant current source 70-1 is connected to a _first connection point N1 between the drain 72 and the first constant current source 70-1. The collector of the second NPN bipolar transistor 95 is a fifth P-channel MOS.
It is connected to the _second connection point N2 between the drain of the FET 75 and the second constant current source 70-2. The emitter of the first NPN bipolar transistor 94 is connected to a first resistor 96.
Is connected to a ground terminal 65 via a second resistor 97.
Is connected to the ground terminal 65 via the.

In such a configuration, the rising correction current I _upH
Bypasses the first constant current source 70-1 and connects the ground terminal 65 from the drain of the second P-channel MOSFET 72 via the collector and emitter of the first NPN bipolar transistor 94 and the first resistor 96. Flows to The falling correction current I _downH is supplied to the second constant current source 70-2.
Flows from the drain of the fifth P-channel MOSFET 75 to the ground terminal 65 via the collector and emitter of the second NPN bipolar transistor 95 and the second resistor 97. As a result, the rising correction current I _upH and the falling correction current I _downH are added to the rising constant current source and the falling constant current source, respectively. In other words, the rising constant current I _UP and the falling constant current I _DOWN correspond to the conventional rising constant current I ′ _UP and the conventional falling constant current I ′ _{DOWN, respectively.
Is} equal to a value _obtained by adding the rise correction current I _upH and the fall correction current I _downH to the current _state . That is, I _UP = I ' _UP + I _upH I _DOWN = I' _DOWN + I _downH .

Anyway, the first amplifier 92 and the first NP
The combination of the N-type bipolar transistor 94 and the first resistor 96 causes the rising correction current I to be supplied to the rising constant current source based on the bias voltage Bias according to the charge pump output voltage CP.
_{It operates} as a rising current correction circuit that adds _upH . In other words, the first NPN bipolar transistor 94
It is used to convert the output voltage of the first amplifier 92 into a current and add the rising correction current I _upH to a rising constant current source.

Similarly, the second amplifier 93 and the second NPN
The combination of the bipolar transistor 95 and the second resistor 97 supplies the falling correction current I to the falling constant current source based on the bias voltage Bias according to the charge pump output voltage CP.
_{It operates} as a falling current correction circuit that adds _downH . In other words, the second NPN bipolar transistor 95
Is used to convert the output voltage of the second amplifier 93 into a current, and add the falling correction current I _downH to a falling constant current source.

As described above, in the present embodiment, the bipolar transistor is used in view of the linearity of the voltage-current conversion. However, a MOS transistor may be used instead of the bipolar transistor for the current conversion.

Here, in the rising current correction circuit, the charge pump output voltage CP and the bias voltage Bias are supplied to the non-inverting input terminal 92b and the inverting input terminal 92a of the first amplifier 92, respectively. Positive feedback correction is applied to the rising current source with respect to the voltage CP. Therefore, as the charge pump output voltage CP increases, the current amount (magnitude) of the increase correction current I _upH increases.

On the other hand, in the falling current correction circuit, the charge pump output voltage CP and the bias voltage Bi
Since as is supplied to the inverting input terminal 93a and the non-inverting input terminal 93b of the second amplifier 93, the charge pump output voltage CP is subjected to negative feedback correction to the falling current source. Therefore, as the charge pump output voltage CP increases, the falling correction current I
The current amount (magnitude) of _downH decreases.

On the other hand, as shown in FIG. 6, the current amount (magnitude) of the conventional rising constant current I ' _UP and the conventional falling constant current I' _DOWN are respectively different from the charge pump output voltage CP.
Decrease and increase with increasing. As a result, as shown in FIG. 2, the current amounts (magnitudes) of the rising constant current I _UP and the falling constant current I _DOWN change in almost all the fluctuation ranges in which the charge pump output voltage CP fluctuates (for example,
0.5V to (Vcc-0.5V)). In other words, the charge pump circuit 60 according to the first embodiment has a constant current I
The current balance between the _UP and the falling constant current I _DOWN can be maintained. That, CP current correction times 90, the charge pump output current I _P of the variation with respect to the charge pump output voltage CP (or the control voltage Vc outputted from the filter output terminal 20a of the loop filter 20) a correction current corresponding to by adding, the operation of suppressing variation of the charge pump output current I _P.

The charge pump circuit 60 having such a configuration is described.
In, the ON / OFF operation of the first P-channel MOSFET71 and the first N-channel MOSFET 81, by controlling the flow of effluent and lowering the constant current I _DOWN increase the constant current I _UP, the loop filter 20 (FIG. 4) Control current (charge pump output current) I _P
Outflow / inflow. In other words, the phase comparator 5
In response to the pulse widths of the rising instruction signal UP and the falling instruction signal DOWN supplied from 0 (FIG. 4), the charge pump circuit 60 performs an operation of sending charges to the loop filter 20 and extracting charges from the loop filter 20. I do. The filter output terminal 20a of the loop filter 20
The output frequency f _out of the output signal S _out generated from the voltage controlled oscillator 30 (FIG. 4) changes depending on the control voltage Vc output from the control voltage Vc.

Therefore, when the PLL frequency synthesizer circuit having the charge pump circuit 60 having such a configuration is used as a local oscillator for selecting a mobile communication device, the rising / falling side of the charge pump circuit 60 is reduced. By supplying correction current to each current source,
Since the current balance between the rising and falling constant currents of the charge pump circuit 60 is corrected, the rising constant current I _UP and the falling constant current I
_{The DOWN} current balance is greatly improved, and the signal purity of the local signal generated between the selected channels can be improved.

Referring to FIG. 3, a description will be given of a charge pump circuit 60A according to a second embodiment of the present invention.
The illustrated charge pump circuit 60A has the same basic configuration and operation as those shown in FIG. 1 except that the configuration of the CP current correction circuit is changed. Therefore,
The CP current correction circuit is denoted by reference numeral 90A,
Those having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. Only the differences will be described below.

The CP current correction circuit 90A has the same configuration as that of FIG. C shown
It has the same configuration as the P current correction circuit unit 90.

The sixth P-channel MOSFET 98 has a first connection point N ₁ between the collector of the first NPN bipolar transistor 94, the drain of the second P-channel MOSFET 72, and the first constant current source 70-1. Has been inserted between. Specifically, the sixth P-channel MOSF
The gate of the ET 98 is connected to the lock input terminal 100, the drain is connected to the collector of the first NPN bipolar transistor 94, and the sources are the drain of the second P-channel MOSFET 72 and the first constant current source 70-1.
Is connected to a _first connection point N1.

On the other hand, the seventh P-channel MOSFET 99
Has a collector of the second NPN bipolar transistor 95 is inserted between the second connecting point N ₂ between the drain and the second constant current source 70-2 of the fifth P-channel MOSFET 75. Specifically, the seventh P-channel MO
The gate of the SFET 99 is connected to the lock input terminal 100, the drain is connected to the collector of the second NPN bipolar transistor 95, and the sources are the drain of the fifth P-channel MOSFET 75 and the second constant current source 70-.
2 is connected to a _second connection point N2.

That is, the sixth and seventh P-channel M
OSFETs 98 and 99 are provided with a PLL lock signal Lock.
And operates as switching means for switching the correction control of the charge pump current in accordance with. The sixth and seventh P-channel MOSFETs 98 and 99 are turned off when the lock signal Lock of the PLL indicates a logic L level at the time of unlocking, and turned on when the lock signal Lock indicates a logic H level at the time of locking. I do. The reason for providing this switching means is as follows.

That is, in the charge pump circuit 60 shown in FIG. 1, when the frequency is switched, the original PLL loop control and the current correction control of the CP current correction circuit section 90 perform a double feedback operation, thereby stabilizing the loop. This is because there is a concern about delays in lock-up time and performance. To prevent it,
In the CP current correction circuit 90A, the charge pump current correction control is turned off when unlocking during frequency switching,
During a call after locking, an operation of turning on the charge pump current correction control is performed to reduce reference noise.

The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the spirit of the present invention. For example, in the embodiment described above, CP current correction circuit, is performed to correct the charge pump output current I _P according to the charge pump output voltage CP which is output from the pump output terminal 63 of the charge pump circuit, loop it may be performed to correct the charge pump output current I _P according to the control voltage Vc output from the filter output terminal 20a of the filter 20.

[0070]

As described above, according to the present invention, the correction current is supplied to each of the current sources on the rising / falling sides according to the charge pump output voltage or the control voltage, so that the current of the rising / falling constant current is increased. Since the balance can be improved, it is possible to improve the reference noise of the local signal generated between the selected channels.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of charge pump currents of the charge pump circuit shown in FIG. 1 and the conventional charge pump circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a charge pump circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a PLL frequency synthesizer circuit to which the charge pump circuit according to the present invention is applied.

FIG. 5 is a block diagram showing a configuration of a conventional charge pump circuit.

6 is a diagram showing characteristics of a charge pump current of the conventional charge pump circuit shown in FIG.

[Explanation of symbols]

 60, 60A Charge pump circuit 61, 62 Input terminal 63 Output terminal 64 Power supply terminal 65 Ground terminal 70-1, 70-2 Constant current source 71-75 P-channel MOSFET 81-83 N-channel MOSFET 90, 90A CP current correction circuit section 91 Bias input terminal 92,93 Amplifier 94,95 NPN type bipolar transistor 96,97 Resistor 98,99 P-channel MOSFET 100 Lock input terminal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC21 CC38 CC41 CC53 DD32 EE19 GG15 HH03 JJ08 KK03 KK26 PP03 QQ08 QQ09

Claims (36)

[Claims] 1. A charge pump circuit used in a PLL frequency synthesizer circuit, wherein a control current flows from an output terminal to a loop filter in response to a rising instruction signal supplied from a phase comparator. In response to a falling instruction signal supplied from the phase comparator, a control current flows from the loop filter to the output terminal to discharge the charge stored in the capacitor. Thus, in the charge pump circuit that applies a charge pump output voltage from the output terminal to the loop filter, the charge pump circuit is connected to a power supply terminal, and supplies a rising constant current from the power supply terminal. Connected to the output terminal to control the rising constant current to flow to the output terminal in response to the rising instruction signal. 1 transistor switching means, connected to a ground terminal, a falling constant current source for flowing a falling constant current to the ground terminal, connected between the falling constant current source and the output terminal, and responsive to the falling instruction signal. A second transistor switching means for controlling the inflow of the falling constant current from the output terminal; connected to the output terminal, the rising constant current source, and the falling constant current source; Accordingly, a current correction means is provided for applying a rise correction current and a fall correction current corresponding to the variation of the rise constant current and the fall constant current to the rise constant current source and the fall constant current source, respectively. The magnitudes of the rising constant current and the falling constant current are made substantially the same in almost all fluctuation ranges of the charge pump output voltage. The charge pump circuit that. 2. The first transistor switching means has a first P-channel electric field having a source connected to the rising constant current source, a gate supplied with the rising instruction signal, and a drain connected to the output terminal. A first N-channel electric field having a source connected to the falling constant current source, a gate supplied with the falling instruction signal, and a drain connected to the output terminal. 2. The charge pump circuit according to claim 1, comprising an effect transistor, wherein each of the rising constant current source and the rising constant current source is configured by a combination of a constant current source and a current mirror circuit. 3. The rising constant current source, a first constant current source having one end connected to the ground terminal and the other end connected to a first connection point, and a drain connected to the first connection point. A second P-channel field effect transistor having a gate connected and a source connected to the power supply terminal, a gate connected to the first connection point, a source connected to the power supply terminal, and a drain connected to the first power supply terminal; A first current mirror circuit comprising a third P-channel field-effect transistor connected to the source of the P-channel field-effect transistor of the first embodiment, wherein the falling constant current source has one end connected to the ground terminal, A second constant current source having the other end connected to a second connection point; a fourth P-channel field effect transistor having a gate connected to the second connection point and a source connected to the power supply terminal; , Said A second current mirror circuit including a fifth P-channel field-effect transistor having a drain and a gate connected to a connection point of No. 2 and a source connected to the power supply terminal; A second N-channel field effect transistor having a drain and a gate connected to a drain and a source connected to the ground terminal; and a gate connected to a drain of the fourth P-channel field effect transistor, and a source connected to the ground terminal. And a third current mirror circuit including a third N-channel field-effect transistor having a drain connected to a source of the first N-channel field-effect transistor. Item 3. The charge pump circuit according to Item 2. 4. The current correction means has a bias input terminal to which a bias voltage is supplied, and the current correction means is connected to the output terminal, the bias input terminal, and the first connection point, Rising current correcting means for flowing the rising correction current from the first connection point to the ground terminal by bypassing the first constant current source based on the bias voltage in accordance with a charge pump output voltage; Terminal, the bias input terminal, and the second connection point, and bypasses the second constant current source from the second connection point based on the bias voltage according to the charge pump output voltage. 4. The charge pump circuit according to claim 3, further comprising: a descending current correcting unit that supplies the descending correction current to the ground terminal. 5. The rising current correction unit applies a positive feedback correction to the charge pump output voltage to supply the rising correction current, and the falling current correction unit applies a negative feedback to the charge pump output voltage. 5. The charge pump circuit according to claim 4, wherein said falling correction current is applied after correcting the feedback. 6. A first amplifier having an inverting input terminal connected to the bias input terminal and a non-inverting input terminal connected to the output terminal, wherein the rising current correction means includes an output terminal of the first amplifier. A first NPN bipolar transistor having a collector connected to the first connection point, one end connected to the emitter of the first NPN bipolar transistor, and the other end connected to the ground terminal. Connected first
A second amplifier having a non-inverting input terminal connected to the bias input terminal, and an inverting input terminal connected to the output terminal; A second NPN-type bipolar transistor having a base connected to the output terminal of the second NPN-type bipolar transistor and a collector connected to the second connection point; one end connected to the emitter of the second NPN-type bipolar transistor; The second connected to the ground terminal
The charge pump circuit according to claim 5, wherein the charge pump circuit comprises: 7. The current correction means has a bias input terminal to which a bias voltage is supplied, and a lock input terminal to which a lock signal indicating one of unlocking and locking is supplied. The means is connected to the output terminal, the bias input terminal, the lock input terminal, and the first connection point, and when the lock signal indicates unlocking, performs correction control by the rise correction current. Off, and when the lock signal indicates a lock state, bypassing the first constant current source from the first connection point based on the bias voltage according to the charge pump output voltage. A rising current correction means for flowing the rising correction current to the ground terminal, the lock terminal being connected to the output terminal, the bias input terminal, the lock input terminal, and the second connection point; When the lock signal indicates unlocking, the correction control based on the descending correction current is turned off. And descent current correction means for flowing the descent correction current from the second connection point to the ground terminal bypassing the second constant current source. A charge pump circuit as described. 8. The rising current correction means applies a positive feedback correction to the charge pump output voltage to flow the rising correction current when the lock signal indicates a lock state, 8. The charge according to claim 7, wherein the correction unit applies the negative feedback correction to the charge pump output voltage to flow the falling correction current when the lock signal indicates a lock state. Pump circuit. 9. The lock signal is a signal which takes a logic L level when unlocked and a logic H level when locked, wherein the rising current correction means has an inverting input terminal connected to the bias input terminal, and A first amplifier having a non-inverting input terminal connected to the terminal, a sixth P-channel field effect transistor having a gate connected to the lock input terminal, and a source connected to the first connection point; A first NPN-type bipolar transistor having a base connected to the output terminal of the first amplifier and a collector connected to the drain of the sixth P-channel field-effect transistor; and one end connected to the emitter of the first NPN-type bipolar transistor. And the other end is connected to the ground terminal.
A second amplifier having a non-inverting input terminal connected to the bias input terminal and an inverting input terminal connected to the output terminal; and a lock input terminal connected to the lock input terminal. A seventh P-channel field-effect transistor having a gate connected and a source connected to the second connection point; a base connected to an output terminal of the second amplifier; A second NPN-type bipolar transistor having a collector connected to the drain of the second NPN-type bipolar transistor, a second end connected to the emitter of the second NPN-type bipolar transistor, and the other end connected to the ground terminal.
9. The charge pump circuit according to claim 8, wherein the charge pump circuit comprises: 10. A loop filter including a capacitor and generating a voltage between terminals of the capacitor as a control voltage;
A voltage controlled oscillator that generates an output signal having an output frequency in response to the control voltage; a variable frequency divider that divides the output signal based on a variable frequency division ratio to generate a divided signal; An input signal having an input frequency and the divided signal are received, a phase frequency difference between the input signal and the divided signal is detected, and a rising instruction signal and a falling instruction signal indicating the phase frequency difference are detected. And a phase comparator for generating a control current; causing a control current to flow to the loop filter to charge the capacitor; and in response to the falling instruction signal, a control current flowing from the loop filter to be stored in the capacitor. A charge pump circuit for applying a charge pump output voltage from an output terminal to the loop filter by discharging the accumulated charge. A charge pump circuit connected to a power supply terminal, a rising constant current source for flowing a rising constant current from the power supply terminal, and connected between the rising constant current source and the output terminal; First transistor switching means for controlling the flow of the rising constant current to the output terminal, a falling constant current source connected to the ground terminal and supplying a falling constant current to the ground terminal, the falling constant current source and the output A second transistor switching means connected between the output terminal and the output terminal, the second transistor switching means being connected between the output terminal and the rising constant current source, for controlling the inflow of the falling constant current from the output terminal in response to the falling instruction signal. A constant current source connected to the charge pump output voltage, the rising constant current source and the falling constant current source, respectively, Current correction means for adding corresponding rise correction current and fall correction current, and in almost all fluctuation ranges of the charge pump output voltage, the magnitudes of the rise constant current and the fall constant current are substantially the same. A PLL frequency synthesizer circuit characterized in that: 11. The first transistor switching means has a first P-channel electric field having a source connected to the rising constant current source, a gate supplied with the rising instruction signal, and a drain connected to the output terminal. A first N-channel electric field having a source connected to the falling constant current source, a gate supplied with the falling instruction signal, and a drain connected to the output terminal. The rising constant current source has one end connected to the ground terminal,
A first constant current source having the other end connected to a first connection point; a second P-channel field effect having a drain and a gate connected to the first connection point and a source connected to the power supply terminal A transistor, a third P-channel field-effect transistor having a gate connected to the first connection point, a source connected to the power supply terminal, and a drain connected to the source of the first P-channel field-effect transistor; A first current mirror circuit comprising: a falling constant current source having one end connected to the ground terminal;
A second constant current source having the other end connected to a second connection point; a fourth P-channel field effect transistor having a gate connected to the second connection point and a source connected to the power supply terminal; A second current mirror circuit comprising: a fifth P-channel field-effect transistor having a drain and a gate connected to the second connection point, and a source connected to the power supply terminal; and the fourth P-channel electric field. A drain and a gate are connected to a drain of the effect transistor, and a gate is connected to a drain of the second N-channel field effect transistor whose source is connected to the ground terminal, and a source is connected to the drain of the fourth P-channel field effect transistor A third N-channel field-effect transistor connected to the ground terminal and having a drain connected to the source of the first N-channel field-effect transistor Claim 1, characterized in that it is composed; third current mirror circuit consisting of
0 PLL frequency synthesizer circuit. 12. The current correction means has a bias input terminal to which a bias voltage is supplied, wherein the current correction means is connected to the output terminal, the bias input terminal, and the first connection point, Rising current correcting means for flowing the rising correction current from the first connection point to the ground terminal by bypassing the first constant current source based on the bias voltage in accordance with a charge pump output voltage; Terminal, the bias input terminal, and the second connection point, and bypasses the second constant current source from the second connection point based on the bias voltage according to the charge pump output voltage. 12. The PLL frequency synthesizer circuit according to claim 11, further comprising: a descending current correcting means for flowing the descending correction current to the ground terminal. 13. The rising current correction means applies a positive feedback correction to the charge pump output voltage to flow the rising correction current, and the falling current correction means negatively applies the charge pump output voltage. 13. The PLL frequency synthesizer circuit according to claim 12, wherein the feedback correction is applied to cause the falling correction current to flow. 14. A rising amplifier comprising: a first amplifier having an inverting input terminal connected to the bias input terminal and a non-inverting input terminal connected to the output terminal; and an output terminal of the first amplifier. A first NPN bipolar transistor having a collector connected to the first connection point, one end connected to the emitter of the first NPN bipolar transistor, and the other end connected to the ground terminal. Connected first
A second amplifier having a non-inverting input terminal connected to the bias input terminal, and an inverting input terminal connected to the output terminal; A second NPN-type bipolar transistor having a base connected to the output terminal of the second NPN-type bipolar transistor and a collector connected to the second connection point; one end connected to the emitter of the second NPN-type bipolar transistor; The second connected to the ground terminal
14. The PLL frequency synthesizer circuit according to claim 13, further comprising a resistor. 15. The current correction means has a bias input terminal to which a bias voltage is supplied and a lock input terminal to which a lock signal indicating one of unlocking and locking is supplied. The means is connected to the output terminal, the bias input terminal, the lock input terminal, and the first connection point, and when the lock signal indicates unlocking, performs correction control by the rise correction current. Off, and when the lock signal indicates a lock state, bypassing the first constant current source from the first connection point based on the bias voltage according to the charge pump output voltage. A rising current correction means for flowing the rising correction current to the ground terminal, the rising terminal being connected to the output terminal, the bias input terminal, the lock input terminal, and the second connection point; When the signal indicates unlocking, the correction control based on the falling correction current is turned off, and when the lock signal indicates locking, the correction control based on the bias voltage is performed according to the charge pump output voltage. And a descent current correction means for flowing the descent correction current from the second connection point to the ground terminal by bypassing the second constant current source. A PLL frequency synthesizer circuit according to any of the preceding claims. 16. The rising current correction means applies a positive feedback correction to the charge pump output voltage and flows the rising correction current when the lock signal indicates a lock state. 16. The PLL according to claim 15, wherein the correction means applies the negative feedback correction to the charge pump output voltage to flow the falling correction current when the lock signal indicates a lock state. Frequency synthesizer circuit. 17. The lock signal is a signal which takes a logical L level when unlocked and a logical H level when locked. The rising current correction means has an inverting input terminal connected to the bias input terminal, and A first amplifier having a non-inverting input terminal connected to a terminal, a sixth P-channel field effect transistor having a gate connected to the lock input terminal, and a source connected to the first connection point; A first NPN-type bipolar transistor having a base connected to the output terminal of the first amplifier and a collector connected to the drain of the sixth P-channel field-effect transistor; and one end connected to the emitter of the first NPN-type bipolar transistor. And the other end is connected to the ground terminal.
A second amplifier having a non-inverting input terminal connected to the bias input terminal and an inverting input terminal connected to the output terminal; and a lock input terminal connected to the lock input terminal. A seventh P-channel field-effect transistor having a gate connected and a source connected to the second connection point; a base connected to an output terminal of the second amplifier; A second NPN-type bipolar transistor having a collector connected to the drain of the second NPN-type bipolar transistor, a second end connected to the emitter of the second NPN-type bipolar transistor, and the other end connected to the ground terminal.
The PLL frequency synthesizer circuit according to claim 15, wherein the PLL frequency synthesizer circuit comprises: 18. A mobile communication device using the PLL frequency synthesizer circuit according to claim 10 as a local oscillator that oscillates the output signal as a local signal. 19. A charge pump circuit used in a PLL frequency synthesizer circuit, wherein a control current flows out of a pump output terminal to a loop filter in response to a rising instruction signal supplied from a phase comparator. The capacitor constituting the filter is charged with electric charge, and in response to a descending instruction signal supplied from the phase comparator, a control current flows from the loop filter to the pump output terminal to charge the electric charge stored in the capacitor. A charge pump circuit configured to output a control voltage from a filter output terminal of the loop filter by discharging; a rising constant current source connected to a power supply terminal and flowing a rising constant current from the power supply terminal; Connected to the pump output terminal, the pump output terminal of the rising constant current in response to the rising instruction signal. First transistor switching means for controlling the outflow to the ground terminal; a falling constant current source connected to the ground terminal for flowing a falling constant current to the ground terminal; and a connection between the falling constant current source and the pump output terminal. A second transistor switching means for controlling inflow of the falling constant current from the pump output terminal in response to the falling instruction signal; a filter output terminal; the rising constant current source; and the falling constant current source. And connected to the rising constant current source and the falling constant current source according to the control voltage,
Current correction means for adding a rise correction current and a fall correction current corresponding to the variation of the rise constant current and the fall constant current, and in almost all the fluctuation range of the control voltage, the rise constant current and the fall A charge pump circuit wherein the magnitude of the constant current is substantially the same. 20. The first transistor switching means, wherein a source is connected to the rising constant current source, the gate is supplied with the rising instruction signal, and a drain is connected to the pump output terminal. The second transistor switching means comprises a first transistor having a source connected to the falling constant current source, a gate supplied with the falling instruction signal, and a drain connected to the pump output terminal. 20. The charge pump according to claim 19, comprising a channel field effect transistor, wherein each of the rising constant current source and the rising constant current source is configured by a combination of a constant current source and a current mirror circuit. circuit. 21. The rising constant current source, a first constant current source having one end connected to the ground terminal and the other end connected to a first connection point, and a drain connected to the first connection point. A second P-channel field effect transistor having a gate connected and a source connected to the power supply terminal, a gate connected to the first connection point, a source connected to the power supply terminal, and a drain connected to the first power supply terminal; A first current mirror circuit comprising a third P-channel field-effect transistor connected to the source of the P-channel field-effect transistor of the first embodiment, wherein the falling constant current source has one end connected to the ground terminal, A second constant current source having the other end connected to a second connection point; a fourth P-channel field effect transistor having a gate connected to the second connection point and a source connected to the power supply terminal; ,Previous A second current mirror circuit comprising: a fifth P-channel field-effect transistor having a drain and a gate connected to a second connection point and a source connected to the power supply terminal; and the fourth P-channel field-effect transistor A drain and a gate are connected to a drain of the second N-channel field-effect transistor whose source is connected to the ground terminal, and a gate is connected to a drain of the fourth P-channel field-effect transistor and the source is the ground. A third current mirror circuit connected to a terminal and having a drain connected to a source of the first N-channel field-effect transistor, and a third N-channel field-effect transistor. 21. The charge pump circuit according to claim 20, wherein: 22. The current correction means has a bias input terminal to which a bias voltage is supplied, and the current correction means is connected to the filter output terminal, the bias input terminal, and the first connection point, Rising current correction means for flowing the rising correction current from the first connection point to the ground terminal by bypassing the first constant current source based on the bias voltage in accordance with the control voltage; A terminal, the bias input terminal, and the second connection point. The second connection point is bypassed from the second connection point based on the bias voltage according to the control voltage. 22. The charge pump circuit according to claim 21, further comprising: a descending current correction unit that supplies the descending correction current to a ground terminal. 23. The rising current correction unit applies a positive feedback correction to the control voltage to flow the rising correction current, and the falling current correction unit performs a negative feedback correction on the control voltage. 23. The charge pump circuit according to claim 22, wherein the lowering correction current is applied to the charge pump. 24. A first amplifier having an inverting input terminal connected to the bias input terminal and a non-inverting input terminal connected to the filter output terminal; A first NPN bipolar transistor having a base connected to the terminal and a collector connected to the first connection point; one end connected to the emitter of the first NPN bipolar transistor, and the other end connected to the ground terminal The first connected to
A second amplifier in which a non-inverting input terminal is connected to the bias input terminal, and an inverting input terminal is connected to the filter output terminal. A second NPN-type bipolar transistor having a base connected to the output terminal of the amplifier and a collector connected to the second connection point; one end connected to the emitter of the second NPN-type bipolar transistor; A second terminal connected to the ground terminal;
24. The charge pump circuit according to claim 23, further comprising: a resistor. 25. The current correction means having a bias input terminal to which a bias voltage is supplied and a lock input terminal to which a lock signal indicating one of an unlocked state and a locked state is supplied. Means are connected to the filter output terminal, the bias input terminal, the lock input terminal, and the first connection point, and when the lock signal indicates unlocking, correction control by the rise correction current. Is turned off, and when the lock signal indicates a lock state, the first connection point is bypassed from the first connection point based on the bias voltage according to the control voltage. A rising current correction means for flowing the rising correction current to a ground terminal, the filter output terminal, the bias input terminal, the lock input terminal, and the second connection point; When the lock signal indicates the unlocking time, the correction control by the descent correction current is turned off.When the lock signal indicates the lock time, the correction control is performed based on the bias voltage according to the control voltage. 22. A descent current correction means for flowing the descent correction current from the second connection point to the ground terminal by bypassing the second constant current source. Charge pump circuit. 26. The rising current correction unit, wherein the rising current correction unit applies a positive feedback correction to the control voltage to flow the rising correction current when the lock signal indicates a lock state. 26. The charge pump circuit according to claim 25, wherein, when the lock signal indicates a lock state, the control voltage is subjected to negative feedback correction to flow the drop correction current. 27. The lock signal is a signal which takes a logical L level when unlocked and a logical H level when locked, wherein the rising current correction means has an inverting input terminal connected to the bias input terminal, A first amplifier having a non-inverting input terminal connected to an output terminal, a sixth P-channel field effect transistor having a gate connected to the lock input terminal, and a source connected to the first connection point; A first NPN-type bipolar transistor having a base connected to the output terminal of the first amplifier and a collector connected to the drain of the sixth P-channel field-effect transistor; and an emitter connected to the first NPN-type bipolar transistor. A first end connected to one end and the other end connected to the ground terminal;
A second amplifier having a non-inverting input terminal connected to the bias input terminal and an inverting input terminal connected to the filter output terminal; and the lock input terminal. A seventh P-channel field effect transistor having a gate connected to the second node and a source connected to the second connection point; a base connected to an output terminal of the second amplifier; A second NPN bipolar transistor having a collector connected to the drain of the transistor; a second NPN bipolar transistor having one end connected to the emitter of the second NPN bipolar transistor and the other end connected to the ground terminal.
27. The charge pump circuit according to claim 26, further comprising: a resistor. 28. A loop filter that includes a capacitor and generates a voltage between terminals of the capacitor as a control voltage from a filter output terminal; a voltage controlled oscillator that generates an output signal having an output frequency in response to the control voltage; A variable frequency divider that divides the output signal based on a variable frequency division ratio to generate a divided signal; and receives an input signal having an input frequency and the divided signal, and receives the input signal and the divided signal. A phase comparator for detecting a phase frequency difference between the frequency-divided signal and a rising instruction signal and a falling instruction signal indicating the phase frequency difference; The control current flows out to the loop filter to charge the capacitor, and in response to the falling instruction signal, the control current flows from the loop filter to the pump output terminal to cause the capacitor to charge. A charge pump circuit that outputs the control voltage from the filter output terminal of the loop filter by discharging the charge stored in the capacitor. A rising constant current source connected to the power supply terminal for flowing a rising constant current; and a pump connected between the rising constant current source and the pump output terminal, the pump of the rising constant current being responsive to the rising instruction signal. A first transistor switching means for controlling the outflow to the output terminal; a falling constant current source connected to the ground terminal for flowing a falling constant current to the ground terminal; and a connection between the falling constant current source and the pump output terminal. And a second transistor switch for controlling the inflow of the falling constant current from the pump output terminal in response to the falling instruction signal. A ring means, which is connected filter output terminal and the rise constant current source and the descending constant current source in response to said control voltage, to the increase in the constant current source and the descending constant current source, respectively,
Current correction means for adding a rise correction current and a fall correction current corresponding to the variation of the rise constant current and the fall constant current, and in almost all the fluctuation range of the control voltage, the rise constant current and the fall A PLL frequency synthesizer circuit wherein the magnitude of the constant current is substantially the same. 29. The first P-channel switching means, wherein the first transistor switching means has a source connected to the rising constant current source, a gate supplied with the rising instruction signal, and a drain connected to the pump output terminal. The second transistor switching means comprises a first transistor having a source connected to the falling constant current source, a gate supplied with the falling instruction signal, and a drain connected to the pump output terminal. The rising constant current source has one end connected to the ground terminal,
A first constant current source having the other end connected to a first connection point; a second P-channel field effect having a drain and a gate connected to the first connection point and a source connected to the power supply terminal A transistor, a third P-channel field-effect transistor having a gate connected to the first connection point, a source connected to the power supply terminal, and a drain connected to the source of the first P-channel field-effect transistor; A first current mirror circuit comprising: a falling constant current source having one end connected to the ground terminal;
A second constant current source having the other end connected to a second connection point; a fourth P-channel field effect transistor having a gate connected to the second connection point and a source connected to the power supply terminal; A second current mirror circuit comprising: a fifth P-channel field-effect transistor having a drain and a gate connected to the second connection point, and a source connected to the power supply terminal; and the fourth P-channel electric field. A drain and a gate are connected to a drain of the effect transistor, and a gate is connected to a drain of the second N-channel field effect transistor whose source is connected to the ground terminal, and a source is connected to the drain of the fourth P-channel field effect transistor A third N-channel field-effect transistor connected to the ground terminal and having a drain connected to the source of the first N-channel field-effect transistor Claim 2, characterized in that it is composed; third current mirror circuit consisting of
9. The PLL frequency synthesizer circuit according to 8. 30. The current correction means has a bias input terminal to which a bias voltage is supplied, and the current correction means is connected to the filter output terminal, the bias input terminal, and the first connection point, Rising current correction means for flowing the rising correction current from the first connection point to the ground terminal by bypassing the first constant current source based on the bias voltage in accordance with the control voltage; A terminal, the bias input terminal, and the second connection point. The second connection point is bypassed from the second connection point based on the bias voltage according to the control voltage. 30. The PLL frequency synthesizer circuit according to claim 29, further comprising: a descending current correction unit that supplies the descending correction current to a ground terminal. 31. The rising current correction unit applies a positive feedback correction to the control voltage to flow the rising correction current, and the falling current correction unit performs a negative feedback correction on the control voltage. The PLL frequency synthesizer circuit according to claim 30, wherein the falling correction current is applied to the PLL frequency synthesizer. 32. A first amplifier having an inverting input terminal connected to the bias input terminal and a non-inverting input terminal connected to the filter output terminal; A first NPN bipolar transistor having a base connected to the terminal and a collector connected to the first connection point; one end connected to the emitter of the first NPN bipolar transistor, and the other end connected to the ground terminal The first connected to
A second amplifier in which a non-inverting input terminal is connected to the bias input terminal, and an inverting input terminal is connected to the filter output terminal. A second NPN-type bipolar transistor having a base connected to the output terminal of the amplifier and a collector connected to the second connection point; one end connected to the emitter of the second NPN-type bipolar transistor; A second terminal connected to the ground terminal;
32. The PLL frequency synthesizer circuit according to claim 31, further comprising a resistor. 33. The current correction means having a bias input terminal to which a bias voltage is supplied and a lock input terminal to which a lock signal indicating one of an unlocked state and a locked state is supplied. Means are connected to the filter output terminal, the bias input terminal, the lock input terminal, and the first connection point, and when the lock signal indicates unlocking, correction control by the rise correction current. Is turned off, and when the lock signal indicates a lock state, the first connection point is bypassed from the first connection point based on the bias voltage according to the control voltage. A rising current correction means for flowing the rising correction current to a ground terminal, the filter output terminal, the bias input terminal, the lock input terminal, and the second connection point; When the lock signal indicates the unlocking time, the correction control by the descent correction current is turned off. 30. A descent current correction means for flowing the descent correction current from the second connection point to the ground terminal while bypassing the second constant current source. PLL frequency synthesizer circuit. 34. The rising current correction unit, wherein the rising current correction unit applies a positive feedback correction to the control voltage and flows the rising correction current when the lock signal indicates a lock state; 34. The PLL frequency synthesizer circuit according to claim 33, wherein, when the lock signal indicates a lock state, the control voltage is subjected to negative feedback correction and the falling correction current flows. 35. The lock signal is a signal which takes a logical L level when unlocked and a logical H level when locked, wherein the rising current correction means has an inverting input terminal connected to the bias input terminal, A first amplifier having a non-inverting input terminal connected to an output terminal, a sixth P-channel field effect transistor having a gate connected to the lock input terminal, and a source connected to the first connection point; A first NPN-type bipolar transistor having a base connected to the output terminal of the first amplifier and a collector connected to the drain of the sixth P-channel field-effect transistor; and an emitter connected to the first NPN-type bipolar transistor. A first end connected to one end and the other end connected to the ground terminal;
A second amplifier having a non-inverting input terminal connected to the bias input terminal and an inverting input terminal connected to the filter output terminal; and the lock input terminal. A seventh P-channel field effect transistor having a gate connected to the second node and a source connected to the second connection point; a base connected to an output terminal of the second amplifier; A second NPN bipolar transistor having a collector connected to the drain of the transistor; a second NPN bipolar transistor having one end connected to the emitter of the second NPN bipolar transistor and the other end connected to the ground terminal.
35. The PLL frequency synthesizer circuit according to claim 34, further comprising a resistor. 36. A mobile communication device using the PLL frequency synthesizer circuit according to any one of claims 28 to 35 as a local oscillator that oscillates the output signal as a local signal.