JP2000323704A - Field effect transistor - Google Patents

Abstract

(57) [Problem] To improve a gate breakdown voltage by suppressing an increase in a gate current. A 4 nm-thick I-layer is formed on an electron supply layer.
An intermediate layer 106a made of nAlP and a 1 nm-thick In
And an intermediate layer 106b made of P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor.

[0002]

2. Description of the Related Art Devices using compound semiconductors such as indium phosphide (InP) and gallium arsenide (GaAs) have characteristics of low power consumption and high speed as compared with silicon devices. Devices have been developed. Among them, various field-effect transistors using a compound semiconductor have been developed in order to obtain a faster circuit operation. Among them, a recess gate structure, which has an advantage that the source / drain resistance can be further reduced while a desired threshold value is secured, is widely used.

[0003] Regarding the recess gate structure, HEMT
(High Electron Mobility Transistor) will be described below as an example. The HEMT is a field effect transistor having a structure in which a region where electrons travel (a channel layer) and a region where electrons are supplied are spatially separated by a heterojunction. With this structure, scattering of electrons by donor impurities is reduced, electron mobility is increased, and high speed is improved.

[0004] To explain the structure, as shown in FIG. 12, first, a buffer layer 1202 made of InAlAs formed by crystal growth is arranged on a substrate 1201 made of InP. In addition, the buffer layer 1
On 202, a channel layer 1203 made of non-doped InGaAs is formed by crystal growth. An electron supply layer 12 made of InAlAs is formed thereon.
04 is formed therein, and a delta-doped layer 1205 into which an n-type impurity is introduced is formed therein.

The delta-doped layer 1205 is formed by introducing an n-type impurity at a desired position in the process of forming the electron supply layer 1204 by growing InAlAs on the channel layer 1203 by crystal growth. As described above, by making the region in which the impurity is introduced into the electron supply layer 1204 thinner and two-dimensional, even if the impurity is introduced into the whole of the electron supply layer 1204, the same threshold value is obtained. The gate leak can be further reduced, and the date breakdown voltage can be improved.

On the electron supply layer 1204, InP
An intermediate layer 1206 made of
a semiconductor layer 1207 made of lAs, a semiconductor layer 1208 made of InAlAs doped with n-type impurities, and a semiconductor layer 12 made of InGaAs doped with n-type impurities
09 is formed. On the semiconductor layer 1209, an ohmic junction is formed to form a source / drain electrode 1210.
Is formed.

As described above, in this HEMT, electrons supplied from the donor impurity added to the electron supply layer 1204 move to the channel layer 1203 and move to the channel layer 1203.
It accumulates at the junction interface between 204 and the channel layer 1203 to form a current channel. As a result of this physical phenomenon, electrons traveling through the channel are spatially separated from the donor impurity, which is the source, via a heterojunction. The thickness of the current channel formed in the channel layer 1203 is extremely thin, and there is no freedom of movement in the direction perpendicular to the bonding surface, which is substantially a two-dimensional electron channel (two-dimensional electron gas).

Then, the semiconductor layers 1207, 1208, 1
A groove is formed in 209 to expose the intermediate layer 1206, and a Schottky connection is made to the exposed surface to form a gate electrode 1211 to form a recess gate structure. Although the gate electrode 1211 is in Schottky junction with the intermediate layer 1206, the semiconductor layer 120
7, 1208, and 1209.

In this recess gate structure, first, an insulating layer 1212 having an opening is used as a mask, and a semiconductor layer 120 is formed.
7, 1208 and 1209 are selectively etched to form grooves. Then, the gate electrode 121 is provided in the groove.
1 may be arranged. Here, in the etching for forming the groove, a mixed aqueous solution of citric acid and hydrogen peroxide dissolving InGaAs or InAlAs is used as an etching solution. However, InP hardly dissolves in this etching solution. Therefore, the etching for forming the groove is
It stops automatically at the intermediate layer 1206 made of InP.

As described above, in a field effect transistor using a compound semiconductor, when a recess gate structure is used, an intermediate layer made of InP is used as an etching stopper layer. This intermediate layer is
If the film thickness is about 5 nm or more, the above-mentioned automatic stop function in wet etching can be exhibited. Generally, in the process of etching, it is difficult to make the etching amount uniform, and the etching amount tends to be non-uniform. However, as described above, by using the intermediate layer 1206 made of InP, the semiconductor layers 1207, 1208, and 120 can be formed without involving uneven etching.
The depth of the groove can be controlled by the thickness 9 formed.

[0011]

However, the conventional configuration described above has the following problems. Looking at the state of band gap energy in the film thickness direction in the HEMT having the above-described configuration, as shown by the solid line in FIG. 13, the electron barrier between the gate electrode 1211 and the two-dimensional electron gas becomes low. I have. Note that the horizontal axis in FIG. 13 indicates the distance from the gate electrode 1211 in the direction of the substrate 1201. As described above, when the intermediate layer made of InP is used, the gate current is increased and the gate withstand voltage is decreased due to a low electron barrier. The electron barrier is reduced because the Schottky barrier of InP constituting the intermediate layer 1206 is as low as 0.4V.

On the other hand, the InP and the lower electron supply layer 1
The difference of the conduction band between InAlAs and the
Ec) is 0.25 V, and the barrier is expected to be high inside the semiconductor constituting the element. However, it does not sufficiently function as a barrier due to the voltage drop inside the semiconductor. As described above, in the related art, there is a problem that the gate current increases and the gate breakdown voltage decreases, and the voltage application range of the field-effect transistor is limited, so that it is difficult to extract power.

By the way, as shown in FIG.
If the gate 206 is partially removed and the bottom of the gate electrode 1211a is brought into direct contact with the electron supply layer 1204, the barrier at that portion can be made higher. In this case, the state of the band gap energy is as shown by the dotted line in FIG. 13, and a high electron barrier is obtained between the gate electrode 1211 and the two-dimensional electron gas. This HEMT is almost the same as the HEMT shown in FIG.
The difference is that a Schottky barrier is formed between the electron supply layer 211a and the electron supply layer 1204. In this structure, after a groove is formed by selective etching using the insulating layer 1212 as a mask, the intermediate layer 1 is selectively formed by sputter etching having vertical anisotropy also using the insulating layer 1212 as a mask.
It can be formed by removing 206.

However, even with such a configuration,
The gate electrode 1211a is in contact with the intermediate layer 1206 on its side. Therefore, the horizontal gate electrode 1211a
In the path of the intermediate layer 1206-semiconductor layer 1207, FIG.
3 has a band gap structure as shown by the solid line, and is in a state where gate leakage is likely to occur. As described above, the configuration shown in FIG.
Since it is in contact with the intermediate layer 1206 made of nP and the Schottky barrier at this contact point is low, gate leakage is likely to occur as in the structure shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve a gate breakdown voltage by suppressing an increase in gate current in a field effect transistor having a recess gate structure. .

[0016]

A field effect transistor according to the present invention includes a channel layer formed on a semiconductor substrate,
A gate electrode formed on the channel layer, first and second semiconductor layers formed on the channel layer with the gate electrode interposed therebetween, and ohmic connection formed on the first and second semiconductor layers; And at least an intermediate layer made of a compound semiconductor composed of indium, aluminum and phosphorus disposed between the channel layer and the first and second semiconductor layers. . With this configuration, the electron barrier formed between the gate electrode and the surrounding semiconductor layer or channel layer is governed by the height of the barrier formed between the gate electrode and the intermediate layer. .

In the above configuration, the bottom surface of the gate electrode is formed by Schottky connection with the upper surface of the intermediate layer. Therefore, the electron barrier formed between the gate electrode and the surrounding semiconductor layer or channel layer is governed by the Schottky barrier formed between the gate electrode and the intermediate layer. In the above structure, a part of the gate electrode penetrates the intermediate layer, and the bottom surface is formed by Schottky connection with the upper surface of the semiconductor layer below the intermediate layer. With this configuration, the electron barrier formed between the gate electrode and the channel layer is governed by the Schottky barrier formed between the gate electrode and the channel layer, and the gate electrode and the surrounding Formed between the gate electrode and the intermediate layer is governed by the Schottky barrier formed between the gate electrode and the intermediate layer.

An electron supply layer into which an n-type impurity is introduced to form a heterojunction with the channel layer;
The intermediate layer was formed on the electron supply layer. With this configuration, this field-effect transistor is H
It becomes EMT (High Electron Mobility Transistor). Further, in the structure, a strain relaxation layer may be provided between the channel layer and the electron supply layer to reduce lattice mismatch between the substrate and the electron supply layer. Further, a semiconductor layer made of a group III-V compound semiconductor and covering the surface of the intermediate layer and having a thickness smaller than that of the intermediate layer may be provided, and a compound semiconductor composed of indium, aluminum and phosphorus having a smaller aluminum composition ratio than the intermediate layer. And a semiconductor layer thinner than the intermediate layer may be provided to cover the surface of the intermediate layer.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 First, a first embodiment of the present invention will be described. In the following, a description will be given taking HEMT as an example. FIG.
As shown in FIG. 1, the field effect transistor (HEMT) according to the first embodiment includes a substrate 101 made of InP.
A buffer layer 102 made of InAlAs and formed by crystal growth is disposed thereon. A channel layer 103 made of non-doped InGaAs is formed on the buffer layer 102 by crystal growth.

An electron supply layer 104 made of InAlAs is formed thereon, and a delta-doped layer 105 into which an n-type impurity is introduced is formed therein.
This delta-doped layer 105 has an I
In the process of forming the electron supply layer 104 by crystal-growing nAlAs, an n-type impurity is introduced at a desired location. As described above, by making the region in which the impurity is introduced into the electron supply layer 104 thinner and two-dimensional, compared with the case where the impurity is introduced into the entire electron supply layer 104, even if the threshold value is the same, The gate leak can be further reduced, and the date breakdown voltage can be improved.

In the first embodiment, an intermediate layer 106a made of InAlP having a thickness of 4 nm and an intermediate layer 106 made of InP having a thickness of 1 nm are formed on the electron supply layer 104.
b. The intermediate layer 106b is formed so as to cover the surface of the intermediate layer 106a. A semiconductor layer 107 made of InAlAs, a semiconductor layer 108 made of InAlAs into which an n-type impurity is introduced,
A semiconductor layer 109 made of InGaAs doped with an n-type impurity is formed. A source / drain electrode 110 is formed on the semiconductor layer 109 by ohmic contact.

A trench is formed in the semiconductor layers 107, 108 and 109 to expose the intermediate layer 106b, and a Schottky connection is made to the exposed surface to form a gate electrode 111, thereby forming a recess gate structure. This gate electrode 11
1 has a Schottky junction with the intermediate layers 106a and 106b, but on the side surface thereof,
08,109.

This recess gate structure is formed as follows. First, a groove is formed by selectively etching the semiconductor layers 107, 108, and 109 using the insulating layer 112 having an opening as a mask. Then, the gate electrode 111 may be arranged in the groove. Here, in the etching for forming the groove, a mixed aqueous solution of citric acid and hydrogen peroxide dissolving InGaAs or InAlAs is used as an etching solution. However, this etching solution contains I
nP and InAlP do not dissolve much. For this reason,
Etching for groove formation is automatically performed by InAlP or I
Stop at the intermediate layers 106a and 106b made of nP.

Here, from the results of experiments, it has been found that a film thickness of at least about 5 nm is required in order for the intermediate layer made of InP to exhibit the etching stop function. Therefore, the total thickness of the intermediate layers 106a and 106b is also 5n.
m or more. In the first embodiment,
As described below, the intermediate layer may be constituted by one layer of InAlP.
It has been found that AlP is easily oxidized and, if exposed to the surface, creates semiconductor defects.
To cover it thinly.

As described above, the intermediate layer for Schottky connection with the gate electrode 111 is made of InAlP and thin InP.
And made up of That is, the state of the band gap energy in the HEMT according to the first embodiment is as shown by the solid line in FIG. 2, and the electron barrier between the gate electrode 111 and the two-dimensional electron gas can be increased. Note that the two-dimensional electron gas is supplied to the electron supply layer 104.
Electrons accumulate at the junction interface between the semiconductor layer and the channel layer 103 to form a current channel. The horizontal axis of FIG. 2 indicates the distance from the gate electrode 111 in the direction of the substrate 101. Further, since the thickness of the intermediate layer 106b made of InP is reduced, according to the configuration of this embodiment,
Gate leakage in the horizontal direction is suppressed as compared with the conventional case.

For comparison, the band gap in the case of the conventional configuration shown in FIG. 12 is shown by a dotted line in FIG. 2, but the electron barrier is clearly higher in the first embodiment. Also, as is clear from FIG. 2, the thinner the intermediate layer 106b made of InP, the higher the electron barrier. Therefore, the intermediate layer 106b is eliminated and InAlP
If only the intermediate layer 106a made of is used, a state where the electron barrier is the highest can be obtained. However, as described above, since a compound semiconductor containing aluminum is easily oxidized, it is better to cover with an InP layer to prevent oxidation.

Here, looking at the element characteristics of the field effect transistor of the first embodiment, as shown in FIG. 3, an increase in current is suppressed. FIG. 3 is a block diagram of the H
The gate electrode of the EMT element has an anode electrode, the drain electrode has a cathode electrode, and the source electrode has a two-terminal characteristic in an open state. In FIG.
The solid line shows the case of the first embodiment, and the dotted line shows the conventional case. As is apparent from FIG. 3, the reverse current is 1
/ 1000. As shown in FIG. 4, the range on the vertical axis is linear, and the voltage on the horizontal axis is 10%.
When viewed in the doubled state, the gate breakdown voltage is improved several times. FIG. 4 also shows the case of the first embodiment by a solid line,
The dotted line shows the conventional case. The gate breakdown voltage is Ig
s is defined as the point where the constant current is -1 mA / mm.

The gate characteristics shown above are based on the HEM
As a three-terminal characteristic of T, as shown in FIG. 6, the voltage application area can be increased. 6A shows a conventional case, and FIG. 6B shows a case of the first embodiment. Since the power that can be extracted from the field-effect transistor (HEMT) is proportional to the product of the applied voltage and the output current, as is apparent from the comparison between the two, according to the first embodiment, while suppressing the fluctuation factors of the element characteristics, In addition, the output current that can be extracted can be improved.

In the above description, in order to protect the intermediate layer of InAlP as an etching stopper,
Although the case where a thin layer of P is used has been described, the present invention is not limited to this. An etching selectivity to InAlAs or InGaAs can be taken, and a stable material such as hardly oxidized may be used. As an intermediate layer for protecting the material, GaAs may be used.
Alternatively, GaP may be used. However, in the case of the above-described embodiment, since it is made of an InP-based material, it is better to use InP lattice-matched to this. In addition, as an intermediate layer for the protection, InAlP in which the composition ratio of Al is reduced to a level that is not so oxidized may be used. By having Al as a composition to some extent as compared with InP, a higher barrier height can be secured.

Embodiment 2 Next, a second embodiment of the present invention will be described.
In the second embodiment, as shown in FIG.
On a substrate 601 made of P, a buffer layer 602 made of InAlAs formed by crystal growth is arranged. A channel layer 603 made of non-doped InGaAs is formed on the buffer layer 602 by crystal growth. An electron supply layer 604 made of InAlAs is formed thereon, and a delta-doped layer 605 into which an n-type impurity is introduced is formed therein. This delta-doped layer 605 is
In the process of forming the electron supply layer 604 by crystal-growing InAlAs thereon, n-type impurities are formed at desired locations by introducing n-type impurities.

The electron supply layer 604 has a thickness of 4n.
m of an intermediate layer 606a made of InAlP and a thickness of 1 nm
And an intermediate layer 606b made of InP.
A semiconductor layer 60 made of InAlAs is further formed thereon.
7, a semiconductor layer 608 made of InAlAs doped with n-type impurities, InGaAs doped with n-type impurities
A semiconductor layer 609 is formed. Further, a source / drain electrode 610 is formed on the semiconductor layer 609 by ohmic junction.

In the second embodiment, grooves are formed in the semiconductor layers 607, 608, 609 and the intermediate layer 6
Grooves were also formed in 06a and 606b, the surface of the electron supply layer 604 was exposed, and a Schottky connection was made to the exposed surface to form a gate electrode 611, thereby forming a recess gate structure. The lower surface of the gate electrode 611 has the electron supply layer 6.
04, and the lower ends of the side surfaces are intermediate layers 606a and 606.
b, but on that other side,
The semiconductor layers 607, 608, and 609 are separated from each other.

In this recess gate structure, first, using the insulating layer 612 having an opening as a mask, the semiconductor layers 607, 6
A groove is formed by selectively etching 08 and 609. In this etching, InGaAs or InAlA
A mixed aqueous solution of citric acid and hydrogen peroxide that dissolves s is used as an etching solution. This etching solution contains In
P and InAlP do not dissolve much. Therefore, the etching for forming the groove automatically stops at the intermediate layers 606a and 606b made of InAlP or InP.

Next, the intermediate layers 606a and 606b are selectively removed by sputter etching having vertical anisotropy using the insulating layer 612 as a mask. Thereafter, a metal serving as a material of the gate electrode 611 is deposited by a sputtering method, and the deposited metal film is subjected to pattern processing.
Can be formed directly in contact with the gate electrode 611. Here, reverse sputtering is performed in an apparatus for forming a metal film by a sputtering method, so that the above-described intermediate layers 606a, 60
By selectively removing 6b, a metal film can be formed continuously.

As described above, in the second embodiment, since the gate electrode 611 is in a state of being in direct contact with the electron supply layer 604, the state of the band gap energy is as shown by the solid line in FIG. That is, according to the second embodiment, the electron barrier between the gate electrode 111 and the two-dimensional electron gas can be made higher than in the first embodiment. Further, in the second embodiment, the lower side surface of the gate electrode 611 is in contact with the intermediate layer 606b made of InP. However, since this is very thin as 1 nm, the lateral leakage is suppressed. I have.

Third Embodiment Next, a third embodiment of the present invention will be described.
In the third embodiment, as shown in FIG.
On a substrate 801 made of P, a buffer layer 802 made of InAlAs formed by crystal growth is arranged. On the buffer layer 802, a channel layer 803 made of non-doped InGaAs is formed by crystal growth. An electron supply layer 804 made of InAlAs is formed thereon, and a delta-doped layer 805 doped with an n-type impurity is formed therein. This delta-doped layer 805 is
In the process of forming the electron supply layer 804 by crystal growth of InAlAs thereon, an n-type impurity is introduced at a desired location to form the electron supply layer 804.

The electron supply layer 804 has a thickness of 4n.
m, an intermediate layer 806a made of InAlP,
And an intermediate layer 806b made of InP.
A semiconductor layer 80 of InAlAs is further formed thereon.
7, a semiconductor layer 808 made of InAlAs doped with an n-type impurity, InGaAs doped with an n-type impurity
Is formed. A source / drain electrode 810 is formed over the semiconductor layer 809 by ohmic contact.

In the third embodiment, grooves are formed in the semiconductor layers 807, 808, 809 and the intermediate layer 8 is formed.
A groove is also formed in the gate electrode 81b by exposing the surface of the intermediate layer 806a and making a Schottky connection to the exposed surface.
By forming No. 1, a recess gate structure was obtained. The lower surface of the gate electrode 811 contacts the intermediate layer 806a,
Although the lower end of the side surface is in contact with the intermediate layer 806b, the semiconductor layers 807, 808,
809.

In this recess gate structure, first, the semiconductor layers 807, 8
A groove is formed by selectively etching 08 and 809. In this etching, InGaAs or InAlA
A mixed aqueous solution of citric acid and hydrogen peroxide that dissolves s is used as an etching solution. This etching solution contains In
P and InAlP do not dissolve much. Therefore, the etching for forming the groove automatically stops at the intermediate layers 806a and 806b made of InAlP or InP.

Next, the intermediate layer 806b is selectively removed by sputter etching having vertical anisotropy using the insulating layer 812 as a mask. Thereafter, a metal serving as the material of the gate electrode 811 is deposited by a sputtering method, and the deposited metal film is patterned to form the gate electrode 811 in contact with the intermediate layer 806a. Here, if the above-described intermediate layer 806b is selectively removed by performing reverse sputtering in an apparatus for forming a metal film by a sputtering method,
Subsequently, a metal film can be formed.

As described above, in the third embodiment, since the gate electrode 811 is in contact with the intermediate layer 806a made of InAlP, the electron barrier between the gate electrode 811 and the two-dimensional electron gas is reduced. It can be higher than 2. This is because the Schottky barrier of InAlP is higher than that of InAlAs. Also in the third embodiment, the gate electrode 81
Although the lower side surface of 1 is in contact with the intermediate layer 806b made of InP, as in the second embodiment, since it is very thin, 1 nm, the lateral leakage is suppressed.

Embodiment 4 Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, FIG.
As shown in the figure, first, on a substrate 901 made of InP,
A buffer layer 902 made of InAlAs formed by crystal growth is provided. The buffer layer 9
On channel 02, a channel layer 903 made of non-doped InGaAs is formed by crystal growth.

On the channel layer 903, In
InAl via a spacer layer 903a made of AlAs
An electron supply layer 904 made of P is formed.
A delta-doped layer 905 into which an impurity of the shape is introduced is formed. This delta-doped layer 905 is
03a on the electron supply layer 904 by crystal growth of InAlP.
Is formed by introducing an n-type impurity at a desired position in the process of forming the.

Incidentally, the spacer layer 903a is provided for forming the electron supply layer 904 with high crystal quality. Since electrons flow through these layers, high crystal quality is required. In such a case, it is better to perform the crystal growth of InAlAs during that time, rather than suddenly switch from the crystal growth of InGaAs to the crystal growth of InAlP. Therefore, if the crystal quality can be maintained, the spacer layer 903a may not be provided.

The electron supply layer 904 has a film thickness of 1 n.
An intermediate layer 906 of about m of InP is provided. This intermediate layer 906 may be made of InAlAs in which the composition ratio of Al is smaller than that of the electron supply layer 904. By reducing the composition ratio of Al,
Oxidation can be suppressed. In addition, InA
A semiconductor layer 907 made of lAs, a semiconductor layer 908 made of InAlAs doped with an n-type impurity, and a semiconductor layer 909 made of InGaAs doped with an n-type impurity are formed. A source / drain electrode 910 is formed over the semiconductor layer 909 by ohmic junction.

In the fourth embodiment, grooves are formed in the semiconductor layers 907, 908, 909, and the intermediate layer 9 is formed.
06, an electron supply layer 9 made of InAlP.
The surface of the gate electrode 911 was formed by exposing the surface of the substrate 04 and making a Schottky connection to the exposed surface to form a recess gate structure. The lower surface of the gate electrode 911 is in contact with the electron supply layer 904 and the lower end of the side surface is in contact with the intermediate layer 906, but the other side surfaces are separated from the semiconductor layers 907, 908, and 909. are doing.

In this recess gate structure, first, using the insulating layer 912 having the opening as a mask, the semiconductor layers 907 and 9
08 and 909 are selectively etched to form grooves. In this etching, InGaAs or InAlA
A mixed aqueous solution of citric acid and hydrogen peroxide that dissolves s is used as an etching solution. This etching solution contains In
P and InAlP do not dissolve much. Therefore, the etching for forming the groove automatically stops at the intermediate layer 906 made of InP on the electron supply layer 904 made of InAlP. Further, as described above, since the electron supply layer 904 is made of InAlP, the electron supply layer 904 itself functions as an etching stopper.

Next, the intermediate layer 906b is selectively removed by sputter etching having vertical anisotropy using the insulating layer 912 as a mask. Thereafter, a metal serving as a material for the gate electrode 911 is deposited by a sputtering method, and the deposited metal film is patterned to form the gate electrode 911 in contact with the electron supply layer 904 made of InAlP. Here, in an apparatus for forming a metal film by a sputtering method,
If the above-described intermediate layer 906 is selectively removed by performing reverse sputtering, a metal film can be formed successively.

As described above, in the fourth embodiment, since the gate electrode 911 is in contact with the electron supply layer 904 made of InAlP, an electron barrier between the gate electrode 911 and the two-dimensional electron gas is formed. It can be higher than in Example 2. The Schottky barrier of InAlP is
This is because it is higher than the Schottky barrier of InAlAs. Further, also in the fourth embodiment, the lower side surface of the gate electrode 911 is in contact with the intermediate layer 906b made of InP. However, as in the second embodiment, since this is very thin, 1 nm, The leak is suppressed.

Fifth Embodiment Next, a fifth embodiment of the present invention will be described.
In the fifth embodiment, as shown in FIG.
A buffer layer 1002 made of InAlAs formed by crystal growth is arranged on a substrate 1001 made of nP. On the buffer layer 1002, a channel layer 1003 made of non-doped InGaAs is formed by crystal growth.

On the channel layer 1003, I
In via the spacer layer 1003a made of nAlAs
An electron supply layer 1004 made of AlP is formed, and a delta-doped layer 1005 into which an n-type impurity is introduced is formed.
Are formed. The delta-doped layer 1005 forms n at a desired position in the process of forming the electron supply layer 1004 by growing InAlP on the spacer layer 1003a.
It is formed by introducing a shape impurity.

By the way, the spacer layer 1003a
This is provided for forming the electron supply layer 1004 with high crystal quality. Since electrons flow through these layers, high crystal quality is required. In such a case, it is better to perform the crystal growth of InAlAs during that time, rather than suddenly switch from the crystal growth of InGaAs to the crystal growth of InAlP. Therefore, if the crystal quality can be maintained, the spacer layer 1003a may not be provided.

The electron supply layer 1004 has a thickness of 1
An intermediate layer 1006 made of InP of about nm is provided. Note that the intermediate layer 1006 may be made of InAlAs in which the composition ratio of Al is smaller than that of the electron supply layer 1004. Oxidation can be suppressed by reducing the composition ratio of Al. Also, on top of that,
A semiconductor layer 1007 made of InAlAs, a semiconductor layer 1008 made of InAlAs into which an n-type impurity is introduced,
A semiconductor layer 1009 made of InGaAs into which an n-type impurity has been introduced is formed. In addition, the semiconductor layer 1009
On top, an ohmic junction is formed to form a source / drain electrode 10.
10 are formed.

In the fifth embodiment, grooves are formed in the semiconductor layers 1007, 1008, and 1009 to form the intermediate layer 1
The surface 006 was exposed, and a Schottky connection was made to the exposed surface to form a gate electrode 1011 to form a recess gate structure. The lower surface of the gate electrode 1011 is in contact with the intermediate layer 1006, but is separated from the semiconductor layers 1007, 1008, and 1009 on other side surfaces. In this recess gate structure, first, an insulating layer 1012 having an opening is used as a mask and a semiconductor layer 1002 is formed.
7, 1008, 1009 are selectively etched to form grooves.

In this etching, InGaAs or InGaAs is used.
A mixed aqueous solution of citric acid and hydrogen peroxide that dissolves AlAs is used as an etching solution. InP and InAlP hardly dissolve in this etching solution. Therefore, the etching for forming the groove is performed by the intermediate layer 100 made of InP on the electron supply layer 1004 made of InAlP.
Stops automatically at 6. Thereafter, a metal serving as a material of the gate electrode 1011 is deposited by a sputtering method, and the deposited metal film is patterned to form the gate electrode 1011 in contact with the intermediate layer 1006.

As described above, in the fifth embodiment, the electron supply layer 1004 is made of InAlP, and the gate electrode 10 is formed on the intermediate layer 1006 made of InP formed thereon.
11 was in contact. And the intermediate layer 100
6 was formed as thin as 1 nm, for example. As a result, similarly to the first embodiment, the gate electrodes 1011 and 2
The electron barrier between the two-dimensional electron gas and the three-dimensional electron gas can be higher than before.

Embodiment 6 Next, a sixth embodiment of the present invention will be described.
In the sixth embodiment, as shown in FIG.
A buffer layer 1102 made of InAlAs formed by crystal growth is arranged on a substrate 1101 made of nP. A channel layer 1103 made of non-doped InGaAs is formed on the buffer layer 1102 by crystal growth.

On the channel layer 1103, I
In via a spacer layer 1103a made of nAlAs
An electron supply layer 1104 made of AlP is formed, and a delta doped layer 1105 into which an n-type impurity is introduced is formed therein.
Are formed. The delta-doped layer 1105 is formed at a desired position in the process of forming an electron supply layer 1104 by growing InAlP on the spacer layer 1103a.
It is formed by introducing a shape impurity.

Incidentally, the spacer layer 1103 a
This is provided for forming the electron supply layer 1104 with high crystal quality. Since electrons flow through these layers, high crystal quality is required. In such a case, it is better to perform the crystal growth of InAlAs during that time, rather than suddenly switch from the crystal growth of InGaAs to the crystal growth of InAlP. Therefore, if the crystal quality can be maintained,
The spacer layer 1103a may not be provided.

In addition, on the electron supply layer 1104, InA
through a strain relaxation layer 1104a of 1As,
An intermediate layer 1106 made of about m of InP was provided. By providing the strain relaxation layer 1104a, the strain of the electron supply layer 1104 made of InAlP having a different lattice spacing from the InP substrate is relaxed. Therefore,
The strain relieving layer 1104a is not limited to InAlAs, but may be made of a material that is instructor-matched to the InP substrate.

The intermediate layer 1106 may be made of InAlAs in which the composition ratio of Al is smaller than that of the electron supply layer 1104. By reducing the composition ratio of Al, the oxidation of the underlying layer of InAlAs can be suppressed. Further, a semiconductor layer 1107 made of InAlAs is further formed thereon, and InAl
A semiconductor layer 1108 made of As and a semiconductor layer 1109 made of InGaAs into which an n-type impurity is introduced are formed. A source / drain electrode 1110 is formed on the semiconductor layer 1109 by ohmic junction.

Also in the sixth embodiment, grooves are formed in the semiconductor layers 1107, 1108, and 1109 to form the intermediate layer 1
The surface of the gate electrode 1111 was formed by exposing the surface of the substrate 106 and making a Schottky connection to the exposed surface to form a recess gate structure. The gate electrode 1111 has a lower surface in contact with the intermediate layer 1106, but is separated from the semiconductor layers 1107, 1108, and 1109 on other side surfaces. In this recess gate structure, first, using the insulating layer 1112 provided with an opening as a mask, the semiconductor layer 110
7, 1108, 1109 are selectively etched to form grooves.

In this etching, InGaAs or InGaAs
A mixed aqueous solution of citric acid and hydrogen peroxide that dissolves AlAs is used as an etching solution. InP and InAlP hardly dissolve in this etching solution. Therefore, the etching for forming the groove is performed by the intermediate layer 110 made of InP on the electron supply layer 1104 made of InAlP.
Stops automatically at 6. Thereafter, a metal serving as a material of the gate electrode 1111 is deposited by a sputtering method, and the deposited metal film is patterned to form the gate electrode 1111 in contact with the intermediate layer 1106.

As described above, in the sixth embodiment, the electron supply layer 1104 is composed of InAlP, and the gate electrode 11 is formed on the intermediate layer 1106 composed of InP formed thereon.
11 was in contact. Then, the intermediate layer 110
6 was formed as thin as 1 nm, for example. As a result, similarly to the first embodiment, the gate electrodes 1111 and 2111
The electron barrier between the two-dimensional electron gas and the three-dimensional electron gas can be higher than before.

In the first to sixth embodiments, the HEMT has been described as an example of the recess gate structure. However, the present invention is not limited to this. For example, the present invention can be applied to another MESFET using a compound semiconductor that uses a recess gate structure.

[0066]

As described above, according to the present invention, a channel layer formed on a semiconductor substrate, a gate electrode formed on the channel layer, and a channel layer formed on the channel layer with the gate electrode interposed therebetween. Between the first and second semiconductor layers, the source and drain electrodes formed on the first and second semiconductor layers by ohmic connection, and between the channel layer and the first and second semiconductor layers. At least an intermediate layer made of a compound semiconductor composed of indium, aluminum, and phosphorus is arranged.
With this configuration, the electron barrier formed between the gate electrode and the surrounding semiconductor layer or channel layer is governed by the height of the barrier formed between the gate electrode and the intermediate layer. . Since this barrier height is almost equal to the Schottky barrier in the compound semiconductor composed of indium, aluminum and phosphorus, a high potential barrier can be obtained. Therefore, according to the present invention, there is an excellent effect that the increase in the gate current can be suppressed and the gate breakdown voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a field effect transistor (HEMT) according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a state of band gap energy of the HEMT of FIG. 1;

FIG. 3 is an explanatory diagram illustrating element characteristics of the field-effect transistor according to the first embodiment;

FIG. 4 is an explanatory diagram showing element characteristics of the field-effect transistor according to the first embodiment.

FIGS. 5A and 5B are an explanatory diagram illustrating device characteristics of a conventional field-effect transistor and an explanatory diagram illustrating device characteristics of the field-effect transistor according to the first embodiment.

FIG. 6 is a configuration diagram illustrating a configuration of a field effect transistor (HEMT) according to a second embodiment of the present invention.

FIG. 7 is an explanatory view showing a state of band gap energy of the HEMT of FIG. 6;

FIG. 8 is a configuration diagram showing a configuration of a field effect transistor (HEMT) according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram showing a configuration of a field effect transistor (HEMT) according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a configuration of a field effect transistor (HEMT) according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram showing a configuration of a field effect transistor (HEMT) according to a sixth embodiment of the present invention.

FIG. 12 shows a conventional field effect transistor (HE)
FIG. 3 is a configuration diagram illustrating a configuration of the MT).

13 is an explanatory diagram showing a state of band gap energy of the HEMT of FIG.

FIG. 14 shows a conventional field effect transistor (HE)
FIG. 14 is a configuration diagram showing another configuration of the MT).

[Explanation of symbols]

101: substrate, 102: buffer layer, 103: channel layer, 104: electron supply layer, 105: delta doped layer, 1
06a, 106b ... middle layer, 107, 108, 109 ...
Semiconductor layer, 110: source / drain electrode, 111: gate electrode, 112: insulating layer.

Continued on the front page (72) Inventor Takashi Makimura 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yasunobu Ishii 3- 19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Telephone Co., Ltd. (72) Inventor Takashi Kobayashi 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation F-term (reference) 5F102 FA01 GB01 GC01 GD01 GJ06 GK04 GL04 GM04 GN04 GQ01 GR04 GR10 GS04 GV05 HC01 HC04 HC15 HC16

Claims (7)

[Claims] 1. A channel layer formed on a semiconductor substrate, a gate electrode formed on the channel layer, and first and second semiconductor layers formed on the channel layer with the gate electrode interposed therebetween. A source electrode and a drain electrode formed on the first and second semiconductor layers by ohmic connection; and indium and aluminum disposed between the channel layer and the first and second semiconductor layers. A field effect transistor comprising at least an intermediate layer made of a compound semiconductor composed of: 2. The field effect transistor according to claim 1, wherein a bottom surface of said gate electrode is formed by Schottky connection with an upper surface of said intermediate layer. 3. The field-effect transistor according to claim 1, wherein the gate electrode is partially formed through the intermediate layer, and a bottom surface thereof is formed by Schottky connection with an upper surface of a semiconductor layer below the intermediate layer. A field effect transistor characterized by the above-mentioned. 4. The field-effect transistor according to claim 1, further comprising: an electron supply layer in which an n-type impurity is introduced on the channel layer to make a heterojunction with the channel layer. A field effect transistor, wherein the intermediate layer is formed on the electron supply layer. 5. The field effect transistor according to claim 4, further comprising: a strain relaxation layer between the channel layer and the electron supply layer, for relaxing lattice mismatch between the substrate and the electron supply layer. A field-effect transistor provided for: 6. The field effect transistor according to claim 1, further comprising a semiconductor layer made of a group III-V compound semiconductor, covering the surface of the intermediate layer and thinner than the intermediate layer. A field-effect transistor characterized by the above-mentioned. 7. The field-effect transistor according to claim 1, wherein the intermediate layer is made of a compound semiconductor composed of indium, aluminum, and phosphorus having a lower aluminum composition ratio than the intermediate layer. A field-effect transistor further comprising a semiconductor layer covering the surface and thinner than the intermediate layer.