JP2000322898A - Semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor integrated circuit device having a memory test function capable of performing a memory circuit test operation while performing a defect relief by a redundant circuit with a simple configuration. SOLUTION: In a memory test circuit mounted on the same semiconductor integrated circuit device as a memory circuit, a register holding the same number of addresses as the redundant circuit is provided, and when a failure is detected, the address is stored in the register, and the defective address is stored. Ignore the fail output by excluding from the test scan target, etc., ignore the fail output, and if the test scan is completed when the number of fail detections is within the number of redundant circuits, rescue is possible. Disabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, for example, a memory test circuit in a semiconductor integrated circuit device such as a system LSI having a memory circuit such as a dynamic RAM (random access memory) mounted thereon. It relates to technology that is effective to use.

[0002]

2. Description of the Related Art A test of a memory circuit such as a dynamic RAM is roughly performed as follows. When the memory circuit is completed on the semiconductor wafer, a probing test is performed by electrically connecting the memory tester and the memory circuit with a probe, and the fail information obtained there is stored in the fail memory in the memory tester. Store. Next, the fail memory is scanned by a program in the memory tester, and a relief judgment is performed by the mounted redundant circuit. In other words, it is determined by scanning the above-mentioned fail memory how the limited number of redundant circuits can be used most efficiently to repair a defect, and the rescuable chip and the rescue data (defective address) are sent to the laser cutting device. The laser beam is conveyed, and the fuse as a program element is cut by the laser cutting device to switch a defective address to a redundant circuit.

[0003]

With the development of semiconductor technology, large-scale integrated circuits are moving toward a technique of combining large-scale macros (cores) in the same manner as the design of a printed circuit board for combining components. Memory is indispensable in digital signal processing.
AM has a feature that a large storage capacity can be obtained, and thus plays an important role in the large-scale integrated circuit as described above. When a memory circuit is mounted on such a large-scale semiconductor integrated circuit, when the memory circuit is directly operated from the outside using the memory tester as described above, a test signal transmission path between a test and an original operation is performed. Since the operating conditions such as the difference between the two are greatly different, a highly reliable test cannot be performed. In addition, since the function of the integrated circuit is tested by a tester corresponding to a plurality of macros, an increase in test cost is a problem.

Therefore, by mounting the memory test circuit, the memory circuit can be read / written under the same conditions at the time of the original operation, so that a highly reliable test result can be obtained and the number of memory testers can be reduced. However, if a memory test circuit having the same function as the memory tester as described above is provided while providing a redundancy circuit and performing defect repair using the redundancy circuit, a fail memory having the same storage capacity as the memory circuit is provided. Is required, and the memory test circuit used only at the time of the test becomes enormous more than the circuit scale of the memory circuit to be tested, which is not practical.

Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device having a memory test function capable of performing a test operation of a memory circuit while performing a defect remedy by a redundant circuit with a simple configuration. Other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

Means for Solving the Problems In the present application, an outline of a representative one of the disclosed inventions will be briefly described as follows. That is, the redundant circuit provided in the memory circuit is limited to the X system and the Y system.
Focusing on the fact that all combinations to be rescued are determined by repeating the number of mounted redundant circuits, a memory test circuit mounted on the same semiconductor integrated circuit device as the memory circuit has a register holding the same number of addresses as the redundant circuit. When a failure is detected, the address is stored in a register, and the failure output is ignored by excluding such a defective address from the target of the test scan, and the failure can be remedied when the test scan is completed within the number of redundant circuits. If the number of fail detections is equal to or greater than the number of redundant circuits in all of the above combinations, it cannot be repaired.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a basic flowchart for explaining a method for testing a built-in memory circuit in a semiconductor integrated circuit device according to the present invention. In this embodiment, it is possible to judge good / defective while performing defect repair using a redundant circuit (spare word line, spare bit line) without using a fail memory as in the memory tester. It is devised.

In step (1), a relief pattern is set. The setting of the repair pattern means the order of use of the redundant circuit, and for example, as shown in FIG. 2A, two sets of X and Y systems (X1, X2 and Y1, Y2 ) For memories with redundant circuits,
As shown in the explanatory diagram of FIG. 7B, one of six relief patterns 0 to 5 in total is set. Incidentally, it is determined that pattern 0 uses redundant circuits in the order of Y1, Y2, X1, and X2.

The redundancy circuit provided in the memory circuit is limited to the X-system and the Y-system, and there are two combinations for relieving a certain failure, the X-system or the Y-system. All combinations are determined.
When there are two redundant circuits X1, X2, Y1 and Y2 as described above, the combination of the order is shown in FIG.
As shown in the explanatory diagram of FIG.

In step (2), a scan is performed. That is, a write operation is performed on the memory. In this case, a memory cell is selected by a known test pattern such as a checker pattern and a gallop pattern in consideration of the influence of coupling between an adjacent word line and an adjacent bit line, and data is written into the memory cell.

In step (3), the write data is read out and compared with an expected value to detect a failure (defective). Here, if one defect does not exist, the end of the scan is determined in step (7), and the determination of a perfectly good product is output.

In the step (4), the step (3)
When a further failure is detected, it is determined whether masking is possible. That is, it is determined whether or not such a defect can be remedied by the previously used redundant circuit. If the defect can be remedied, the process proceeds to step (7).

In the step (5), the step (4)
When it is determined that masking is impossible, it is determined whether such a failure can be remedied. That is, it is determined whether or not there is an unused redundant circuit. If there is an unused redundant circuit, the fail data is stored in step (8). Specifically, the defective address is stored in a register corresponding to the redundant circuit. The defective address stored in this register is used as information on whether or not masking is possible in step (4).

When the data is stored in step (8), it is determined in step (7) whether or not the scan is completed. If there is an unscanned memory cell, the process returns to step (2) and the scan is completed. If it is, a non-defective product is determined, and fail data between the defective address at that time and the redundant circuit to be used is output. Based on the fail data, a defective address is stored in the redundant circuit by the above-described laser cutting device or the like, and the defective is remedied.

In the step (6), the step (5)
When it is determined that the rescue is impossible, it is determined whether the entire rescue pattern has been executed. If there are remaining patterns, the process returns to step (1) to change the rescue pattern. Memory cells exist, and a defective product is determined.

The determination as to whether masking is possible in step (4) can be omitted if the scan direction and the used redundant circuit match. For example, when a memory cell is scanned by selecting a word line and sequentially switching bit lines, a failure is determined in one of the memory cells connected to the word line, and when replacing it with a spare word line, Alternatively, the word line may be excluded from the scan target, and subsequent bit line selection may be omitted to switch to the next word line selection operation.

In this embodiment, if the function of skipping the word line selection operation at an arbitrary address is added as described above, the memory scan circuit and the sequence control become correspondingly complicated. The same effect can be obtained irrespective of scan addressing only by adding a simple gate function of masking the fail detection output in step (3) in step (4).

In FIG. 2, when the defect indicated by the mark X exists in the memory circuit, the repair pattern is 0-5.
However, if scanning is sequentially started from the above-described rescue pattern 0 and all the fail patterns are rescued by the pattern 1 and the pass is OK, it is meaningless to verify the remaining patterns 2 to 5. The test ends when the non-defective product is accepted. Therefore, FIG.
As described above, the rescue determination results of the remaining patterns 2 to 5 are theoretical, and differ from the results of actual scanning according to the test method shown in the flowchart of FIG.

FIG. 3 is an explanatory diagram for explaining one of the repair patterns of the test method of the built-in memory circuit in the semiconductor integrated circuit device according to the present invention. The figure shows an example in which all the failures of the memory circuit are relieved in the order of use of X1, X2, Y1, and Y2.
When the first fail indicated by x in black is detected by the start of scanning, the same address x1 as the above-mentioned fail is to be rescued by the X-system redundant circuit 1, and the other fail existing there is also rescued. That is, the other fail on the x1 address is determined to be maskable. Subsequent scans again indicated by black x 2
When the third failure is detected, the X-system redundant circuit 2
The address x2 which is the same as the above fail is a target of relief,
Other failures there will also be rescued.

When the third fail indicated by black x is detected again by the subsequent scan, the same address y1 as the above-mentioned fail is to be relieved by the Y-system redundant circuit 1, but in FIG. Does not exist. When the fourth fail indicated by black x is detected again by the subsequent scan, the same address y2 as the above-mentioned fail is to be rescued by the Y-system redundant circuit 2, and the other fail existing there is also rescued. . As a result, a total of 4
It is determined that relief of all failures is possible by one redundant circuit, and a non-defective OK is determined.

FIG. 4 is an explanatory diagram for explaining another relief pattern for a method of testing a built-in memory circuit in a semiconductor integrated circuit device according to the present invention. This figure shows an example in which, in a memory circuit having the same fail bit, not all the failures of the memory circuit are repaired when the order of use is Y1, Y2, X1, and X2. When the first fail indicated by black x is detected at the start of scanning, the same address y1 as the above-mentioned fail is to be rescued by the Y-system redundant circuit 1, but there is no other fail in FIG. When a second fail indicated by black x is detected again by the subsequent scan, the same address y2 as the above-mentioned fail is to be rescued by the Y-related redundant circuit 2, but there is no other fail in FIG. .

When the third failure indicated by black x is detected again by the subsequent scanning, the same address x1 as the above-mentioned failure is to be rescued by the X-system redundancy circuit 1, but other failures are shown in FIG. Does not exist. When the fourth failure indicated by black x is detected again by the subsequent scan, the same address x2 as the above-mentioned failure is to be rescued by the X-system redundant circuit 2, and the other fail existing there is also rescued. . As a result, even if four redundant circuits are used, as many as three fail memory cells still remain, so that it is determined that the scan is defective at the end of the scan.

FIG. 5 is a block diagram showing one embodiment of the memory test circuit mounted on the semiconductor integrated circuit device according to the present invention. Memory test circuit m of this embodiment
The BIST is not particularly limited, but is an interface JTAG for a test circuit built in an LSI (Large Scale Integrated Circuit).
MBIST corresponding to (IEEE1149.1 standard)
/ JTAG interface circuit, a register, a pattern memory, a computing unit, an output control circuit, an error check / rescue determination circuit, and a sequencer.

The test signal input serially through the JTAG is stored in the pattern memory through the mBIST / JTAG interface circuit. The expected value corresponding to the test signal is transmitted to an error check / rescue determination circuit. The arithmetic unit generates an address signal and write data using the test signal stored in the register and the pattern memory, controls an output circuit, and simultaneously performs a write operation on a plurality of memory circuits 1 to n. The read operation is performed.

The data read from the memory circuits 1 to n are transmitted to the corresponding error check / rescue determination circuits, and a good / bad error check is performed by comparing the data with the expected value. The error check / rescue determination circuit includes a fail register as described later. If it is determined from the result of the error check that rescue is possible in step (5) in FIG. And other fail data.

The rescue judging function of the error check rescue judging circuit basically performs a test operation according to the flowchart shown in FIG. As in this embodiment, when a plurality of memory circuits 1 to n are simultaneously subjected to a test operation in parallel, if the memory circuit 1 is determined to be non-defective according to the repair pattern of FIG. Is not required. However, other memory circuits 2
If the relief is not performed at n, the relief pattern is changed and the above-described scanning operation is continuously performed. At this time,
The operation of the error check / judgment circuit of the memory circuit 1 is stopped, and the fail data of the rescue pattern determined to be non-defective is stored as in the rescue pattern of FIG.

FIG. 6 is a block diagram showing one embodiment of the memory circuit. The DRAM module in this embodiment is constituted by 512 Kbits / bank, and
This module can be added and expanded up to 6 banks (2 to 8 Mbits). This remedy method for a DRAM module involves simultaneous switching of all banks in the module, and has two sets of redundant lines for each of X and Y systems. The memory configuration has a storage capacity of 512K bits of 2048 word lines × 256 bits per bank, and a maximum of 8 Mbits storage capacity as described above by mounting 16 at a maximum.

The X redundancy has 128 redundant lines and has two sets. Then, the four word lines are collectively switched to the redundant word lines. That is, if there is a memory cell connected to any one of the word lines in units of four, the four word lines including the memory cell are collectively switched to the redundant word line. If any one of the 16 banks is defective, the remaining 15 banks are simultaneously switched to redundant word lines. The Y redundancy has 16 redundant lines and has 2 sets. Then, 8 bits are simultaneously switched to the redundant bit line. Of the maximum 16 banks,
If any one of the banks has a defect, the remaining 15 banks are simultaneously switched to redundant bit lines.

Therefore, the relief address space, that is,
As for the X address of the redundant circuit, a redundant circuit including a word line of 0 to 255 and a bit line of 0 to 63 is provided for a 4096 × 2048 = 8 Mbit module, and is reduced as described above. It is a relief address space.

FIG. 7 is a block diagram showing an embodiment of the error check / rescue determination circuit shown in FIG. 5. The circuit block is divided for each function of the rescue determination algorithm as described above. I have. The error check / rescue determination circuit is roughly composed of a determiner, a pass / fail detector, and a fail register.

The pass / fail detector includes an error check circuit for comparing data and addresses, and a fail mask circuit for excluding addresses in the fail register from being subjected to the error check. The pass / fail detector is
FIG. 8 shows a detailed block diagram thereof. This block performs fail detection by comparing the expected value with output data from the memory circuit DRAM, and performs fail mask processing by comparing data in a fail register with an error.

When a failure is detected, writing to the fail register is selectively performed in accordance with an output of a test machine described later to store the failure. That is,
When a failure is detected by the error check circuit,
Through a fail mask circuit, a redundancy circuit to be used corresponding to the repair pattern for repairing the defect is selected, and the fail register is selected. The memory access address (defective address) is output as fail data to the selected fail register via the error check circuit.

The fail mask circuit receives the output of the fail register and the output of the determiner, and the detected fail result selects the output of the fail register in accordance with the output of the determiner corresponding to the relief pattern at that time.
If the redundancy circuit corresponding to the register can repair the error, the error detection output from the error check circuit is masked, and the output signals of the fail register control and the decision unit control are stopped. The judgment result and the rescue data stored in the fail register are output to the outside of the semiconductor integrated circuit device via the mBIST / JTAG interface circuit and the input / output circuit JTAG when the test operation is completed, and the defect remedy is output. Used for

FIG. 9 is a block diagram of the fail register section. In the fail register section,
A plurality of fail registers corresponding to the redundant circuit are provided. These fail registers are selected by a fail register control signal, and fail data is written to the selected fail register. The information stored in the selected fail register is supplied to the fail mask circuit as a fail register output.
Further, the determination result flag included in the storage information and the rescue data (defective address) are output to the outside. Using this rescue data, defect rescue is performed by a laser cutting device or the like.

The configuration of the relief data stored in the fail register is not particularly limited, but is composed of 33 bits 0 to 32. Of these, the 6 bits 0-5 are
A row (X-system) redundant line address 1 is indicated, and 6 bits 6 to 11 indicate a row (X-system) redundant line address 2. 12 ~
Nineteen bits indicate a column (Y-system) redundant line address 1, and eight bits 20 to 27 indicate a column (Y-system) redundant line address 2. And the 4 bits 28 to 31 are
This flag indicates an effective redundant line, and indicates whether or not the addresses of the four redundant lines are valid. Then, one bit (32) of the 33rd bit is used as a flag indicating whether repair is possible.

FIG. 10 is a block diagram showing an embodiment of the decision unit shown in FIG. In the rescue determination algorithm of this embodiment, each state is generated by a state machine configured in a determiner. The determiner includes two types of state machines 1 and 2 and one error counter. The state machine 1 has a function of determining a relief, and the state machine 2 has a function of generating a relief pattern. The error counter determines a fail pattern that cannot be remedied,
It has a function to end the rescue judgment test.

FIG. 11 is a state transition diagram for explaining a part of the operation of the decision unit. FIG. 2 is a state transition diagram corresponding to the state machine 1. This state machine 1 has ten states indicated by 〇 in FIG. The scan pattern set state (ini) is shown in FIG.
In this case, one of the six rescue patterns as shown in (1) is set, and a rescue determination is performed using the redundant circuit X1 or Y1 used first in correspondence with the rescue pattern. Each time a defect occurs in the middle of the scan, the redundant circuit is switched according to the order of use of the repair pattern.

When all four redundant circuits are used, a final state (final) occurs. This final state means that there is no remaining redundant line. The state shifts from the final state to the cancel state (cancel), and the set relief pattern is canceled. Then, after changing to the change state (change) 1 and changing the rescue pattern, the restarter (restart) instructs the sequencer of FIG. 5 to restart scanning using the changed rescue pattern. , The same scan and rescue determination as described above are performed. When all the scans are completed except for the redundant circuit, the state shifts to a change state (change) 2. Change state 2
Means that rescue is possible, and the state machine 2
To go to the good state (good).

FIG. 12 is a state transition diagram for explaining the rest of the operation of the decision unit. Figure (A)
Corresponds to the state machine 2, (B) corresponds to an error counter, and (C) indicates each state of the error counter.

In FIG. 12A, this state machine 2 has nine states indicated by 〇 in FIG. Patterns (pat) 0 to 5 determine the order of use of the redundant circuits as described above. For example, pattern 0 is Y1 → Y2 →
X1 → X2, and pattern 1 is X1 → X2 → Y1 → Y
2, pattern 2 is X1 → Y1 → X2 → Y2, pattern 3 is X1 → Y1 → Y2 → X2, pattern 4 is Y1 → X1 → Y2 → X2, and pattern 5 is Y1 → X1 → X2 → Y2. The rescue pattern is instructed to shift according to the check state 1 of the state machine 1, and if a failure is detected even after the completion of the above six rescue patterns, it corresponds to the defective item determination in step (9) in FIG. It becomes a failed state, and outputs a message that repair is impossible. In any of the rescue patterns, the scan is completed, the state becomes a good (good) state corresponding to the non-defective item determination in step (10) of FIG.

In FIG. 12 (B), each state of the error counter comprises four states. As shown in FIG. 12 (C), an error (error) 0 indicates that an error which cannot be remedied is 0. Error (error) 1 means that there is one error that can be irreparable, error (erro
r) 2 indicates that there are two errors that can not be remedied, and error (error) 3 indicates that the error cannot be remedied. The state of error 3 has a function of instructing the state machine 2 to transition to a fail state.

In the test mode, the DRAM module
The detection of coincidence / mismatch of 8-bit data is performed by one access. The judgment items can be classified according to the number of fail bits detected in one match / mismatch detection. In the DRAM module of this embodiment, since the number of redundant circuits (redundant lines) of the column (Y) system is two, a failure having three or more fail bits is instructed to the error counter as an error that cannot be repaired. And
When three detections are made, the state machine 2 is instructed to transition to a fail state corresponding to the defective product determination in step (9) in FIG.

FIG. 13 is a schematic block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the relief judgment circuit is mounted in a memory circuit. A self-rescue circuit is formed in the memory circuit by the rescue determination circuit and the electric fuse circuit. In this embodiment, after the rescue judgment test is completed, the rescue data is written by applying a PROM (programmable ROM) write power. When the semiconductor integrated circuit device starts up, the PROM data is
The switch matrix is controlled, and the external address of the memory is converted to the internal address to achieve the relief. This embodiment is realized by combining the above-described relief determination circuit and an anti-fuse circuit formed of a PROM. The self-rescue circuit can significantly improve a memory test process because a defect can be rescued without a defect rescue device.

FIG. 14 is an overall block diagram of one embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device including a logic unit for performing digital signal processing, an analog unit for performing analog signal processing, and a memory circuit RAM used for the digital signal processing. The following circuits are added.

The memory test circuit mBIST tests the memory circuit RAM as described above. For testing the logic section, a test signal is input to the logic test circuit BIST and the flip-flops of the logic section, and a boundary scan cell section for outputting the state of the flip-flop is provided. A test input / output circuit JT for inputting / outputting a test signal from an external terminal and input / output of a judgment output, etc. to these built-in test circuits.
An AG is provided.

The test input / output circuit has a total of five external terminals. TDO is a test data output terminal, TDI is a test data input terminal, TMS is a test mode setting terminal, TRSTN is a terminal for instructing reset of the test circuit, and TCK is an input of each of the above signals. Or, a test clock terminal used for output. The test input / output circuit JTAG outputs an output signal such as a test input signal necessary for the operation of the built-in test circuit and an output signal such as a test result in synchronization with the clock signal TCK through five terminals as described above. This is to input or output serially.

The flowchart of the remedy determination shown in FIG. 1 is useful even if it is installed as a program in a conventional memory tester. In the case where the memory is mounted as a program in the memory tester, a test circuit is not required in the semiconductor integrated circuit as in the above-described embodiment. The memory tester scans a memory circuit to be tested and determines whether data matches with an expected value. With this configuration, a high-speed test equivalent to that when the test circuit is built-in cannot be performed as in the above-described embodiment, but there is an advantage that a fail memory is not required in the memory tester, and the scale of the test apparatus can be significantly reduced. For this reason, by mounting a program for realizing the relief determination flowchart shown in FIG. 1 in a simple test system, a memory circuit formed in a semiconductor integrated circuit device can be tested.

The functions and effects obtained from the above embodiment are as follows. That is, (1) As a test circuit built in a semiconductor integrated circuit device including a logic circuit and a memory circuit including a plurality of redundant circuits composed of an X system and a Y system, a failure corresponding to an error determination output is stored in a register. If the error can be remedied by using the redundant circuit corresponding to the stored defective address, the error determination output is ignored, and a defective address does not exist in the register or a defect corresponding to the error determination output is stored in the register. If the redundancy circuit corresponding to the defective address cannot remedy the error, the error determination output is output and the error determination output is determined by a state machine and an error counter. A test signal is generated, and the state output of the state machine and the error counter are output to the redundant circuit. When the number is equal to or less than the number, the test result is output and the test operation is terminated, and when the state output exceeds the number of the redundant circuits, the register and the error counter are reset, the combination of the use order is changed, and the The determination of the output of the test signal and the error count output thereof is performed, and the state output exceeds the number of the redundant circuits even in the combination of the last use order of the plurality of redundant circuits including the X system and the Y system. In this case, by outputting a failure output that cannot be remedied, it is possible to obtain an effect that the test operation of the memory circuit can be realized while the defect is remedied by the redundant circuit with a simple configuration without using a fail memory.

(2) The memory circuit is constituted by a plurality of memory circuits corresponding to a plurality of memory banks, and a test signal is simultaneously supplied to the plurality of memory banks in parallel by the memory test circuit. Providing the circuits in one-to-one correspondence with the individual memory banks has an effect that the test time can be reduced or the efficiency can be improved.

(3) By providing an interface circuit for serially performing an operation of inputting a test pattern and its expected value to the memory test circuit and a determination output operation including an unrepairable failure output, the test can be performed with a small number of terminals. The effect that the operation can be performed is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, an operation sequence for determining whether or not a failure detected by use of the redundant circuit using the mounted redundant circuit can be remedied can employ various embodiments. The memory circuit may have a configuration using a static memory cell in addition to the above-described dynamic memory cell, or may use a cell such as a nonvolatile memory. The present invention can be widely used for a semiconductor integrated circuit device having a built-in memory circuit.

[0052]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, as a test circuit built in a semiconductor integrated circuit device including a logic circuit and a memory circuit including a plurality of redundant circuits including X and Y systems, a failure corresponding to an error determination output is stored in a register. If the error can be remedied by using the redundant circuit corresponding to the defective address, the error determination output is ignored, and the defective address does not exist in the register or the defect corresponding to the error determination output is stored in the defective address stored in the register. If the corresponding redundant circuit cannot remedy the error, the error determination output is output, the error determination output is determined by a state machine and an error counter, and a test signal is output in accordance with the order of use of a plurality of redundant circuits including an X system and a Y system. And the state output of the state counter and error counter is less than the number of the redundant circuits. Sometimes, such a determination result is output to terminate the test operation, and when the status output exceeds the number of the redundant circuits, the register and the error counter are reset to change the combination of the use order and the test signal again. And the error count output thereof, the above-described determination is performed. Even in the last combination of the use order of the plurality of redundant circuits including the X-system and the Y-system, when the status output exceeds the number of the redundant circuits, remedy is performed. By outputting an unsuccessful failure output, a test operation of the memory circuit can be realized with a simple configuration without using a fail memory, while performing the failure repair by the redundant circuit.

[Brief description of the drawings]

FIG. 1 is a basic flowchart for explaining a test method of a built-in memory circuit in a semiconductor integrated circuit device according to the present invention.

FIG. 2 is an explanatory diagram of a test method of a built-in memory circuit of FIG. 1;

FIG. 3 is an explanatory diagram of one relief pattern in the test method of the built-in memory circuit of FIG. 1;

FIG. 4 is an explanatory diagram of another repair pattern of the test method of the built-in memory circuit of FIG. 1;

FIG. 5 is a block diagram showing one embodiment of a memory test circuit mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a configuration diagram showing one embodiment of a memory circuit mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a block diagram showing one embodiment of the error check / rescue determination circuit of FIG. 5;

FIG. 8 is a detailed block diagram showing one embodiment of the pass / fail detector of FIG. 7;

FIG. 9 is a detailed block diagram illustrating one embodiment of the fail register of FIG. 7;

FIG. 10 is a detailed block diagram showing one embodiment of a determiner of FIG. 7;

FIG. 11 is a state transition diagram for explaining an operation of a part of the determiner in FIG. 10;

FIG. 12 is a state transition diagram for explaining the remaining operation of the determiner in FIG. 10;

FIG. 13 is a schematic block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 14 is an overall block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

X1, X2 ... X system redundant circuit, Y1, Y2 ... Y system redundant circuit, mBIST ... Built-in memory test circuit, RAM ... Memory circuit, JTAG ... Test input / output circuit.

Continued on front page F-term (reference)

Claims (3)

[Claims] 1. A memory circuit comprising: a logic circuit; a memory circuit including a plurality of redundant circuits of X and Y systems; and a memory test circuit for testing the memory circuit. The memory test circuit is included in the memory circuit A register corresponding to the plurality of redundant circuits composed of the X system and the Y system; a test signal generating circuit for supplying a test signal to the memory circuit; data corresponding to the test signal from the memory circuit; A judgment circuit for judging an error by comparing with an expected value and comparing a defective address corresponding to the error with data stored in the register to judge rescue; and a test signal generation circuit based on a judgment result from the judgment circuit. And a control circuit for controlling a failure. The determination circuit is configured to determine whether a failure corresponding to the error determination output corresponds to a failure address stored in the register. If the error determination output can be remedied by use of the redundant circuit, the error determination output is ignored, and if the defective address does not exist in the register, or the defect corresponding to the error determination output corresponds to the defective address stored in the register, If the repair cannot be performed, the error determination output is output and the error determination output is counted by an error counter. The control circuit is configured to perform the test signal generation circuit in accordance with the order of use of the plurality of redundant circuits including the X-system and the Y-system. When the error count output of the error counter is equal to or less than the number of the redundant circuits, the test result is output and the test operation is terminated, and when the error count output exceeds the number of the redundant circuits. Reset the register and error counter to change the combination of The output of the test signal and the error count output thereof are again judged as described above, and the error count output is also output to the redundant circuit even in the last use order combination of the plurality of redundant circuits consisting of the X system and the Y system. A semiconductor integrated circuit device that outputs a faulty output that cannot be remedied when the number of data exceeds the number. 2. The memory circuit according to claim 1, wherein the memory circuit includes a plurality of memory circuits corresponding to a plurality of memory banks, and the memory test circuit supplies a test signal to the plurality of memory banks simultaneously in parallel. Wherein the determination circuit is provided in one-to-one correspondence with a memory circuit corresponding to each memory bank. 3. An interface circuit according to claim 2, further comprising an interface circuit for serially performing an operation of inputting a test pattern and its expected value to the memory test circuit and a determination output operation including an unrepairable failure output. A semiconductor integrated circuit device characterized by the above-mentioned.