JP2000315792A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device having a high cell density and a low on-resistance while maintaining a withstand voltage when the semiconductor device is off. SOLUTION: A drain extraction region is formed in contact with a trench drain region formed from a surface of a well region to a buried region below the trench drain region, and has a width from the surface of the buried region toward the trench drain region. And the first diffusion drain region having a smaller width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral power semiconductor device, and more particularly to a semiconductor device having a high cell density while maintaining a withstand voltage and a low on-resistance.

[0002]

2. Description of the Related Art A "groove type semiconductor device" disclosed in Japanese Patent Application Laid-Open No. 8-316467 corresponds to a prior art 1 of a power semiconductor device having a U groove. This groove type semiconductor device is shown in FIG. FIG. 14A shows a planar arrangement pattern of each cell, and FIG. 14B shows a cross-sectional structure diagram corresponding to a cross-section taken along the line AA in FIG. 14A.

First, a cross-sectional structure of a conventional example will be described with reference to FIG. In FIG. 14B, an N ⁺ -type buried layer 2002 is formed on a P-type substrate 2001,
Further, an N-type well region 20 is formed on the N ⁺ type buried layer 2002.
03 is formed. In the N-type well region 2003, a P-type base region 2004 is formed. Further, an N ⁺ diffusion drain lead region 2014 is formed so as to reach the N ⁺ type buried layer 2002. An N ⁺ -type source region 2005 and a P ⁺ -type base contact region 2006 are formed in the P-type base region 2004, and a U-gate insulating film is formed inside a groove penetrating the P-type base region 2004 from the surface. A U gate electrode 2008 is formed via 2007. Further, a source electrode 2010 and a first drain electrode 2012 which are insulated from the U gate electrode 2008 by the first interlayer insulating film 2009 are formed. Further, the second drain electrode 2013 is insulated from the source electrode 2010 by the second interlayer insulating film 2011 and is connected to the first drain electrode 2012.
Are formed.

Next, a plan layout pattern of each cell is shown in FIG.
This will be described with reference to FIG. Here, the drain cell 2016
Means an N ⁺ type diffusion drain extraction region 2014
This is a region surrounded by a U gate trench 2018 in which a drain extraction region 2017 formed by is formed.
The source cell 2015 is a P ⁺ -type base contact region 20 surrounded by an N ⁺ -type source region 2005.
06 is a region separated by the U gate trench 2018 in which the gates 06 are formed. A source cell 2015 is arranged so as to surround the periphery of the drain cell 2016. Based on this pattern arrangement, the source cell 2015 is arranged.
And a drain cell 2016 are repeatedly arranged.
Here, a region between the source cell 2015 and the drain cell 2016 is a U gate trench 2018.

Next, the basic operation of the prior art 1 will be described.
When a voltage higher than the threshold value is applied to the U gate electrode 2008 in a state where a positive voltage is applied between the second drain electrode 2013 and the source electrode 2010, the U gate insulating film 20
A channel inverted to N-type is formed in the vertical direction at the interface between the transistor 07 and the P-type base region 2004. As a result, a current flows in the vertical direction through the N ⁺ -type diffusion drain extraction region 2014, subsequently flows in the N ⁺ -type buried layer 2002 in the horizontal direction, further flows in the N-type well region 2003 in the vertical direction, and passes through the channel. It flows to the N ⁺ type source region 2005. When a voltage equal to or lower than the threshold value is applied to the U gate electrode, no channel is formed in the P-type base region 2004, and a reverse bias state is established, so that the depletion layer is formed between the P-type base region 2004 and the N-type.
It spreads to the interface of the mold well region 2003 to keep the breakdown voltage.

In the prior art 1, the P-type base region 20
The source cells can be arranged at a high density by making the distance 2019 between the N.sub.04 and the N.sup. ⁺ Type diffusion drain lead region 2014 close to such a level that the breakdown voltage does not decrease.

However, in this conventional example, since the N ⁺ type drain lead region 2014 is formed by diffusion,
In order to form the N ⁺ -type drain lead-out region until reaching the N ⁺ -type buried layer while maintaining the above-mentioned breakdown voltage, the N ⁺ -type drain lead-out region 201 is expanded in the lateral direction.
4 becomes large. As a result, there was a limit to the improvement in cell density.

In order to improve this, the prior art 2 shown in FIG. 15 can be considered. FIG. 15A is a plan layout pattern diagram of each cell, and FIG. 15B is a cross-sectional view taken along the line AA in FIG.

The prior art 2 is different from the prior art 1 in that
N ⁺ -type diffusion drain extraction region 2 formed by diffusion
014, an N-type trench drain extraction region 2101 is formed by forming a trench in the N-type well region 2003 and then depositing and filling the trench with, for example, polysilicon into which an N-type impurity is implanted. Things.

Accordingly, as in the prior art 1, the P-type base region 2004 and the N-type trench drain lead-out region 21 are formed.
The area of the drain lead-out region 2014 can be reduced while maintaining the distance 2104 from 01 to maintain the required withstand voltage, so that many transistors can be arranged in the same chip area, and the cell density can be improved. can do.

[0011]

The main path of the current when the transistor of the power semiconductor device shown in the prior art 2 is on is 2100 shown in FIG. 15B. There is also a route. Since this path passes through the non-concentrated N-type well region 2003 over a long distance, the on-resistance of this path has increased. In particular, the N-type trench drain extraction region 21
In the region 2105 that contacts the lower portion of the N-type well region 2003 and the lower portion of the N-type well region 2003, although a distance on the withstand voltage is not required,
Since the concentration is not high, the region has a high on-resistance.

It is an object of the present invention to provide a semiconductor device having a high cell density and a low on-resistance while maintaining the off-state breakdown voltage of the semiconductor device.

[0013]

According to a first aspect of the present invention, there is provided a buried region of a first conductivity type formed on a semiconductor substrate and a buried region formed on the buried region. And a first impurity having a lower impurity concentration than the buried region.
A conductivity type well region; a second conductivity type base region formed on the surface of the well region; a first conductivity type source region formed on the surface of the base region; , A gate electrode formed inside the gate trench through a gate insulating film, and a trench formed from the surface of the well region where the base region is not formed to the buried region. And a drain extraction region of a first conductivity type having a higher impurity concentration than the well region, wherein the drain extraction region is a trench drain region formed from the surface of the well region toward the buried region. At the lower portion of the trench drain region, and the width decreases from the surface of the buried region toward the trench drain region. 1 and diffusion drain region, was constructed from.

According to the second aspect of the present invention, the first aspect is provided.
In the semiconductor device described above, the drain extraction region is formed between a plurality of trench drain regions formed from the surface of the well region toward the buried region, and is formed between the plurality of trench drain regions, and has a higher impurity concentration than the well region. And a first diffusion drain region which is in contact with a lower portion of the trench drain region and has a narrow width from the surface of the buried region toward the trench drain region.

[0015] In the third aspect of the invention, the first aspect is provided.
In the described semiconductor device, the trench drain region is
It is formed from the surface of the well region to the surface of the buried region, has a first width from the surface of the well region to a predetermined depth, and has a first width from the predetermined depth to the surface of the buried layer. The width was configured to be smaller than the width.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a first conductivity type buried region is formed on a semiconductor substrate, and a first conductivity type well region is formed on the buried region. Process and selectively forming a second surface on the surface of the well region.
Forming a conductive type base region, selectively forming a first conductive type source region on the surface of the base region, and forming a gate trench from the surface of the source region to the well region; Forming a gate electrode on the side and bottom surfaces of the gate trench through an insulating film; and forming a gate electrode in a region where the base region is not formed, from the surface of the well region toward the buried region. Forming a trench, and implanting an impurity having a higher impurity concentration than the well region into the drain trench.
Forming a diffusion drain region from the bottom surface of the drain trench to the buried region; and forming a trench drain region by burying the drain trench.

According to a fifth aspect of the present invention, in the method of the fourth aspect, the gate trench and the drain trench are formed in the same step.

In the method of manufacturing a semiconductor device according to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the step of forming the drain trench is performed until the surface of the well region reaches the surface of the buried region. Along with
Has a first width at a predetermined depth from the well region surface,
The step of forming a drain trench having a width smaller than the first width from a predetermined depth to the buried layer surface is performed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. First, FIG.
The structure of the first embodiment will be described with reference to FIG. FIG.
FIG. 1B is a diagram showing a planar arrangement pattern, and FIG.
FIG. 2 is a cross-sectional view taken along line AA in FIG.

A description will be given with reference to FIG. 2001
Is a P-type silicon substrate.
An N ⁺ type buried region 2002 is formed thereon. On the N ⁺ type buried region 2002, an N type well region 200 is formed.
3 are formed. On the surface of the N-type well region 2003, a P-type base region 2004 is formed. From the surface of the P-type base region 2004 to the N-type well region 2
003 is formed, a gate insulating film 2007 is formed on the side and bottom surfaces of the trench,
The inside of the gate insulating film 2007 is filled with polysilicon to form a gate electrode 2008. Also, P
N ⁺ type source region 20 from the surface of type base region 2004
05 is formed. This N ⁺ type source region 2005
A P ⁺ -type base contact region 2006 is formed in a region surrounded by P.sup. 2009 is a first interlayer insulating film. On the N ⁺ type source region 2005 and the P ⁺ type base contact region 2006, a source electrode 2010 is formed.

The N ⁺ -type trench drain region 101 made of polysilicon is formed in a rectangular cross section from the surface of the N-type well region 2003 so as not to reach the N ⁺ -type buried layer 2002. Reference numeral 102 denotes an N ⁺ type first diffusion drain region 102 which covers a lower portion of the N ⁺ type trench drain region 101 and an N ⁺ type buried region 200.
2. The N ⁺ type first diffusion drain region 102 is formed so as to expand as the depth increases. Also, N ⁺
N ⁺ type first
A region not surrounded by the diffusion drain region 102 is surrounded by the N ⁺ type second diffusion drain region 103.

Reference numeral 2012 denotes a first drain electrode,
It is formed on the ⁺ type trench drain region 101.
Reference numeral 2013 denotes a second drain electrode, which is connected to the first drain electrode 2012. Reference numeral 2011 denotes a second interlayer insulating film, which is formed to insulate the connection between the source electrode 2010 and the first and second drain electrodes 2012 and 2013.

Reference numeral 107 denotes a distance between the P-type base region 2004 and the N ⁺ -type second diffusion drain region 103;
Base region 2004 and N ⁺ type first diffusion drain region 1
02, which is a distance capable of maintaining a withstand voltage when the transistor is off.

Next, description will be made with reference to FIG. In FIG. 1B, illustration and description of the interlayer insulating films 2009 and 2011, the source electrode 2010, and the drain electrodes 2012 and 2013 are omitted for simplification.

Reference numeral 106 denotes an N ⁺ type trench drain region 10
1 and an area surrounded by the N ⁺ type second diffusion drain region 103, which is defined as a drain extraction region. 10
4 is a drain extraction region 10 from the gate electrode 2008.
This is a region up to 6 and is a drain cell.
105 is an N ⁺ type source region 2005 formed so as to surround the P ⁺ type base contact region 2006;
Define as source cell. The gate electrode 2008 is formed between the source cell 105 and the drain cell 104. That is, the drain cell 104 is formed so as to be surrounded by the plurality of source cells 105 via the gate region 2008.

Next, the operation will be described with reference to FIG. 1A. The second drain electrode 2013 and the source electrode 2010
And a positive voltage is applied between the gate electrode 2008
Is applied to the gate insulating film 20
A channel is formed in the vertical direction at the interface of the P-type base region 2004 in contact with 07, and an N-type inversion layer is formed. Accordingly, from the drain electrode 2012, the N ⁺ type trench drain region 101 and the N ⁺ type second diffusion drain region 103 are arranged in the vertical direction, the N ⁺ type first diffusion drain region 102 is arranged in the vertical direction, and the N ⁺ type buried region 2002 is formed. Flows in the horizontal direction, the N-type well region 2003 in the vertical direction, the channel in the vertical direction, and the N ⁺ -type source region 2005 (current path 1500).
The transistor turns on. When a voltage lower than the threshold is applied to the gate electrode 2008, no channel is formed and no current flows.

A feature of the embodiment of the present invention is that N ⁺
By forming the first diffusion region 102,
In the current path 1501 flowing through the N-type well region 2003, the distance passing through the N-type well region 2003 having high on-resistance is short. Thus, in the current path 1501, the on-resistance of the entire device can be reduced. Further, the N ⁺ type first diffusion drain region 10
In No. 2, since the distance from the P-type base region 2004 is maintained so as to maintain the breakdown voltage, the breakdown voltage can be maintained. Further, the N ⁺ type trench drain region 101 and N ⁺
Since the type second diffusion drain region 103 is formed not in a shape having a lateral spread but in a rectangular shape, the cell density can be increased while maintaining the distance 107 from the P-type base region 2004 to maintain the breakdown voltage. Can be higher.

That is, it is possible to provide a transistor having a high cell density and a low on-resistance while maintaining the off-state breakdown voltage.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

An N ⁺ type buried region 2002 is formed on the surface of a P type silicon substrate 2001 by impurity implantation / diffusion.
Next, an N-type well region 2003 is formed on the surface of the N ⁺ -type buried region 2002 by epitaxial growth (FIG. 2).

Next, a P-type base region 2004 selectively patterned is formed on the surface of the N-type well region 2003 by impurity implantation / diffusion. Next, on the surface of the P-type base region 2004, selectively patterned N
^A diffusion region serving as a ⁺ type source region 2005 and a P ⁺ type base contact region 2006 are formed by impurity implantation / diffusion (FIG. 3).

Next, a predetermined region of the diffusion region to be the N ⁺ -type source region 2005 and the N-type buried region 2003 are selectively etched from the surface to form a gate trench 401 and a drain trench 402 (FIG. 4). 4). In FIG. 4, the gate trench 401 and the drain trench 402 have different depths, so that the etching is performed twice. However, the same depth reduces the number of steps. can do.

Next, a resist film 501 is formed in portions other than the drain trenches 402, and the trench drains 4 are formed.
An impurity such as phosphorus is implanted only into the bottom of the substrate 02. Next, the implanted impurities are removed from the bottom of the drain trench 402.
Diffusion is performed until reaching the surface of the N ⁺ type buried region 2002,
^{A +} -type first diffusion drain region 102 is formed. By this diffusion step, an N ⁺ type first diffusion drain region 102 is formed so as to surround the lower portion of the trench (FIG. 5).

Next, N ^{+ is formed in the} drain trench 402.
Embedding doped polysilicon in the mold (low resistance),
An N ⁺ type trench drain region 101 is formed. Next, the resist film 501 is removed (FIG. 6).

Next, a gate oxide film 2007 is formed on the side and bottom surfaces of the gate trench 401 by thermal oxidation.
A gate electrode 2008 is formed by embedding low-resistance polysilicon. In the thermal oxidation process for forming the gate oxide film 2007, the N ⁺ -type trench drain region 1
This is a high-concentration N ⁺ -type second diffusion drain region formed by diffusion from No. 01 (FIG. 7).

Next, as shown in FIG. 8, after forming a first interlayer insulating film 2009, the source electrode 2010 and the first
A drain electrode 2012 is formed, then a second interlayer insulating film 2011 is formed as shown in FIG. 9, a second drain electrode 2013 is formed, and finally a final protection film (not shown) is formed.

(Second Embodiment) An embodiment of the second invention will be described with reference to FIGS. Note that the second embodiment of the present invention will be described focusing on the difference from the first embodiment.

1001 is an N ⁺ type trench drain region,
1003 is an N ⁺ type second diffusion drain region, and 1002 is N
^{This is a +} type first diffusion drain region.

FIG. 11 is an enlarged perspective view showing only the main part of FIG. 10 and, as shown in FIG. 11, the N ⁺ type trench drain region 1001
It is composed of a diffusion drain region 1010 and a second diffusion drain region 1011 formed so as to surround the first diffusion drain region 1010 via the N ⁺ type second diffusion drain region 1002. This N ⁺ type trench drain region 10
No. 01 is filled with N ⁺ -doped polysilicon as in the first embodiment. Note that the N ⁺ -type trench drain region 1001 of the first embodiment N ⁺
The same volume as the trench drain region 101 and N ⁺
The type second diffusion drain region 1003 and the N ⁺ type second diffusion drain region 103 of the first embodiment have the same volume.

In the second embodiment, the N ⁺
Since the trench drain region 1001 is divided into a first diffusion drain region 1010 and a second diffusion drain region 1011, the manufacturing process used in the first embodiment shown in FIG. In the step of forming a gate oxide film, an N ⁺ type trench drain region 1001 is formed.
Diffusion of impurities into the N-type well region 2003 can be reduced. Therefore, there is an effect that the physical properties of the N ⁺ -type well region are stabilized.

The N ⁺ type trench drain region 1
By dividing 001 into a plurality of narrow regions, it is easy to embed polysilicon in a single step in the step of embedding polysilicon, and the number of manufacturing steps can be reduced.

In the second embodiment, the N ⁺ type trench drain region 1001 is located at the center of the first trench drain region 1001.
The diffusion drain region 1010 is replaced with the second diffusion drain region 10
Although the first diffusion drain region is formed so as to be surrounded by 11, the first diffusion drain region may be configured in parallel.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. Note that the third embodiment of the present invention will be described focusing on the differences from the first embodiment.

Numeral 1101 denotes an N ⁺ type trench drain region,
1013 is an N ⁺ type second diffusion drain region, 1102 is N
^{This is a +} type first diffusion drain region.

[0046] In the third embodiment, N ⁺ -type trench drain region 1101 a two-stage structure, ie to form so that the cross-sectional shape in the opposite convex shape, N ⁺ -type buried region 2
002.

FIG. 13 is an enlarged perspective view showing only the main part of FIG. 12. As shown in FIG. 13, the N ⁺ type trench drain region 1101 is separated from the first shoulder 1200 and the second shoulder 1201. A shoulder 1202.

In this embodiment, the N ⁺ -type first diffusion drain region 1102 can be sufficiently diffused by the shoulder 1202. That is, in the step of FIG. 5 of the manufacturing process used in the first embodiment, that is, in the step of implanting impurities into the drain trench, impurities are implanted into the first shoulder 1200 and the second shoulder 1201. In the subsequent diffusion process, the impurity diffuses, so that the N ⁺ type first
The diffusion drain region 1102 can be formed large. Therefore, in addition to the effects of the first embodiment,
The on-resistance can be further reduced.

[0049]

As described above, according to the present invention, the following effects can be obtained. 2. The trench drain region according to claim 1, wherein the drain extraction region is in contact with a trench drain region formed from the surface of the well region toward the buried region below the trench drain region, and the trench drain region is formed from the surface of the buried region. , The width of the trench drain region is reduced,
Since the first diffusion drain region can be enlarged,
While maintaining the withstand voltage during non-operation, the first drain diffusion region having a high cell density and a low on-resistance, which is a path during operation, can be enlarged, and the on-resistance during operation can be reduced. it can.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a plurality of trench drain regions formed from the surface of the well region toward the buried region, and a region between the plurality of trench drain regions. And a second diffusion drain region having an impurity concentration higher than that of the well region and being in contact with a lower portion of the trench drain region and having a narrower width from the surface of the buried region toward the trench drain region. Since the drain extraction region is formed, the diffusion of impurities from the trench drain region to the well region can be suppressed to a low level in addition to the effect of the invention described in claim 1, and a stable semiconductor device can be obtained. And the number of steps for burying the trench drain region can be reduced, and the number of manufacturing steps can be reduced. A.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, a trench drain region is formed from the surface of the well region to the surface of the buried region, and the trench drain region is formed from the surface of the well region. The first diffusion drain has a first width at a predetermined depth, and has a width smaller than the first width from the predetermined depth to the buried layer surface. Since the region can be configured to be larger, a semiconductor device that can reduce the on-resistance during operation more than the first aspect of the invention can be obtained.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a first conductivity type buried region is formed on the semiconductor substrate, and a first conductivity type well region is formed on the buried region. Forming, selectively forming a second conductivity type base region on the surface of the well region, selectively forming a first conductivity type source region on the surface of the base region, A step of forming a gate trench from the surface of the region to the well region, a step of forming a gate electrode on the side and bottom surfaces of the gate trench via an insulating film, and a region where the base region is not formed. Forming a drain trench from the surface of the well region toward the buried region; implanting and diffusing an impurity having a higher impurity concentration than the well region into the drain trench; Since the method includes the steps of forming a diffusion drain region from the bottom of the rain trench to the buried region and burying the drain trench to form a trench drain region, the width of the trench drain region is reduced. In addition, since the first diffusion drain region can be enlarged, the first drain diffusion region having a high cell density and a low on-resistance, which is a passage during operation, while maintaining the breakdown voltage during non-operation is increased. And a semiconductor device capable of reducing on-resistance during operation can be obtained.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the gate trench and the drain trench are formed by:
Since the semiconductor device is formed in the same step, the number of manufacturing steps can be reduced in addition to the effect of the method of manufacturing a semiconductor device according to the fourth aspect.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the step of forming a drain trench is performed until the drain trench surface reaches the buried region surface. A drain trench having a first width from the surface of the well region to a predetermined depth and a width smaller than the first width from the predetermined depth to the surface of the buried layer is formed. Since the first diffusion drain region can be configured to be larger in the diffusion step, the on-resistance during operation can be further reduced as compared with the invention according to claim 4. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 7 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 8 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 10 is a diagram illustrating a semiconductor device according to a second embodiment;

FIG. 11 is an enlarged perspective view of a main part of a semiconductor device according to a second embodiment.

FIG. 12 is a diagram illustrating a semiconductor device according to a third embodiment;

FIG. 13 is an enlarged view of a main part of a semiconductor device according to a third embodiment.

FIG. 14 is a diagram showing a first conventional technique.

FIG. 15 is a diagram showing a second conventional technique.

[Explanation of symbols]

Reference Signs List 101 N ⁺ type trench drain region 102 N ⁺ type first diffusion drain region 103 N ⁺ type second diffusion drain region 104 Drain cell 105 Source cell 106 Drain extraction region 107 Distance 1 108 Distance 2 109 U gate trench 401 U gate trench 402 Drain trench 501 Resist film 1001 N ⁺ -type trench drain region 1002 N ⁺ -type first diffusion drain region 1003 N ⁺ -type second diffusion drain region 1004 Distance 3 1005 Distance 4 1101 N ⁺ -type two-stage trench drain region 1102 N ⁺ -type diffusion drain region 1103 N ⁺ type trench lateral extension area 1104 distance 5 1105 distance 6 2001 P-type substrate 2002 N ⁺ -type buried layer 2003 N-type well region 2004 P-type base region 2005 N ⁺ -type source region 2006 ⁺ -Type base contact region 2007 U gate insulating film 2008 U gate electrode 2009 first interlayer insulating film 2010 source electrode 2011 second interlayer insulating film 2012 first drain electrode 2013 second drain electrode 2014 N ⁺ -type diffused drain extraction region 2015 source cell 2016 Drain cell 2017 Drain extraction region 2018 U gate trench 2019 Distance 7 2101 N ⁺ type trench drain extraction region 2102 Drain cell 2103 Source cell 2104 Distance 8 2105 Region 1 2106 U gate trench 2107 Drain extraction region

Claims (6)

[Claims] A first conductivity type buried region formed on a semiconductor substrate; and a first conductivity type well region formed on the buried region and having a lower impurity concentration than the buried region. A second conductivity type base region formed on the surface of the well region; a first conductivity type source region formed on the surface of the base region; and a region extending from the surface of the base region to the well region. A gate trench formed, a gate electrode formed inside the gate trench via a gate insulating film, and a gate electrode formed from the surface of the well region where the base region is not formed to reach the buried region. A first conductivity type drain extraction region having an impurity concentration higher than that of the well region, wherein the drain extraction region includes a surface of the well region. A trench drain region formed from the buried region to the buried region; and a first diffusion drain region contacting at a lower portion of the trench drain region and having a width narrower from the buried region surface toward the trench drain region. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the drain extraction region includes a plurality of trench drain regions formed from the surface of the well region toward the buried region, and a region between the plurality of trench drain regions. A second diffusion drain region having an impurity concentration higher than that of the well region and being in contact with a lower portion of the trench drain region and having a width decreasing from the surface of the buried region toward the trench drain region; A semiconductor device, comprising: one diffusion drain region; 3. The semiconductor device according to claim 1, wherein the trench drain region is formed from the surface of the well region to the surface of the buried region, and the trench drain region is formed at a predetermined depth from the surface of the well region. And a width smaller than the first width from a predetermined depth to the surface of the buried layer. 4. A step of forming a buried region of a first conductivity type on a semiconductor substrate, a step of forming a well region of a first conductivity type on the buried region, and selectively forming a surface of the well region. Forming a base region of the second conductivity type on the base region; selectively forming a source region of the first conductivity type on the surface of the base region; and forming a gate trench from the surface of the source region to the well region. Forming a gate electrode on the side and bottom surfaces of the gate trench via an insulating film; and forming the gate electrode in a region where the base region is not formed, from the surface of the well region. Forming a drain trench toward the drain region; implanting and diffusing an impurity having a higher impurity concentration than the well region into the drain trench; Step and a step of forming a trench drain regions by embedding the drain trench, a method of manufacturing a semiconductor device comprising a forming a diffusion drain region to reach said buried region from. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the gate trench and the drain trench are
A method for manufacturing a semiconductor device, wherein the semiconductor devices are formed in the same step. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the drain trench is performed from the surface of the well region to the surface of the buried region, and from the surface of the well region. Forming a drain trench having a first width at a predetermined depth and a width smaller than the first width from the predetermined depth to the buried layer surface; Manufacturing method of a semiconductor device.