JP2000315691A - Semiconductor device - Google Patents

Abstract

(57) [Problem] It is difficult to obtain a sufficient withstand voltage even when an FLR is provided in a transistor. SOLUTION: A base region 11, an emitter region 12, and first, second, third and fourth collector regions 13, 14, 1 are provided.
5, 16 and field limiting ring (FL
R) region 17 is provided. The first collector region 13 is made adjacent to the base region 11. The second and third collector regions 14 and 15 are formed so as to be included in the base region 11 in plan view. The impurity concentration is increased in the order of the first, second and third collector regions 13, 14 and 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a bipolar transistor and an insulated gate type field effect transistor in which the withstand voltage has been improved to a high level.

[0002]

2. Description of the Related Art As shown in FIG. 1, a power transistor in which an emitter region 2 surrounded by a base region 1 is formed in a lattice or island shape is known. In the transistor of FIG. 1, in order to improve the breakdown voltage on the outer peripheral side of the PN junction 5 between the P-type collector region 3 and the N-type base region 1 adjacent to the P ⁺ -type collector region 4, the base region 1 Field limiting ring or FLR comprising the same N-type semiconductor region as base region 1 so as to surround the outer periphery of FLR.
(Field Limiting Ring) region 6 is formed. The FLR region 6 is sometimes called a gart ring, and contributes to the improvement of the breakdown voltage of the planar structure. In addition, 7 is a base electrode, 8 is an emitter electrode, and 9 is a collector electrode.

[0003]

However, simply forming the FLR region 6 did not provide a sufficient withstand voltage improvement effect. The reason is that the depletion layer extending from the FLR region 6 reaches the P-type collector region 4 (reach-through), the extension of the depletion layer is restricted, and the electric field relaxation effect by the depletion layer is not sufficiently exhibited. Therefore, the present inventor has proposed that the minimum distance between the field limiting ring region and the collector region is increased by selectively forming the collector region at a position facing the base region without forming the collector region over the entire semiconductor substrate. A semiconductor device having such a configuration was manufactured. But,
Even in the semiconductor device having such a structure, the withstand voltage improving effect was not sufficiently obtained as expected. The above problem also occurs in other semiconductor devices such as a diode. In addition, it occurs in a semiconductor device having no FLR region.

Accordingly, it is an object of the present invention to provide a semiconductor device capable of improving the breakdown voltage.

[0005]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems and achieving the above-mentioned objects will be described with reference to the drawings showing the embodiments. A semiconductor device having at least a first semiconductor region 11 of a first conductivity type and a second semiconductor region 11 of a second conductivity type opposite to the first conductivity type. Third and fourth semiconductor regions 13, 1
4, 15 or 13, 14a, 15a, and the first
Semiconductor region 11 is one main surface 1 of semiconductor substrate 10.
8 and are arranged in an island shape in the second semiconductor region 13, and the second semiconductor region 13 is formed on a part of one main surface 18 of the semiconductor substrate 10. The third semiconductor region 14 or 14a has an impurity concentration higher than the impurity concentration of the second semiconductor region 13;
And the other main surface 24 of the semiconductor substrate 10, wherein the fourth semiconductor region 15 or 15 a is
And has an impurity concentration higher than that of the semiconductor region 14 or 14a and is disposed between the third semiconductor region 14 or 14a and the other main surface 24 of the semiconductor substrate 10 or in the third semiconductor region 14a. The third semiconductor region 14 or 14a and the fourth semiconductor region 15 or 15a
The first electrode 21 is disposed inside the first semiconductor region 11 in a plan view, and the first electrode 21 is disposed on one main surface 18 of the semiconductor substrate 10 and electrically connected to the first semiconductor region 11. A second electrode 25 disposed on the other main surface 24 of the semiconductor substrate 10 and electrically connected to the fourth semiconductor region 15 or 15a directly or via the semiconductor region. It concerns the device.

It is desirable that a field limiting ring region 17 be provided. In addition, as described in claim 3, the field play
It is desirable to provide a gate 21a. It is desirable to provide a fifth semiconductor region corresponding to the fourth collector region 16 of the embodiment. Further, as described in claim 5, the fourth semiconductor region (for example, the third collector region) 15a can be arranged in the third semiconductor region (for example, the second collector region) 14a. In addition, a transistor can be used.

[0007]

According to the invention of each claim, the third and fourth semiconductor regions 14 and 15 are formed so as to be included in the first semiconductor region 11 in plan view. The thickness of the low impurity concentration second semiconductor region 13 around the region 11 is increased, and the peripheral breakdown voltage is improved. Since the third and fourth semiconductor regions 14 and 15 having a high impurity concentration are arranged in the region facing the first semiconductor region 11, the forward voltage drop here is reduced. The third semiconductor region 1 having an impurity concentration lower than that of the fourth semiconductor region 15
Since 4 is a region that allows the depletion layer to spread due to a reverse bias of the PN junction, the breakdown voltage of the central region of the semiconductor substrate 10 can be increased. According to the second aspect of the present invention, the withstand voltage improving effect of the field limiting ring region 17 can be rationally obtained. Also,
According to the third aspect of the invention, the withstand voltage can be improved by the field plate.

[0008]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

[0009]

First Embodiment A bipolar transistor according to a first embodiment shown in FIG. 2 has a base region 11 made of an N-type semiconductor region, an emitter region 12 made of a P ⁺ type semiconductor region, ^A first collector region 13 composed of a-type semiconductor region, a second collector region 14 composed of a P-type semiconductor region having a higher impurity concentration than the first collector region 13, and an impurity concentration higher than the second collector region 14. A third collector region 15 composed of a P ⁺ -type semiconductor region having a high impurity concentration, a fourth collector region 16 composed of a P ⁺ -type semiconductor region having a higher impurity concentration than the third collector region 15, and the same as the base region 11. FLR (field limiting ring) composed of N-type semiconductor region
Region 17. In the claims, the first semiconductor region corresponds to the base region, and the second, third, fourth, and fifth semiconductor regions correspond to the first, second, third, and fourth collector regions 13, 14,. 15 and 16 are supported. An insulating film 19 is provided on one main surface, that is, the upper surface 18 of the semiconductor substrate 10, and a base electrode 21 as a first electrode is connected to the base region 11 through an opening 20 provided therein,
An emitter electrode 23 is connected to the emitter region 12 via the opening 22. A collector electrode 25 as a second electrode is provided on the other main surface, that is, the lower surface 24 of the semiconductor substrate 10, and is connected to the fourth collector region 16.

In the power bipolar transistor of the present embodiment, the base region 11 and the emitter region 12 are formed substantially the same as the power bipolar transistor of FIG. 1, but the first, second, third and third power bipolar transistors are formed. Collector area 1 of 4
3, 14, 15, and 16 and the FLR region 17 are different from FIG.

The base region 11 is a first collector region 13
Are formed in an island shape by impurity diffusion, and the bottom surface and the side surfaces are surrounded by the first collector region 13, and a PN junction 26 is formed therebetween. The emitter region 12 is formed in a lattice shape in the base region 11 by impurity diffusion in a plan view. As a result, a transistor having a base island structure in which the base region 11 is exposed in an island shape on the upper surface 18 of the semiconductor substrate 10 is obtained. In addition,
The emitter region 12 is formed in an island shape by impurity diffusion in the base region 11 when viewed in a plan view.
It is also possible to adopt a structure in which the base region 11 is exposed in a lattice shape.

The first collector region 13 surrounds the base region 11 and the FLR region 17 as in FIG.
Below the LR region 17, the fourth collector region 16
It is formed so as to reach the collector electrode 25 only through the gate electrode. The impurity concentration of the first collector region 13 (about 1 × 1
The second collector region 14 having an impurity concentration (about 1 × 10 ¹⁶ cm ⁻³ ) higher than 0 ¹³ to 1 × 10 ¹⁴ cm ⁻³ ) faces the entire lower surface 24 of the semiconductor substrate 10. The base region 1 is not formed and viewed in plan.
1 is formed. That is, the outer peripheral side of the second collector region 14 except for the portion of the lower surface 24 that is in contact with the fourth collector region 25 is the first collector region 1.
3 surrounded. This second collector region 14
It can be formed by diffusing impurities into the first collector region 13 from the lower surface 24 side. The outermost peripheral edge of the second collector region 14 has a base electrode 2
1 is arranged between the outermost peripheral edge of the portion connected to the base region 11 and the innermost peripheral edge of the FLR region 17. Therefore, the FLR region 17 and the second collector region 14
Is longer than the shortest distance L1 between the base region 11 and the second collector region 14. Also,
The shortest distance L3 between the FLR region 17 and the fourth collector region 16 is longer than L1.

A third collector region 15 having a higher impurity concentration than the second collector region 14 (about ^{1 × 10 19 ~1 × 10 2} 0 cm -3) , the lower surface of the semiconductor substrate 10 2
4 is not formed in the entire region, but is formed in a range included in the second collector region 14 in plan view. In other words, the third collector region 15 has the second collector region 14 except for the portion in contact with the fourth collector region 16 on the lower surface.
Besieged. The third collector region 15 can be formed by diffusing impurities into the second collector region 14 from the lower surface 24 side.

A fourth collector region 16 having a higher impurity concentration (for example, 2 × 10 ²⁰ cm ⁻³ ) than the third collector region 15 is formed over the entire lower surface 24 of the semiconductor substrate 10. The upper surface is in contact with the first, second and third collector regions 13, 14, 15. The fourth collector region 16 can be formed by diffusing impurities in the entire region of the lower surface 24 of the semiconductor substrate 10.

The two FLR regions 17 include the base region 11
Is formed in an annular shape when viewed in plan so as to surround the outer periphery of the device at a distance. The FLR region 17 is surrounded by the first collector region 13 except for the surface, and the surface is covered with an insulating film 19. The impurity concentration of the FR region 17 is the same as the impurity concentration of the base region 11 and the FLR region 1
The diffusion depth 7 is the same as the diffusion depth of the base region 11.
Therefore, the FLR region 17 can be formed by the same diffusion process as the base region 11, which is advantageous in terms of productivity. However, the FLR region 17 may be formed by a different diffusion process from the base region 11 so that the impurity concentration of the FLR region 17 is lower than the impurity concentration of the base region 11. In this case, there is obtained an advantage that a depletion layer for alleviating the electric field concentration on the outer peripheral side of the first PN junction 26 formed at the interface between the base region and the collector region 13 can be better formed. Further, for the same reason, the FLR region 17 may be formed to be diffused deeper than the base region 11. FLR
Whether or not the region 17 is formed by the same diffusion step as that of the base region 11 should be determined depending on the required breakdown voltage level and the like. In the transistor of this embodiment, since the second and third collector regions 14 and 15 are not provided below the FLR region 17, the second PN region is provided between the FLR region 17 and the first collector region 13. Since the depletion layer extending from the junction 27 is prevented from reaching the second and fourth collector regions 14 and 16, even if the FLR region 17 is formed by the same diffusion process as the base region 11, a sufficiently high breakdown voltage Can be achieved. This will be described later in detail.

The transistor of this embodiment can be formed as follows. First, as shown in FIG. 4, a P-type semiconductor substrate 30 is prepared, and a mask 32 made of an insulating film (such as a silicon oxide film) is formed on a lower surface 31 thereof. The insulating film mask 32 includes the second and third collector regions 14,
An opening 33 is provided corresponding to a region where 15 is to be formed.
No insulating film is formed on the upper surface 34 of the semiconductor substrate. In addition,
Part of the semiconductor substrate 30 finally forms the first collector region 13.

Next, a P-type impurity diffusion solvent prepared by dissolving B ₂ O ₃ and AlCl ₃ in a solvent (for example, alcohol) is prepared.
And the other main surface 34. Subsequently, by performing a heat treatment on this, boron and aluminum as P-type impurities are diffused from the solvent into the semiconductor substrate. Semiconductor substrate 30
Since no mask is formed on the upper surface 34, the P-type impurity is diffused over the entire surface. On the other hand, the semiconductor substrate 30
This P-type impurity is selectively diffused in the lower surface 31 through the opening 33 of the mask into the central region. Where P
The diffusion coefficient of boron as a type impurity is different from that of aluminum, and the diffusion coefficient of aluminum is sufficiently larger than that of boron, so that aluminum diffuses relatively deeply into the semiconductor substrate 30 as shown in FIG. On the lower surface 31 side, a second collector region 14 in which aluminum is dominant is formed, and boron is diffused shallower than aluminum to form a third collector region 15 in which boron is dominant but also contains aluminum. You. Therefore, the third
The impurity concentration of the collector region 15 is higher than that of the second collector region 14. On the upper surface 34 side, a P-type impurity diffusion layer 35 in which aluminum is dominant and a P ⁺ -type impurity diffusion layer 36 in which boron is dominant are formed.

Next, as a P-type impurity, for example, aluminum is formed relatively shallowly over the entire lower surface 31 of the semiconductor substrate 30, and the impurity concentration is higher than that of the third collector region 15 as shown in FIG. A high fourth collector region 16 is formed. The second and third collector regions 1
Lower surface 3 of semiconductor substrate 30 for selectively diffusing 4 and 15
When the mask 32 formed in 1 is formed of a silicon oxide film, only aluminum among the P-type impurities contained in the P-type impurity diffusion solvent selectively diffuses through the mask 32 to the lower surface side of the semiconductor substrate 30. . On the other hand, the diffusion of boron among the P-type impurities is prevented by the mask 32. Therefore, a diffusion mask 32 made of a silicon oxide film is used.
Is used, the second, third and fourth collector regions 1
4, 15, and 16 can be formed simultaneously.

Next, as shown in FIG.
The P-type and P ⁺ -type impurity diffusion layers 35 and 36 formed on the side of the upper surface 34 and a part of the P ⁻ -type semiconductor region 30a are removed by etching. Thereby, the substrate 10 having the first collector region 13 is obtained.

Next, as is well known, a mask made of an insulating film made of a silicon oxide film or the like is formed on the upper surface of the semiconductor substrate 10, and N-type impurities and P-type impurities are selectively diffused through openings of the mask, As shown in FIG. 8, a base region 11, an emitter region 12, and an FLR region 17 are formed.

Finally, the base electrode 21, the emitter electrode 23, and the collector electrode 25 are formed on the upper surface 18 and the lower surface 24 of the semiconductor substrate 10 by using a well-known vacuum deposition technique or the like, thereby completing the transistor of FIG. Let it.

According to the transistor of this embodiment, the following effects can be obtained. (1) First PN junction 2 formed between base region 11 and first collector region 13 of the transistor in FIG.
When a voltage is applied in the direction of biasing 6 in the reverse direction, the depletion layer expands from the first PN junction 26. This depletion layer mainly has a lower impurity concentration in the first collector region 13 than in the base region 11.
Spread to the side. Also, when this applied voltage increases, FLR
A second PN between region 17 and first collector region 13;
The depletion layer also extends from the junction 27. However, FLR region 1
7, the second collector region 14 is not formed, and the shortest distance L2 between the FLR region 17 and the second collector region 14 is the shortest distance between the base region 11 and the second collector region 14. Since it is longer than the distance L1, FLR
The depletion layer extending from region 17 is less likely to reach second collector region 14. Therefore, the extension of the depletion layer on the surface 18 of the semiconductor substrate 10 is not limited, which is advantageous for achieving a high breakdown voltage. Further, in the transistor of the present embodiment, a second collector region 14 having an impurity concentration intermediate between the first collector region 13 and the third collector region 15 is formed between the first collector region 13 and the third collector region 15. Therefore, a depletion layer extending from first PN junction 26 forms second collector region 14.
And the breakdown voltage can be further increased. As a result, a high breakdown voltage is achieved at a high level. (2) As described above, since the second collector region 14 is a region where the depletion layer extends, the thickness of the first collector region 13 having the lowest impurity concentration, that is, the base region 11 and the second collector region 14 (Corresponding to the shortest distance L1 between the base region 11 and the second collector region 14) does not need to be set large to improve the breakdown voltage. If the second
When the structure in which the collector region 14 is not provided is used, it is necessary to increase the thickness of the first collector region 13 in order to improve the breakdown voltage. As described above, in the present embodiment, the thickness of the first collector region 13 having a low impurity level can be relatively reduced.
Therefore, the thickness VF can be relatively reduced in the forward direction, and the current amplification factor hFE can be improved.

[0023]

[Second Embodiment] Next, referring to FIG.
The transistor will be described. However, FIG. 9 and FIG.
0, the same reference numerals are used for the substantially same parts as those in FIG.
The description is omitted here. The transistor in FIG.
Second, third and fourth collector regions of two transistors
The second, third, and fourth collections obtained by modifying 14, 15, and 16
2 except that the contactor regions 14a, 15a and 16a are formed.
And formed substantially identically. In FIG.
The second and third collector regions 14a, 15a are the first and third collector regions.
As a buried region of the fourth collector regions 13 and 16a
Is formed. That is, the P-type fourth collector region 16
a as substrate⁻The first collector region 13 of the mold
When growing a tax, P⁺The second collector area of the mold
Region 14a and P ⁺⁺Mold third collector region 15a is buried.
It is embedded. According to the second embodiment, the first
As in the embodiment, the breakdown voltage is improved, the forward voltage is reduced, and the current is reduced.
The effect of improving the amplification factor is obtained.

[0024]

Third Embodiment A transistor according to a third embodiment shown in FIG. 10 is similar to the first transistor shown in FIG. 2 except that the FLR region 17 is omitted and a field plate 21a is provided.
It has the same configuration as that of FIG. Field plate 21
“a” is provided as an extension of the base current 21 and is arranged so as to face the collector region 13 surrounding the base region 11 via the insulating film 19. Note that the thickness of the insulating film 19 is determined according to the withstand voltage. This field plate 21a
Prevents the inversion layer from being formed on the surface of the collector region 13 and contributes to the improvement of the breakdown voltage. The effect based on the four collector regions 13, 14, 15, 16 is obtained in the same manner as in the first embodiment.

[0025]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The present invention can be applied to a diode. That is, a structure in which the emitter region 12 is omitted from the transistors of FIGS. 2, 9 and 10 or a structure in which the emitter electrode 23 and the base electrode 21 are connected can be employed. (2) A structure in which the fourth collector region 16 is omitted can be provided. In this case, the collector electrode 2 is provided on the third collector region 15 or the second and third collector regions 14 and 15.
5 is connected. (3) The FLR region 17a is omitted from the transistor of FIG. 9 and the field plate 21 of FIG.
The same thing as a can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional transistor.

FIG. 2 is a cross-sectional view showing a transistor according to a first example of the present invention.

FIG. 3 is a plan view illustrating a surface of the semiconductor substrate of FIG. 2;

FIG. 4 is a sectional view schematically showing a semiconductor substrate for manufacturing the transistor of FIG. 2;

FIG. 5 is a cross-sectional view illustrating a substrate in which second and third collector regions are formed on the substrate of FIG. 4;

FIG. 6 is a cross-sectional view showing a fourth collector region formed on the substrate of FIG. 5;

FIG. 7 is a cross-sectional view showing an unnecessary part removed from the substrate of FIG. 6;

FIG. 8 shows a base region, an emitter region, and a FL on the substrate of FIG. 7;
It is sectional drawing which shows what formed the R area.

FIG. 9 is a cross-sectional view illustrating a transistor according to a second embodiment.

FIG. 10 is a sectional view showing a transistor according to a third embodiment.

[Explanation of symbols]

 Reference Signs List 11 base region 12 emitter region 13 first collector region 14 second collector region 15 third collector region 16 fourth collector region 17 FLR region

Claims (6)

[Claims] 1. A semiconductor device having a semiconductor substrate (10) and at least first and second electrodes (21, 25), wherein the semiconductor substrate (10) has at least a first conductivity type first substrate. Semiconductor region (11) and second, third, and fourth semiconductor regions (13, 1) of a second conductivity type opposite to the first conductivity type.
4, 15 or 13, 14a, 15a), wherein the first semiconductor region (11) is provided on the semiconductor substrate (1).
0) is arranged so as to be exposed on a part of one main surface (18) and is arranged in an island shape in the second semiconductor region (13), and the second semiconductor region (13) is Semiconductor substrate (1
0), the third semiconductor region (14 or 14a) is disposed so as to be exposed at a part of one main surface (18) of the second semiconductor region (13). And disposed between the second semiconductor region (13) and the other main surface (24) of the semiconductor substrate (10), wherein the fourth semiconductor region (15 or 15a) is 3
Having a higher impurity concentration than the semiconductor region (14 or 14a), and between the third semiconductor region (14 or 14a) and the other main surface (24) of the semiconductor substrate (10) or the third semiconductor region (14). The third semiconductor region (14 or 14a) and the fourth semiconductor region (14 or 14a) are arranged in a semiconductor region (14a).
The semiconductor region (15 or 15a) is disposed inside the first semiconductor region (11) when viewed in plan, and the first electrode (21) is provided on one main surface of the semiconductor substrate (10). (18) and electrically connected to the first semiconductor region (11); the second electrode (25) is disposed on the other main surface (24) of the semiconductor substrate (10); A semiconductor device which is electrically connected to the fourth semiconductor region (15 or 15a) directly or via the semiconductor region. 2. The semiconductor device according to claim 1, further comprising: a field limiting ring region disposed so as to surround the first semiconductor region, wherein the field limiting ring region includes a first region. The field limiting ring region having one conductivity type and arranged in an island shape in the second semiconductor region;
The shortest distance (L2) between the first semiconductor region (11) and the third semiconductor region (14 or 14a) is
Shortest distance (L1) to the semiconductor region (14 or 14a)
2. The semiconductor device according to claim 1, wherein said semiconductor device is longer than said semiconductor device. 3. A field plate (21a) is provided on the surface of the second semiconductor region (13) so as to oppose the insulating film (19). Item 2. The semiconductor device according to item 1. 4. A semiconductor device according to claim 1, further comprising a fifth semiconductor region of a second conductivity type, wherein said fifth semiconductor region has a higher impurity concentration than said fourth semiconductor region. The third and fourth semiconductor regions (14) are arranged so as to be exposed on the other main surface (24) of the semiconductor substrate (10) and have a depth based on the other main surface (24). , 1
5), the second electrode (25) is formed to be shallower than the fifth semiconductor region (1).
3. The method according to claim 1, further comprising the steps of:
Or the semiconductor device according to 3. 5. The fourth semiconductor region (15a) is disposed in the third semiconductor region (14a), and further includes a second semiconductor type fifth semiconductor region (16a). The fifth semiconductor region (16a) has a degree of impurity of the second semiconductor region (13) and the third semiconductor region (14).
a) being disposed so as to be exposed to the other main surface (24) of the semiconductor substrate (10) with an impurity concentration between the second electrode (25) and the fifth electrode (25). Semiconductor region (16
3. The method according to claim 1, wherein the connection is made to a).
Or the semiconductor device according to 3. 6. The first semiconductor region (11) further comprising an emitter region (12) and an emitter electrode (23).
Is a base region, the second, third and fourth semiconductor regions (13, 14, 15) are collector regions, the first electrode (21) is a base electrode, and the second electrode 4. The method according to claim 1, wherein (25) is a collector electrode.
Or the semiconductor device according to 4 or 5.