JP2000312002A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase the withstand voltage and reduce the on-resistance. SOLUTION: The semiconductor device according to the present invention includes a gate electrode 7 formed on a gate insulating film 6 of a P-type semiconductor substrate 1;
A P-type body region 3 formed adjacent to the gate electrode 7; an N-type source region 4 and a channel region 8 formed in the P-type body region 3; And a drift region (N−) formed at a position which is shallow at least under the gate electrode 7 and deep near the drain region 5 from the channel region 8 to the drain region 5. Layer 22), the P-type body region 3 extends below the first N − layer 22A formed shallowly below the gate electrode 7, and the first shallowly formed first region 22A in that region. Body region 3A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an LD (Lateral Double) as a high-voltage element used in, for example, a liquid crystal driving IC.
Diffused) MOS transistor technology.

[0002]

2. Description of the Related Art Here, the LDMOS transistor structure means that a diffusion region formed on the surface side of a semiconductor substrate is diffused with an impurity having a different conductivity type to form a new diffusion region. The difference in the lateral diffusion is used as the effective channel length. By forming a short channel, the element is suitable for low on-resistance.

FIG. 8 is a cross-sectional view for explaining a conventional LDMOS transistor, and shows an N-channel type LDMOS transistor structure as an example.
Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type.

In FIG. 8, reference numeral 1 denotes a first conductivity type, for example, P
A semiconductor substrate 2 of a second conductivity type, for example, an N-type well region, and a P-type body region 3 in the N-type well region 2;
Are formed, and N is formed in the P-type body region 3.
A type diffusion region 4 is formed, and an N type diffusion region 5 is formed in the N type well region 2. A gate electrode 7 is formed on the surface of the substrate with a gate insulating film 6 interposed therebetween, and a channel region 8 is formed in a surface region of the P-type body region 3 immediately below the gate electrode 7.

The N-type diffusion region 4 is a source region, the N-type diffusion region 5 is a drain region, and the N-type well region 2 below the LOCOS oxide film 9 is a drift region. Reference numerals 10 and 11 denote a source electrode and a drain electrode, respectively, reference numeral 12 denotes a P-type diffusion region for taking the potential of the P-type body region 3, and reference numeral 13 denotes an interlayer insulating film.

In the above LDMOS transistor,
By forming the N-type well region 2 by diffusion, the concentration on the surface of the N-type well region 2 is increased, so that the current easily flows on the surface of the N-type well region 2 and the breakdown voltage can be increased. The LDMOS transistor having such a configuration is called a surface relaxation type (RESURF) LDMOS, and the dopant concentration of the drift region of the N-type well region 2 is set so as to satisfy the RESURF condition. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

[0007]

However, for example, in a vehicle-mounted IC, a high breakdown voltage MOS transistor is often used as a high-side switch in a circuit (H-bridge circuit) used for motor control. In the LDMOS transistor on the semiconductor substrate, there is a problem that the LDMOS transistor cannot be used as a high-side switch because the source region is not separated from the P substrate.

In order to use the LDMOS transistor as a high-side switch, an NMOS transistor is required to cover the P-type body region 3 of the LDMOS transistor.
The mold well region 2 had to be formed.

In this case, it is necessary to increase the concentration of the N-type well region 2, which causes a problem that the breakdown voltage is reduced. A technique using such an LDMOS transistor as a high-side switch is disclosed in Japanese Patent Application Laid-Open No. 5-198757.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can meet the demand for reducing the on-resistance without deteriorating the high breakdown voltage.

[0011]

In order to solve the above-mentioned problems, the present invention provides an N-type well region 2 formed in a P-type semiconductor substrate 1, for example, as shown in FIG. 1. Gate electrode 7 formed on gate insulating film 6 on
And an N-type drain region 5 separated from the gate electrode 7; and the drain region 5;
An N-type drift region (N− layer 22) formed shallow below and deep near the drain region 5, formed adjacent to the gate electrode 7,
It extends to below the first N − layer 22A formed shallow below and is shallow in that region (first body region 3A).
A P-type body region 3 formed and deeply formed on the source region side (second P-type body region 3B), an N-type source region 4 and a channel region 8 formed in the P-type body region 3 And a first N- layer 22A formed shallowly below the gate electrode 7;
With the first body region 3A formed shallowly below 2A,
It is characterized by being completely depleted.

Further, the manufacturing method is to form an N- layer 22 which will become a drift region through a post-process in an N-type well region 2 in a P-type semiconductor substrate 1 as shown in FIG. , Two types of second conductivity type impurities are ion-implanted. Next, as shown in FIG. 2B, a certain region on the substrate 1 is selectively oxidized to form a LOCOS oxide film 9, and
From the difference between the diffusion coefficients of the various N-type impurities,
A first N-layer 22A and a second N-layer 22B are respectively provided on a relatively surface layer and a relatively deep position in the mold well region 2.
To form Subsequently, as shown in FIG. 3A, a photoresist film 3 formed on the substrate 1 on the drain formation region is formed.
N-layer 22 is formed by ion-implanting and diffusing a P-type impurity into the surface layer of the substrate in the source forming region by using the mask 9 as a mask so as to be shallow under the gate electrode forming region and deep near the drain forming region. At the same time, a shallow, low-concentration P-type layer
Of the body region 3A. ) Is formed. Further, FIG.
As shown in (b), a gate insulating film 6 is formed on the substrate 1 and the LOCOS oxide film 9 is formed from the gate insulating film 6.
The gate electrode 7 is formed so as to straddle the upper part. Next, as shown in FIG. 4A, a P-type impurity is implanted and diffused using the photoresist film 40 formed so as to cover the gate electrode 7 and the drain formation region, thereby diffusing the gate electrode 7 into the gate electrode 7. A first body region 3 which is formed to be adjacent to and extends below the first N- layer 22A formed shallowly below the gate electrode 7 and which is shallow in that region.
A P-type body region 3 constituting A is formed. continue,
As shown in FIG. 4B, N-type impurities are implanted by using photoresist films 41 and 44 having openings on the source formation region and the drain formation region formed in the P-type body region 3 as a mask. Forming the drain regions 4 and 5.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining an LDMOS transistor of the present invention, and shows an N-channel type LDMOS transistor structure as an example.
Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type. The same components as those in the conventional configuration are denoted by the same reference numerals, and the description will be simplified.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate of a first conductivity type, for example, a P-type. Reference numeral 21 denotes a second conductivity type, for example, an N-type well region. At the same time, a P-type body region 3 is formed.
An N-type diffusion region 4 is formed in the P-type body region 3, and an N-type diffusion region 5 is formed in the N− layer 22. A gate electrode 7 is formed on the surface of the substrate with a gate insulating film 6 interposed therebetween, and a channel region 8 is formed in a surface region of the P-type body region 3 immediately below the gate electrode 7.

The N-type diffusion region 4 is a source region, the N-type diffusion region 5 is a drain region, and the N− layer 22 under the LOCOS oxide film 9 is a drift region. still,
The N − layer 22 as a drift region is formed shallowly below the gate electrode 7 (first N − layer 22A) and deeply near the drain region 5 (second N − layer 22B).

Although not shown in the drawings, a source electrode 10 and a drain electrode 11 are formed so as to contact the N-type diffusion regions 4 and 5 as in the conventional structure.
A P-type diffusion region 12 for taking the potential of the P-type body region 3 is formed adjacent to the D-type diffusion region 4, and is covered with an interlayer insulating film 13.

A feature of the present invention is that the P-type body region 3
In the N− layer 22, the gate electrode 7 extends below the N− layer 22A formed shallowly below the gate electrode 7, and is formed shallow (first body region 3A) in that region, and formed on the source region side. It is formed deep (second body region 3B). By forming the shallow first body region 3A so as to extend below the N- layer 22A, complete depletion can be achieved in the PN junction region.
The on-resistance can be reduced by the so-called RESURF effect.

Further, in the semiconductor device of the present invention, the N- layer 22 is formed in the N-type well region 21 and the N- layer 22 is formed.
Is shallow below the gate electrode 7 (first N− layer 22A),
Since it is formed deep (the second N− layer 22B) in the vicinity of the drain region 5, the RESURF is further increased as compared with the conventional device.
The effect is obtained, and the concentration of the first N − layer 22A formed shallowly below the gate electrode 7 is formed to be high, so that the on-resistance becomes small, the current easily flows, and the vicinity of the drain region 5 (drift) 2nd N-layer 2 in area position)
Since the concentration of 2B is formed to be low, the depletion layer is easily expanded, and high breakdown voltage can be achieved (see the concentration distribution diagram shown in FIG. 6). Note that the N-channel LDMOS transistor of the present embodiment has a withstand voltage of about 30 V.

Hereinafter, a method of manufacturing the above-described semiconductor device will be described with reference to the drawings.

In FIG. 2A, after a pad oxide film 30 is formed on a P-type semiconductor substrate 1, a P-type well region 2 is formed.
1. Two types of N for forming an N− layer 22 which will be a drift region in a later process using the photoresist film 31 as a mask
First and second ion-implanted layers 32 and 33 are formed by implanting type impurities (for example, arsenic ions and phosphorus ions). In this step, for example, the arsenic ion is reduced to about 1
At an acceleration voltage of 60 KeV, an implantation amount of 3 × 10 ¹² / cm ² is implanted, and phosphorus ions are implanted at an acceleration voltage of approximately 50 KeV under an implantation condition of 4 × 10 ¹² / cm ² .

Next, in FIG. 2B, a certain region on the surface of the substrate is selectively oxidized by using the silicon nitride film 34 formed on the substrate 1 as a mask to form a LOCOS oxide film 9 having a thickness of about 7300 °. And the difference between the diffusion coefficients of arsenic ions and phosphorus ions implanted in the surface layer of the substrate as described above.
The first N- layer 22A is diffused inside and relatively on the surface of the substrate.
Is formed, and the phosphorus ions are diffused into the substrate 1 to form a second N− layer 22 </ b> B at a relatively deep position in the P-type well region 21.

Subsequently, in FIG. 3A, after a photoresist film 39 is formed on the substrate 1 on the drain formation region, a P-type impurity is formed on the surface of the substrate in the source formation region by using the photoresist film 39 as a mask. By implanting and diffusing (for example, boron ions), phosphorus ions constituting the second N− layer 22B located in a relatively deep region of the substrate 1 on the source forming region side are converted to boron ions. Try to negate. At this time, by implanting the boron ions more than at least canceling out the phosphorus ions constituting the second N− layer 22B, the second N− layer 22B on the source forming region side is extinguished, A low-concentration P-type layer (first body region 3A described later) is formed. In this step, for example, boron ions are accelerated to about 8 × 10 ¹² / c at an acceleration voltage of about 80 KeV.
After the injection at an injection amount of m ² , thermal diffusion is performed at about 1100 ° C. for 2 hours. Here, FIG. 6 is a diagram showing impurity concentration distributions when the arsenic ions (shown by solid lines), phosphorus ions (shown by dotted lines), and boron ions (shown by dashed lines) are respectively diffused. However, the concentration distribution of the substrate using phosphorus ions as a parent is canceled by the concentration distribution using boron ions as a parent, and a concentration distribution mainly containing boron ions remains.

As described above, according to the present invention, when forming the drift region, the difference between the diffusion coefficients of arsenic ions and phosphorus ions having different diffusion coefficients is utilized to form the second N formed deep in the substrate near the source formation region. The layer 22B is offset by diffusing boron ions implanted in a later step, and the first N− layer 2 formed on the surface of the substrate is formed on the source forming region side.
Only 2A remains, and a semiconductor device with reduced on-resistance can be provided by a relatively simple manufacturing process.

Next, referring to FIG.
The gate insulating film 6 having a thickness of about 800
A polysilicon film (amorphous film)
A silicon film may be used. ), This policy
For example, POCl _ThreeLind with heat diffusion source
After the gate insulating film has been made conductive by
6 so as to extend over the LOCOS oxide film 9.
The contact electrode 7 is formed.

Subsequently, in FIG. 4A, a P-type impurity (for example, boron ion) is implanted and diffused using the photoresist film 40 formed so as to cover the gate electrode 7A and the drain formation region as a mask. Then, a P-type body region 3 is formed adjacent to one end of the gate electrode 7. In this step, for example, boron ions are implanted at an acceleration voltage of about 40 KeV at an implantation amount of 5 × 10 ¹³ / cm ² , and then thermally diffused at about 1050 ° C. for 2 hours. At this time, the P-type body region 3 is superimposed with the low-concentration P-type layer (the first body region 3A), so that the shallow first body region 3A and the source region side below the N− layer 22A. Then deep second body area 3
B.

As described above, in the present invention, by forming the first body region 3A which is shallow so as to extend below the N- layer 22A, a complete depletion layer can be achieved in this PN junction region.
Low on-resistance can be achieved by the so-called RESURF effect.

4 (b) and 5 (a), an N-type photoresist film having openings on the source formation region and the drain formation region formed in the P-type body region 3 is used as a mask. N-type diffusion regions 4 and 5 serving as source / drain regions are formed by implanting impurities. In this step, for example, when a source / drain region having a so-called LDD structure is formed, a photoresist film 41 having an opening 41a on the source formation region is used as a mask, for example, phosphorous ions are accelerated at an acceleration voltage of about 40 KeV. After the implantation at a dose of 0.5 × 10 ¹³ / cm ² (low-concentration N-type diffusion region 4A), a sidewall spacer film 43 is formed on the side wall of the gate electrode 7 as shown in FIG. Then, using the photoresist film 44 as a mask,
For example, an arsenic ion is charged at an accelerating voltage of about 80 KeV for 5
The implantation is performed at an implantation amount of × 10 ¹⁵ / cm ² (high-concentration N-type diffusion regions 4B and 5B). In this embodiment, it goes without saying that the source / drain regions are not limited to the LDD structure.

In FIG. 5B, a photoresist is formed to form a P-type diffusion region 12 formed at a position adjacent to the N-type diffusion region 4 in order to take the potential of the P-type body region 3. Using the film 38 as a mask, a P-type impurity (for example, boron difluoride ion) is
A mold diffusion region 12 is formed. In this step, for example,
Boron difluoride ions are implanted at an acceleration voltage of about 60 KeV and at a dose of 4 × 10 ¹⁵ / cm ² .

Hereinafter, similarly to the conventional configuration, the source electrode 10,
After the formation of the drain electrode 11, the interlayer insulating film 13 is formed to complete the semiconductor device.

FIG. 7 is an equivalent circuit diagram showing a circuit configuration using the N-type LDMOS transistor as a high-side switch.
The gate of the (low-side switch) is fixed to a fixed voltage B, the signal A is input to the gate of the N-type LDMOS transistor Q2 (high-side switch), and the input signal is output from the output terminal C. Has become.

As described above, in the present invention, in the N-layer 22 serving as a drift region formed in the N-type well 2, the first body shallower below the N-layer 22A formed below the gate electrode 7 is formed. By forming the region 3A, a complete depletion layer can be achieved in the PN junction region, so-called RESU.
Low on-resistance can be achieved by the RF effect. Therefore, a high-side switch with low on-resistance can be provided.

[0033]

According to the present invention, of the N- layer 22 as a drift region formed in the N-type well 2, the first body region shallow under the N- layer 22A formed shallow under the gate electrode 7. By forming 3A, a complete depletion layer can be achieved in this PN junction region, and low on-resistance can be achieved by the so-called RESURF effect.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a concentration distribution diagram of various ions for explaining the principle of forming a drift region according to the present invention.

FIG. 7 is an equivalent circuit diagram showing a circuit configuration using the semiconductor device of the present invention as a high-side switch.

FIG. 8 is a sectional view showing a conventional semiconductor device.

Claims (5)

[Claims] 1. A gate electrode formed on a gate insulating film of a semiconductor substrate of a first conductivity type, a first conductivity type body region formed adjacent to the gate electrode, and the first conductivity type body. A source region and a channel region of the second conductivity type formed in the region, a drain region of the second conductivity type formed at a position separated from the body region of the first conductivity type, and the drain region from the channel region. A semiconductor device having a second conductivity type drift region formed at least shallow under the gate electrode and deep near the drain region, wherein the first conductivity type body region is formed shallow under the gate electrode. A semiconductor device extending below the second conductivity type drift region and formed shallow in that region. 2. A second conductivity type well region formed in a semiconductor substrate of a first conductivity type, a gate electrode formed on a gate insulating film on the substrate, and a second electrode separated from the gate electrode. A drain region of a conductivity type, including the drain region, shallow under the gate electrode,
A second conductive type drift region formed deep in the vicinity of the drain region; and a second conductive type drift region formed adjacent to the gate electrode and formed shallowly below the gate electrode. And a shallowly formed first
A semiconductor device comprising: a conductive type body region; a second conductive type source region and a channel region formed in the first conductive type body region. 3. The semiconductor device according to claim 2, wherein said second gate electrode is formed shallowly below said gate electrode.
3. The semiconductor device according to claim 1, wherein the drift region of the conductivity type and the body region of the first conductivity type formed shallowly below the drift region are completely depleted. 4. A method for forming a low-concentration second conductivity type layer that becomes a drift region through a post-process in a second conductivity type well region in a semiconductor substrate of a first conductivity type. A step of ion-implanting impurities; a step of selectively oxidizing a certain region on the substrate to form a LOCOS oxide film; and a step of forming the first conductivity type well region based on a difference in diffusion coefficient between the two types of second conductivity type impurities. Forming a low-concentration second-conductivity-type layer at each of a relatively deep position in the substrate and a relatively-surface-layer of the substrate; and When the first conductivity type impurity is ion-implanted and diffused into the substrate surface layer, the second conductivity type drift region is formed so as to be shallow below the gate electrode formation region and deeper near the drain formation region. Forming a shallow, low-concentration first conductivity type layer in the vicinity of a region under the gate electrode formation region; forming a gate insulating film on the substrate; and forming a gate electrode over the LOCOS oxide film from the gate insulating film. Forming a first conductive type impurity by using a photoresist film formed so as to cover the gate electrode and the drain formation region as a mask, and diffusing the first conductive type impurity to form a region adjacent to the gate electrode, and Forming a first-conductivity-type body region extending below and below the second-conductivity-type drift region formed shallowly below the gate electrode, and forming the first-conductivity-type body region in that region; Using a photoresist film having openings on the source formation region and the drain formation region as a mask, a second conductivity type impurity is implanted to form source / drain regions. The method of manufacturing a semiconductor device characterized by a step. 5. The semiconductor device according to claim 2, wherein said second gate electrode is formed shallowly below said gate electrode.
5. The method according to claim 4, wherein the junction region is completely depleted by forming a shallow first conductivity type body region below the conductivity type drift region.