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JP2000307398A - Protection circuit for semiconductor switch device - Google Patents

Protection circuit for semiconductor switch device

Info

Publication number
JP2000307398A
JP2000307398A JP11116452A JP11645299A JP2000307398A JP 2000307398 A JP2000307398 A JP 2000307398A JP 11116452 A JP11116452 A JP 11116452A JP 11645299 A JP11645299 A JP 11645299A JP 2000307398 A JP2000307398 A JP 2000307398A
Authority
JP
Japan
Prior art keywords
voltage
power mosfet
semiconductor switch
switching element
protection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11116452A
Other languages
Japanese (ja)
Inventor
Yosuke Hagiwara
洋右 萩原
Shigeo Akiyama
茂夫 秋山
Masahiko Suzumura
正彦 鈴村
Kazuyuki Tomii
和志 富井
Takeshi Nobe
武 野辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP11116452A priority Critical patent/JP2000307398A/en
Publication of JP2000307398A publication Critical patent/JP2000307398A/en
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electronic Switches (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent thermal destruction of a semiconductor switch element that is a component of a semiconductor switch device. SOLUTION: A protection circuit 1 consists of a current sensor resistor 2 that is connected between the source of a power MOSFET 14 and one output terminal 15b and an npn gate control transistor(TR) 3 that becomes conductive when the voltage drop across the current sensor resistor 2 exceeds a given voltage. Since the current sensing resistor 2 has a positive temperature coefficient, the resistance of the current sensor resistor 2 increases as the temperature rises and the voltage applied between the base and an emitter of the gate control TR 3 also increases. Consequently, the gate voltage of the power MOSFET 14 decreases to suppress the drain current. Since the power consumption of the power MOSFET 14 is reduced, the drain breakdown voltage can be made higher so as to prevent thermal destruction of the power MOSFET 14.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、制御信号に応じて
オンオフするパワーMOSFETやIGBTのような半
導体スイッチング素子により出力端間を導通状態と非導
通状態に切り換える半導体スイッチ装置の保護回路に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a semiconductor switch device in which the output terminals are switched between a conductive state and a non-conductive state by a semiconductor switching element such as a power MOSFET or an IGBT which is turned on / off in response to a control signal. is there.

【0002】[0002]

【従来の技術】従来より、この種の半導体スイッチ装置
10’としては、図3に示すように制御入力により点灯
・消灯する発光ダイオード11と、発光ダイオード11
に対置され発光ダイオード11の光を受光して光起電力
を発生する太陽電池のような光起電力素子12と、出力
端子15a,15bを導通状態と非導通状態に切り換え
る半導体スイッチング素子(パワーMOSFET)14
と、光起電力素子12で発生する光起電力に応じてパワ
ーMOSFET14のゲート電圧を制御する制御回路1
3とを備え、発光ダイオード11が形成されたチップ1
6aと、光起電力素子12、制御回路13及び後述する
保護回路1’が形成されたチップ16bと、パワーMO
SFET14が形成されたチップ16cとが一つのパッ
ケージに実装された、所謂フォトモスリレーと呼ばれる
半導体リレーがある。ここで、パワーMOSFET14
はエンハンスメント型(ノーマリ・オフ型)であって、
ゲート電圧が零の時はドレイン電流が流れずオフ状態で
ある。また、制御回路13はパワーMOSFET14が
ターンオフする際に、パワーMOSFET14のゲート
静電容量に蓄積された残留電荷を短時間で放電させる機
能を有するものであり、パワーMOSFET14のター
ンオフに要する時間を短縮するのである。なお、光起電
力素子12の光起電力が印加された時には、制御回路1
3の出力端間が高インピーダンス状態となり、パワーM
OSFET14のゲート静電容量が効率良く充電され
る。
2. Description of the Related Art Conventionally, as a semiconductor switch device 10 'of this type, a light emitting diode 11 which is turned on / off by a control input as shown in FIG.
A photovoltaic element 12 such as a solar cell that receives light from the light emitting diode 11 and generates photovoltaic power, and a semiconductor switching element (power MOSFET) that switches the output terminals 15a and 15b between a conductive state and a non-conductive state. ) 14
And a control circuit 1 for controlling a gate voltage of the power MOSFET 14 according to a photovoltaic voltage generated by the photovoltaic element 12.
And a chip 1 on which the light emitting diode 11 is formed.
6a, a chip 16b on which a photovoltaic element 12, a control circuit 13 and a protection circuit 1 'described later are formed, and a power MO
There is a semiconductor relay called a so-called photo MOS relay in which a chip 16c on which the SFET 14 is formed is mounted in one package. Here, the power MOSFET 14
Is an enhancement type (normally-off type),
When the gate voltage is zero, the drain current does not flow and the device is off. The control circuit 13 has a function of discharging the residual charge accumulated in the gate capacitance of the power MOSFET 14 in a short time when the power MOSFET 14 is turned off, and shortens the time required for turning off the power MOSFET 14. It is. When the photovoltaic power of the photovoltaic element 12 is applied, the control circuit 1
3 is in a high impedance state between the output terminals, and the power M
The gate capacitance of the OSFET 14 is charged efficiently.

【0003】このような半導体スイッチ装置10’にお
いては、パワーMOSFET14のドレイン・ソース間
に過大な電流が通電されるとパワーMOSFET14が
破壊されるから、パワーMOSFET14の破壊を防止
するようにパワーMOSFET14のドレイン・ソース
間の電流を制限することが要求されている。そこで、パ
ワーMOSFET14のドレイン・ソース間の電流を制
限する保護回路1’として、パワーMOSFET14の
ソースと一方の出力端子15bとの間に接続される電流
検出抵抗2’と、電流検出抵抗2’に生じる電圧降下が
所定電圧以上になるとオンになるnpn形のゲート制御
用トランジスタ3を備えたものが提案されている。ここ
で、ゲート制御用トランジスタ3は、ベース・エミッタ
間に電流検出抵抗2’が接続され、コレクタがパワーM
OSFET14のゲートに接続されている。したがっ
て、負荷の短絡等が原因でパワーMOSFET14のド
レインに過大な電圧が印加されると、電流検出抵抗2’
の両端電圧が上昇してゲート制御用トランジスタ3がオ
ンになり、パワーMOSFET14のゲート・ソース間
電圧を一定値まで低下させるので、パワーMOSFET
14が保護されるのである。すなわち、パワーMOSF
ET14は、ゲート・ソース間電圧が低い領域では、ド
レイン・ソース間電流を制限するから、図4に示すよう
に保護回路1’の働きでドレイン電流Idsが一定値に
抑制されてパワーMOSFET14を保護することがで
きるのである。
In such a semiconductor switch device 10 ′, if an excessive current is applied between the drain and the source of the power MOSFET 14, the power MOSFET 14 is destroyed. It is required to limit the drain-source current. Therefore, as a protection circuit 1 'for limiting the current between the drain and source of the power MOSFET 14, a current detection resistor 2' connected between the source of the power MOSFET 14 and one output terminal 15b and a current detection resistor 2 ' A device having an npn-type gate control transistor 3 that is turned on when a generated voltage drop exceeds a predetermined voltage has been proposed. Here, in the gate control transistor 3, the current detection resistor 2 'is connected between the base and the emitter, and the collector is the power M.
It is connected to the gate of OSFET14. Therefore, when an excessive voltage is applied to the drain of the power MOSFET 14 due to a load short circuit or the like, the current detection resistor 2 ′
, The gate control transistor 3 is turned on, and the gate-source voltage of the power MOSFET 14 is reduced to a constant value.
14 is protected. That is, the power MOSF
Since the ET 14 limits the drain-source current in a region where the gate-source voltage is low, the protection circuit 1 ′ protects the power MOSFET 14 by suppressing the drain current Ids to a constant value as shown in FIG. You can do it.

【0004】[0004]

【発明が解決しようとする課題】上述のように保護回路
1’を設けることで半導体スイッチ装置10のパワーM
OSFET14のドレイン電圧耐量を向上することがで
きるが、ドレイン電圧Vdsが高くなった場合にはパワ
ーMOSFET14で消費される電力(=ドレイン・ソ
ース間電圧Vds×ドレイン電流Ids)が増大するた
め、最終的には素子自体の発熱によってパワーMOSF
ET14が熱的に破壊されてしまう虞がある。また、保
護回路1’を構成する電流検出抵抗2’は、チップ16
bの半導体基板表面に不純物を拡散することにより形成
された拡散抵抗であるため、その抵抗値は負の温度係数
を有している。つまり、パワーMOSFET14の発熱
で温度が上昇するにつれて電流検出抵抗2’の抵抗値が
減少し、電流検出抵抗2’の両端電圧が低下するので、
ゲート制御用トランジスタ3のベース・エミッタ間に印
加される電圧が低下してしまう。その結果、パワーMO
SFET14のゲート電圧が上昇するため、ドレイン電
流Idsが増加してさらに消費電力の増大を招いてしま
い、パワーMOSFET14が熱的に破壊しやすくなっ
てしまう。
By providing the protection circuit 1 'as described above, the power M of the semiconductor switch device 10 is increased.
Although the withstand voltage of the drain voltage of the OSFET 14 can be improved, the power consumed by the power MOSFET 14 (= drain-source voltage Vds × drain current Ids) increases when the drain voltage Vds increases. Power MOSF due to heat generation of the element itself
The ET 14 may be thermally destroyed. Further, the current detection resistor 2 ′ constituting the protection circuit 1 ′ is connected to the chip 16.
Since the diffusion resistance is a diffusion resistance formed by diffusing impurities into the semiconductor substrate surface b, the resistance value has a negative temperature coefficient. That is, as the temperature rises due to the heat generated by the power MOSFET 14, the resistance value of the current detection resistor 2 'decreases, and the voltage across the current detection resistor 2' decreases.
The voltage applied between the base and the emitter of the gate control transistor 3 decreases. As a result, the power MO
Since the gate voltage of the SFET 14 increases, the drain current Ids increases, further increasing the power consumption, and the power MOSFET 14 is easily damaged thermally.

【0005】本発明は上記事情に鑑みて為されたもので
あり、その目的とするところは、半導体スイッチ装置を
構成する半導体スイッチング素子の熱的破壊を防止する
ことができる半導体スイッチ装置の保護回路を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a protection circuit for a semiconductor switch device that can prevent thermal destruction of a semiconductor switching element included in the semiconductor switch device. Is to provide.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、制御入力に応じてオンオフする半導体ス
イッチング素子により出力端間を導通状態と非導通状態
に切り換える半導体スイッチ装置の保護回路において、
半導体スイッチング素子の一端と一方の出力端との間に
接続される電流検出抵抗と、電流検出抵抗に生じる電圧
降下に応じて半導体スイッチング素子のゲート電位を制
御するゲート制御用トランジスタとを備え、電流検出抵
抗として正の温度係数を有する抵抗を用いたことを特徴
とし、半導体スイッチング素子に過大な電圧が印加され
て素子温度が上昇した場合に、電流検出抵抗に生じる電
圧降下が増大することでゲート制御用トランジスタによ
り半導体スイッチング素子のゲート電位が低下するか
ら、半導体スイッチング素子に流れる電流を抑制するこ
とができる。その結果、オン時の過大な電圧印加に対し
て半導体スイッチング素子が熱的に破壊しない最大の電
圧を高くすることができ、半導体スイッチング素子の熱
的破壊を防止することができる。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a protection circuit for a semiconductor switch device in which a semiconductor switching element that is turned on and off in response to a control input switches between a conductive state and a non-conductive state between output terminals. At
A current detection resistor connected between one end of the semiconductor switching element and one output terminal; and a gate control transistor for controlling a gate potential of the semiconductor switching element in accordance with a voltage drop generated in the current detection resistor, It is characterized by using a resistor with a positive temperature coefficient as the detection resistor, and when an excessive voltage is applied to the semiconductor switching element and the element temperature rises, the voltage drop that occurs in the current detection resistor increases, thereby increasing the gate. Since the gate potential of the semiconductor switching element is reduced by the control transistor, the current flowing through the semiconductor switching element can be suppressed. As a result, it is possible to increase the maximum voltage at which the semiconductor switching element does not thermally break down when an excessive voltage is applied at the time of ON, and it is possible to prevent the semiconductor switching element from being thermally broken.

【0007】[0007]

【発明の実施の形態】以下、図面を参照して本発明の一
実施形態を詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

【0008】図1は本実施形態の保護回路1を備えた半
導体スイッチ装置10の概略回路図である。但し、半導
体スイッチ装置10の構成は従来技術で説明したものと
共通であるから、同一の符号を付して説明を省略する。
FIG. 1 is a schematic circuit diagram of a semiconductor switch device 10 including a protection circuit 1 according to the present embodiment. However, since the configuration of the semiconductor switch device 10 is common to that described in the related art, the same reference numerals are given and the description is omitted.

【0009】保護回路1は、パワーMOSFET14の
ソースと一方の出力端子15bとの間に接続される電流
検出抵抗2と、電流検出抵抗2に生じる電圧降下が所定
電圧以上になるとオンになるnpn形のゲート制御用ト
ランジスタ3とで構成されている。ここで、電流検出抵
抗2は半導体プロセスで用いられる金属材料(例えば、
Al,Cu,W,Mo.Ti等)から形成され、正の温
度係数を有するものである。なお、この電流検出抵抗2
は、光起電力素子12や制御回路13とともにチップ1
6bに形成してもよいし、パワーMOSFET14とと
もにチップ16cに形成してもよい。
The protection circuit 1 comprises a current detection resistor 2 connected between the source of the power MOSFET 14 and one of the output terminals 15b, and an npn-type transistor which is turned on when a voltage drop across the current detection resistor 2 exceeds a predetermined voltage. And the gate control transistor 3. Here, the current detection resistor 2 is made of a metal material (for example,
Al, Cu, W, Mo. Ti) and has a positive temperature coefficient. Note that this current detection resistor 2
Is the chip 1 together with the photovoltaic element 12 and the control circuit 13.
6b, or may be formed on the chip 16c together with the power MOSFET 14.

【0010】本実施形態の保護回路1の動作を説明す
る。負荷の短絡等が原因でパワーMOSFET14のド
レインに過大な電圧が印加されると、電流検出抵抗2の
両端電圧が上昇してゲート制御用トランジスタ3がオン
になり、パワーMOSFET14のゲート・ソース間電
圧を一定値まで低下させてパワーMOSFET14を保
護する。しかも、電流検出抵抗2が正の温度係数を有す
るので、パワーMOSFET14の発熱で温度が上昇す
るにつれて電流検出抵抗2の抵抗値が増加し、電流検出
抵抗2の両端電圧が上昇する。そして、電流検出抵抗2
の両端電圧が上昇すれば、ゲート制御用トランジスタ3
のベース・エミッタ間に印加される電圧も上昇するの
で、パワーMOSFET14のゲート電圧が低下して、
図2に示すようにドレイン電流Idsを抑制することが
できる。その結果、パワーMOSFET14の消費電力
が低減されるので、パワーMOSFET14のドレイン
電圧耐量(オン時の過大なドレイン電圧の印加に対して
半導体スイッチング素子が熱的に破壊しない最大のドレ
イン電圧)Vds1を、図2に示すように従来例のドレイ
ン電圧耐量Vds2よりも高くすることができて、パワー
MOSFET14の熱的破壊を防止することができる
(ここで、図2はパワーMOSFET14の電流−電圧
特性を表している)。
The operation of the protection circuit 1 according to this embodiment will be described. When an excessive voltage is applied to the drain of the power MOSFET 14 due to a load short circuit or the like, the voltage between both ends of the current detection resistor 2 rises and the gate control transistor 3 is turned on, and the gate-source voltage of the power MOSFET 14 Is reduced to a certain value to protect the power MOSFET 14. Moreover, since the current detection resistor 2 has a positive temperature coefficient, the resistance value of the current detection resistor 2 increases as the temperature rises due to the heat generated by the power MOSFET 14, and the voltage across the current detection resistor 2 increases. And the current detection resistor 2
Of the gate control transistor 3
Since the voltage applied between the base and the emitter of the power MOSFET 14 also increases, the gate voltage of the power MOSFET 14 decreases,
As shown in FIG. 2, the drain current Ids can be suppressed. As a result, since the power consumption of the power MOSFET 14 is reduced, the drain voltage tolerance (the maximum drain voltage at which the semiconductor switching element does not thermally break down when an excessive drain voltage is applied at the time of ON) Vds1 of the power MOSFET 14 is calculated. As shown in FIG. 2, the drain voltage tolerance Vds2 of the conventional example can be made higher to prevent thermal destruction of the power MOSFET 14 (here, FIG. 2 shows the current-voltage characteristics of the power MOSFET 14). ing).

【0011】なお、半導体スイッチ装置10を構成する
半導体スイッチング素子として、本実施形態のパワーM
OSFET14の代わりに他のパワーデバイス、例えば
IGBTが用いられている場合でも同様の効果を奏す
る。
The semiconductor switching device constituting the semiconductor switch device 10 has a power M of this embodiment.
The same effect is obtained even when another power device, for example, an IGBT is used instead of the OSFET 14.

【0012】[0012]

【発明の効果】本発明は上述のように、半導体スイッチ
ング素子の一端と一方の出力端との間に接続される電流
検出抵抗と、電流検出抵抗に生じる電圧降下に応じて半
導体スイッチング素子のゲート電位を制御するゲート制
御用トランジスタとを備え、電流検出抵抗として正の温
度係数を有する抵抗を用いたので、半導体スイッチング
素子に過大な電圧が印加されて素子温度が上昇した場合
に、電流検出抵抗に生じる電圧降下が増大することでゲ
ート制御用トランジスタにより半導体スイッチング素子
のゲート電位が低下するから、半導体スイッチング素子
に流れる電流を抑制することができ、その結果、オン時
の過大な電圧の印加に対して半導体スイッチング素子が
熱的に破壊しない最大の電圧を高くすることができて、
半導体スイッチング素子の熱的破壊を防止することがで
きるという効果がある。
As described above, according to the present invention, a current detecting resistor connected between one end of a semiconductor switching element and one output terminal, and a gate of the semiconductor switching element in response to a voltage drop generated in the current detecting resistor. A gate control transistor for controlling the potential, and a resistor having a positive temperature coefficient is used as the current detection resistor. Therefore, when an excessive voltage is applied to the semiconductor switching element and the element temperature rises, the current detection resistor is used. Since the gate potential of the semiconductor switching element is reduced by the gate control transistor due to the increase in the voltage drop that occurs in the semiconductor switching element, the current flowing through the semiconductor switching element can be suppressed. On the other hand, the maximum voltage at which the semiconductor switching element does not thermally break can be increased,
There is an effect that thermal destruction of the semiconductor switching element can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態を含む半導体スイッチ回路の
概略回路図である。
FIG. 1 is a schematic circuit diagram of a semiconductor switch circuit including an embodiment of the present invention.

【図2】同上における半導体スイッチ回路を構成する半
導体スイッチング素子の電流−電圧特性を示す波形図で
ある。
FIG. 2 is a waveform chart showing current-voltage characteristics of a semiconductor switching element included in the semiconductor switch circuit of the above.

【図3】従来例を含む半導体スイッチ回路の概略回路図
である。
FIG. 3 is a schematic circuit diagram of a semiconductor switch circuit including a conventional example.

【図4】同上における半導体スイッチ回路を構成する半
導体スイッチング素子の電流−電圧特性を示す波形図で
ある。
FIG. 4 is a waveform chart showing current-voltage characteristics of a semiconductor switching element included in the semiconductor switch circuit of the above.

【符号の説明】[Explanation of symbols]

1 保護回路 2 電流検出抵抗 3 ゲート制御用トランジスタ 14 パワーMOSFET DESCRIPTION OF SYMBOLS 1 Protection circuit 2 Current detection resistor 3 Gate control transistor 14 Power MOSFET

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/78 H03K 17/687 A H03F 1/52 H03K 17/687 (72)発明者 鈴村 正彦 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 富井 和志 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 野辺 武 大阪府門真市大字門真1048番地松下電工株 式会社内 Fターム(参考) 5F038 AR07 AZ08 AZ10 BH02 BH06 BH12 BH16 EZ20 5F040 DA25 DA26 DB07 DB10 EB01 EB11 EB14 5F048 AA02 AB10 AC06 AC07 AC10 5J055 AX32 AX37 BX16 CX00 DX09 DX22 EX24 EY01 EY14 EY17 EY28 EZ00 FX04 FX19 FX32 GX02 GX06 5J091 AA01 AA41 AA56 CA57 FA10 FP02 FP05 GP02 HA02 HA10 HA18 HA25 HA44 HA45 KA28 TA02 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 H03K 17/687 A H03F 1/52 H03K 17/687 (72) Inventor Masahiko Suzumura Kadoma, Osaka 1048 Matsushita Electric Works Co., Ltd., Kazumasa Tomii, Kazumasa Tomii 1048 Kadoma Kazuma, Kadoma City, Osaka Pref. Matsushita Electric Works Co., Ltd. F-term in the formula company F-term (reference) AA01 AA41 AA56 CA57 FA10 FP02 FP05 GP02 HA02 HA10 HA18 HA25 HA44 HA45 KA28 TA02

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 制御入力に応じてオンオフする半導体ス
イッチング素子により出力端間を導通状態と非導通状態
に切り換える半導体スイッチ装置の保護回路において、
半導体スイッチング素子の一端と一方の出力端との間に
接続される電流検出抵抗と、電流検出抵抗に生じる電圧
降下に応じて半導体スイッチング素子のゲート電位を制
御するゲート制御用トランジスタとを備え、電流検出抵
抗として正の温度係数を有する抵抗を用いたことを特徴
とする半導体スイッチ装置の保護回路。
1. A protection circuit for a semiconductor switch device wherein an output terminal is switched between a conductive state and a non-conductive state by a semiconductor switching element which is turned on and off according to a control input.
A current detection resistor connected between one end of the semiconductor switching element and one output terminal; and a gate control transistor for controlling a gate potential of the semiconductor switching element in accordance with a voltage drop generated in the current detection resistor, A protection circuit for a semiconductor switch device, wherein a resistor having a positive temperature coefficient is used as a detection resistor.
JP11116452A 1999-04-23 1999-04-23 Protection circuit for semiconductor switch device Pending JP2000307398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11116452A JP2000307398A (en) 1999-04-23 1999-04-23 Protection circuit for semiconductor switch device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11116452A JP2000307398A (en) 1999-04-23 1999-04-23 Protection circuit for semiconductor switch device

Publications (1)

Publication Number Publication Date
JP2000307398A true JP2000307398A (en) 2000-11-02

Family

ID=14687476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11116452A Pending JP2000307398A (en) 1999-04-23 1999-04-23 Protection circuit for semiconductor switch device

Country Status (1)

Country Link
JP (1) JP2000307398A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115752A (en) * 2001-10-05 2003-04-18 Mitsubishi Electric Corp Level shift circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115752A (en) * 2001-10-05 2003-04-18 Mitsubishi Electric Corp Level shift circuit

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