JP2000307128A - Rectifying element and method of manufacturing the same - Google Patents

Abstract

(57) [PROBLEMS] To provide a Schottky diode having a structure in which means for forming a depletion layer can be formed in a desired shape and position. SOLUTION: A Schottky diode 1 includes an n ⁺ silicon layer 3, an n ⁻ silicon layer 5, an n ⁻ silicon layer 11, insulating buried gate electrodes 7a to 7e, and a metal layer 9.
As a means for forming a depletion layer in the n ^- silicon single crystal layers 5 and 11, insulating buried electrodes 7a to 7e are used. The insulating embedded electrodes 7a to 7e are formed by patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rectifying device having a Schottky junction and a method for manufacturing the rectifying device.

[0002]

2. Description of the Related Art Since a Schottky barrier is smaller than a pn barrier, a Schottky diode can lower a forward voltage drop than a pn junction diode. Therefore, the Schottky diode can reduce the loss in the forward direction more than the pn junction diode. Since the Schottky diode has such characteristics, it is used, for example, for rectification of a power supply unit or the like of a portable device.

However, the Schottky diode has a small Schottky barrier and therefore has a large reverse leakage current. As a result, the loss in the reverse direction is large. As a technique for improving this, there is a technique disclosed in JP-A-9-82988.

FIG. 25 is a sectional view of a Schottky diode disclosed in Japanese Patent Application Laid-Open No. 9-82988. First, the structure of this Schottky diode will be described. Schottky diode 114 is an n ⁺ type semiconductor substrate 102
And an n-type semiconductor layer 104 formed thereon. In the n-type semiconductor layer 104, a plurality of p ⁺ -type buried layers 110 are formed at intervals. In the n-type semiconductor layer 104, so as to surround the p ⁺ -type buried layer 110,
A p ⁺ -type guard ring layer 112 is formed. The p ⁺ -type guard ring layer 112 is formed by each p ⁺ -type buried layer 110
(Not shown in FIG. 25). Metal electrode 1 is formed on n-type semiconductor layer 104.
08 is formed. The n-type semiconductor layer 104 and the metal electrode 108 have a Schottky junction. Metal electrode 108
Are electrically connected to the guard ring layer 112. Therefore, the potential of the p ⁺ type buried layer 110 is
And the same potential as On the n-type semiconductor layer 104.
In addition, an insulating film 106 is formed so as to surround the metal electrode 108. The electrode 100 is formed below the n ⁺ type semiconductor substrate 102.

Next, the operation of the Schottky diode will be described. A negative voltage is applied to the electrode 100 and a positive voltage is applied to the metal electrode 108. That is, a forward voltage is applied to the Schottky diode 114. Metal electrode 1
A forward current flows from 08 to the electrode 100.

[0006] A positive voltage is applied to the electrode 100 and a negative voltage is applied to the metal electrode 108. That is, a reverse voltage is applied to the Schottky diode 114. The potential of the p ⁺ type buried layer 110 is the same as the potential of the metal electrode 108. Therefore, a reverse voltage is applied to the pn junction formed by the p ⁺ -type buried layer 110 and the n-type semiconductor layer 104. As a result, a depletion layer spreads from the vicinity of the p ⁺ -type buried layer 110 into the n-type semiconductor layer 104. This depletion layer extends from the vicinity of the adjacent p ⁺ -type buried layer 110 to the n-type semiconductor layer 10.
4 is connected to the depletion layer. Thus, the current is pinched off. Therefore, the Schottky diode 1
14 can reduce the leakage current in the reverse direction. Further, due to the pinch-off, a high electric field is not applied to a junction (Schottky junction) between the metal electrode 108 and the n-type semiconductor layer 104. For this reason, the breakdown voltage of the Schottky diode 114 is higher than the breakdown voltage of the Schottky junction.

[0007]

The Schottky diode 114 shown in FIG. 25 uses a p ⁺ -type buried layer 110 as a means for forming a depletion layer in the n-type semiconductor layer 104. The p ⁺ type buried layer 110 is a diffusion layer. The diffusion layer is not easy to control the spread. For this reason, it is not easy to form the p ⁺ type buried layer 110 in a desired shape and position.

The present invention has been made to solve such a conventional problem. An object of the present invention is to provide a rectifying element having a structure capable of forming a means for forming a depletion layer in a desired shape and position, and a method of manufacturing the same.

[0009]

A rectifying device according to the present invention includes a semiconductor layer, and first and second buried insulating electrodes formed in the semiconductor layer and spaced from each other. A semiconductor layer formed on the first and second buried insulating electrodes; and a metal layer formed on the semiconductor layer and having a Schottky junction with the semiconductor layer.

The rectifying element according to the present invention uses the first and second buried insulating electrodes as means for forming a depletion layer in the semiconductor layer. The insulating embedded electrode is an embedded electrode covered with an insulating layer. The insulating embedded electrode can be formed by patterning. Therefore, the means for forming a depletion layer in the semiconductor layer can be formed in a desired shape and position as compared with the case where a diffusion layer is used as a means for forming a depletion layer in the semiconductor layer.

The rectifying device according to the present invention has a semiconductor layer between the first and second buried insulating electrodes and the metal layer. Then, the metal layer and the semiconductor layer are in Schottky junction. Therefore, according to the present invention, the area of the Schottky junction between the metal layer and the semiconductor layer does not decrease due to the presence of the first and second buried insulating electrodes. Therefore, according to the present invention, it is possible to reduce the current loss when the forward current is conducted.

In the rectifying device according to the present invention, the voltage of the first and second insulating buried electrodes is such that the voltage between the first and second insulating buried electrodes is increased when a reverse voltage is applied to the rectifying device. It is preferable that the voltage be such that a depletion layer capable of pinching off a flowing current is formed in the semiconductor layer.
By this pinch-off, the leakage current in the reverse direction of the rectifier according to the present invention can be reduced. Further, due to the pinch-off, a high electric field is not applied to the junction (Schottky junction) between the metal layer and the semiconductor layer. Therefore, the withstand voltage of the rectifier according to the present invention is higher than the withstand voltage of the Schottky junction.

In the rectifying device according to the present invention, the voltage of the first and second insulating embedded electrodes is such that when a reverse voltage is applied to the rectifying device, the voltage between the first and second insulating embedded electrodes is increased. A depletion layer capable of pinching off a flowing current is formed in the semiconductor layer, and the depletion layer is formed of the first and second depletion layers.
It is preferable that the voltage is formed below the insulating buried electrode. When the depletion layer is formed under the first and second insulating buried electrodes, the reverse breakdown voltage of the rectifier according to the present invention can be further improved by the depletion layer formed at this position.

In the rectifying device according to the present invention, it is preferable that the first and second insulating embedded electrodes are electrically connected to the metal layer. According to such a structure, the potentials of the first and second buried insulating electrodes are the same as the potential of the metal layer. Therefore, when the reverse voltage is applied to the rectifier, the depletion layer can be formed in the semiconductor layer, and when the forward voltage is applied to the rectifier, an accumulation layer can be formed in the semiconductor layer. Note that the accumulation layer is a layer in which carriers of the first conductivity type are accumulated in a semiconductor layer of the first conductivity type. For example, if the semiconductor layer is n-type, the storage layer is n-type. When the semiconductor layer is p-type, the storage layer is p-type.

In the rectifier according to the present invention, it is preferable that the voltages of the first and second buried gate electrodes are controlled independently of the voltage of the metal layer. Thereby, for example, a voltage that can more reliably pinch off and a voltage that can make the depletion layer under the first and second buried gate electrodes thicker can be applied to the first and second buried gate electrodes. it can. As this control means, for example, two types of power supplies having different voltages may be used, or different voltages may be set by a booster circuit in a single power supply.

In the rectifying device according to the present invention, it is preferable that the conductivity type of the first and second buried insulating electrodes is different from the conductivity type of the semiconductor layer. According to this, it is possible to further reduce the leak current as compared with the case where the conductivity type of the first and second buried insulating electrodes is the same as the conductivity type of the semiconductor layer.

In the rectifying element according to the present invention, the region between the first buried insulating electrode and the second buried insulating electrode, the first buried insulating electrode, and the second buried insulating electrode are planarly arranged. It is preferable to provide a third insulating buried electrode formed at a position overlapping with. According to this, the first
The region between the buried insulating electrode and the third buried insulating electrode and the region between the second buried insulating electrode and the third buried insulating electrode are regions where current flows.
The direction in which the depletion layers formed in these regions extend is the thickness direction of the semiconductor layer. The thickness of the semiconductor layer depends on the thin film forming technology. Therefore, the first insulating buried electrode and the third
The distance between the buried electrode and the second buried electrode and the distance between the third buried electrode and the third buried electrode are the first distance.
Can be made smaller than the distance between the buried insulating electrode and the second buried insulating electrode. Therefore, the leakage current when the reverse voltage is applied can be further reduced.

The method for manufacturing a rectifying element according to the present invention comprises:
Forming a first and a second buried insulated electrode at intervals from each other on the semiconductor layer, and forming a first and a second buried insulated electrode between the first and the second buried insulated electrode; Forming a second semiconductor layer on the second insulating buried electrode; and forming a metal layer in Schottky junction with the second semiconductor layer on the second semiconductor layer.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Description of Structure} FIG. 1 is a cross-sectional view of a rectifier according to a first embodiment of the present invention. This rectifier is a Schottky diode. The Schottky diode 1 has the following structure. An n ⁻ silicon single crystal layer 5 is located on n ⁺ silicon single crystal layer 3. Buried insulating electrodes 7a to 7e are located on n ^- silicon single crystal layer 5 with an interval therebetween. The insulating buried electrodes 7a to 7e have a structure in which a polysilicon layer is covered with a silicon oxide layer. There is an n ^- silicon single crystal layer 11 between the insulating embedded electrodes 7a to 7e. The n ^- silicon single crystal layer 11 is also located on the buried insulating electrodes 7a to 7e. The metal layer 9 is on the n ^- silicon single crystal layer 11. N ^- silicon single crystal layer 11 and metal layer 9 are in Schottky junction. Examples of the material of the metal layer 9 include Ti, Cr, M
o, Al, W, Pt, PtSi and the like.

FIG. 2 is a plan view of the Schottky diode 1. The electrode 13 is exposed. The electrode 13 is electrically connected to the buried insulating electrodes 7a to 7e. Electrode 1
Although not shown, 3 is electrically connected to the metal layer 9. Thereby, the potentials of the insulating buried electrodes 7 a to 7 e become the same as the potential of the metal layer 9. FIG. 3 shows A-
It is A sectional drawing. This cross section shows the insulating embedded electrode 7c. Through hole 17 is formed in n ^- silicon single crystal layer 11. The electrode 13 is embedded in the through hole 17. Electrode 13 and through hole 17
An insulating film 15 is formed between the insulating film 15 and the side surface. The electrode 13 is electrically insulated from the n ^- silicon single crystal layer 11 by the insulating film 15.

{Description of Operation} The operation of the Schottky diode 1 will be described with reference to FIG. First, an operation when a forward voltage is applied to the Schottky diode 1 will be described. Positive voltage to the metal layer 9, a negative voltage to the n ⁺ silicon single crystal layer 3 is applied, respectively, the carrier from the n ⁺ silicon single crystal layer 3 the n ^- silicon single crystal layer 5,1
1 and injected into the metal layer 9. Insulated embedded electrode 7
Since a to 7e are electrically connected to the metal layer 9, a positive voltage is applied to the insulating buried electrodes 7a to 7e. As a result, an accumulation layer 19 is formed in the n ^- silicon single crystal layers 5 and 11 near the insulating buried electrodes 7a to 7e. In FIG. 1, the storage layer 1 formed by the insulating buried electrode 7e is shown.
Only 9 is shown. The illustration of the storage layer formed by other insulating buried electrodes is omitted. Electrons are stored in the storage layer. Since the resistance of the n ^- silicon single crystal layers 5 and 11 is reduced by the accumulation layer, carriers are efficiently injected into the metal layer 9.

Next, the Schottky diode 1 is turned in the reverse direction.
The operation when a voltage is applied will be described. Metal layer
Negative voltage at 9, n⁺Positive voltage is applied to the silicon single crystal layer 3
When applied and applied, the storage layer disappears. Instead, fill with insulation
N near the embedded electrodes 7a to 7e ^-Silicon single crystal layer 5, 1
A depletion layer is formed from 1 and the depletion layer spreads. Some insulation
The depletion layer generated from the vicinity of the buried electrode and expanded
Contact with the expanded depletion layer generated from the vicinity of the insulating buried electrode
Touch. This pinches off the current. This state
Then, the reverse voltage is held by these depletion layers. Further
When the reverse voltage increases, the depletion layer becomes n^-Silicon only
Spread over the crystal layer 5. In this state, these depletion layers
Hold the reverse voltage.

{Description of Manufacturing Method} A method of manufacturing the Schottky diode 1 will be described. As shown in FIG.
A silicon substrate 21 on which an n ⁺ silicon single crystal layer 3 and an n ⁻ silicon single crystal layer 5 are stacked is prepared. The impurities of the n ⁺ silicon single crystal layer 3 are arsenic, phosphorus, antimony, etc.
The concentration is 1 × 10 ¹⁸ cm ⁻³ or more. The impurity in the n ^- silicon single crystal layer 5 is phosphorus, and the concentration is 1 × 10 ¹³ to 1 ×.
10 ¹⁷ cm ^-3 . The substrate 21 usually has a high concentration of n ⁺
This is realized by forming an n ^- silicon single crystal layer 5 on the substrate made of the silicon single crystal layer 3 by epitaxial growth.

A silicon oxide layer 23 having a thickness of 0.05 to 0.2 μm is formed on n ^- silicon single crystal layer 5 by using, for example, thermal oxidation. On the silicon oxide layer 23, for example, CV
Using method D, a polysilicon layer 2 having a thickness of 0.5 to 2 μm
5 is formed. The conductivity type of the polysilicon layer 25 is p-type.

As shown in FIG. 5, the polysilicon layer 25 is patterned using, for example, photolithography and etching to form polysilicon electrodes 25a to 25e. The interval between the polysilicon electrodes 25a to 25e is
For example, it is 0.5 to 1.0 μm.

As shown in FIG. 6, the polysilicon electrode 25
For example, using thermal oxidation, a thickness of about
A silicon oxide layer 27 having a thickness of 0.5 to 0.2 μm is formed. Thereby, the insulating embedded electrodes 7a to 7e are completed.

As shown in FIG. 7, the insulating embedded electrode 7a
The silicon oxide layer 23 located between 7e is removed using, for example, photolithography and etching to expose the n ⁻ silicon single crystal layer 5. The exposed portion of the n ^- silicon single crystal layer 5 becomes the seed crystal portion 31.

As shown in FIG. 8, an amorphous silicon layer 29 having a thickness of 0.5 to 2 μm is formed by, for example, a CVD method so as to cover the buried insulating electrodes 7a to 7e.

As shown in FIG. 9, the amorphous silicon layer 29 is monocrystallized by solid phase epitaxial growth using the seed crystal part 31 as a seed crystal, and the n ^- silicon single crystal layer 1 is formed.
Form one. As a method of forming the n ^- silicon single crystal layer 11, for example, a method of forming an n ^- silicon single crystal layer 11 by forming amorphous silicon doped with phosphorus in advance and then performing single crystallization, or a method of forming the n ^- silicon single crystal layer 11 There is a method of forming an n ^- silicon single-crystal layer 11 by forming a crystalline silicon film, making it a single crystal, and then doping phosphorus by ion implantation or the like.

The impurity concentration of the n ^- silicon single crystal layer 11 must be individually set according to the breakdown voltage of the diode.
By using the above method, it is possible to set a wide concentration of about 1 × 10 ¹² to 1 × 10 ¹⁷ cm ⁻³ . The temperature condition for the solid phase epitaxial growth is, for example, 550 to 620 ° C. Then, heat treatment at 900 to 1000 ° C. is performed to improve the film quality of n ⁻ silicon single crystal layer 11.

As shown in FIG. 1, for example, using a sputtering method, the thickness is 0.1 to 1.0 μm, and the material is Ti, Cr,
A metal layer 9 of Mo, Al, W, Pt, PtSi or the like is formed so as to form a Schottky junction with the n ^- silicon single crystal layer 11.

As shown in FIG. 2, the insulating buried electrodes 7a to 7a are formed by using, for example, photolithography and etching.
The through hole exposing the polysilicon electrode of 7e is n
^- forming a silicon single crystal layer 11 (not shown). An insulating layer (not shown) made of, for example, a CVD oxide film is formed on side surfaces of these through holes. This insulating layer electrically separates n ⁻ silicon single crystal layer 11 from electrode 13 to be formed later. An aluminum layer is formed so as to cover n ^- silicon single crystal layer 11 by, for example, a sputtering method (not shown). Then, the electrode 13 is formed by patterning the aluminum layer using, for example, photolithography and etching. Thus, the Schottky diode 1 is completed.

{Description of Effect} (Effect 1) As shown in FIG. 1, the Schottky diode 1 according to the first embodiment of the present invention forms a depletion layer in the n ^- silicon single crystal layers 5 and 11. For this purpose, insulating buried electrodes 7a to 7e are used. As shown in FIGS. 5 to 7, the insulating embedded electrodes 7a to 7e are formed by patterning. Therefore, the means for forming a depletion layer in the semiconductor layer can be formed in a desired shape and position as compared with the case where a diffusion layer is used as a means for forming a depletion layer in the semiconductor layer.

(Effect 2) As shown in FIG. 1, the Schottky diode 1 according to the first embodiment of the present invention has an n ^- silicon single layer between the insulating buried electrodes 7 a to 7 e and the metal layer 9. There is a crystal layer 11. The metal layer 9 and the n ^- silicon single crystal layer 11 are in Schottky junction. For this reason,
According to the first embodiment of the present invention, the area of the Schottky junction between the metal layer and the semiconductor layer is smaller than the area of the buried insulating electrodes 7a to 7a.
There is no decrease due to the presence of 7e. Therefore, according to the first embodiment of the present invention, the loss of current can be reduced when the forward current is conducted.

(Effect 3) According to the first embodiment of the present invention.
Schottky diode 1
The poles 7a to 7e are electrically connected to the metal layer 9. This
According to such a structure, the insulating embedded electrodes 7a to 7e
The potential is the same as the potential of the metal layer 9. Therefore, the show
Embedding insulation when reverse voltage is applied to the turnkey diode 1
Depletion layer that can pinch off the current flowing between the electrodes
Is n^-The silicon single crystal layers 5 and 11 are formed. to this
Thus, the leakage current in the reverse direction can be reduced. Ma
In addition, this pinch off
No high electric field is applied. Because of this,
The withstand voltage of Iode 1 is higher than the withstand voltage of the Schottky junction
It becomes. As the reverse voltage increases further, the depletion layer becomes
N below the edge buried electrodes 7a to 7e^-Silicon single crystal layer 5
Spread. The depletion layer formed at this position
Further improve the reverse breakdown voltage of the toky diode 1
be able to. That is, the Schottky diode 1
The breakdown voltage is not the Schottky junction but n ^-Silicon simple bonding
Parameters of the structures of the crystalline layers 5 and 11 (impurity concentration, thickness
Etc.), so Schottky Dio
The withstand voltage of the gate can be increased.

(Effect 4) In the Schottky diode 1 according to the first embodiment of the present invention, the buried insulating electrodes 7 a to 7 e are electrically connected to the metal layer 9. According to such a structure, the potentials of the insulating buried electrodes 7 a to 7 e are the same as the potential of the metal layer 9. Therefore, when a forward voltage is applied to Schottky diode 1, it becomes possible to form an accumulation layer in n ^- silicon single crystal layers 5, 11. By forming the accumulation layer, the n ^- silicon single crystal layers 5, 11
, The carrier is efficiently injected into the metal layer 9.

[Second Embodiment] {Description of Structure} FIG. 10 is a sectional view of a rectifier according to a second embodiment of the present invention. This rectifier is a Schottky diode. The Schottky diode 51 has the following structure. An n ⁻ silicon single crystal layer 55 is located on n ⁺ silicon single crystal layer 53. Lower insulating buried electrodes 57a to 57a-5 are formed on n ^- silicon single crystal layer 55.
7e are located at intervals. The lower insulating buried electrodes 57a to 57e have a structure in which a polysilicon layer is covered with a silicon oxide layer. Lower-layer insulating buried electrode 57a
The thickness t ₁ of the lower insulating embedded electrodes 57 a to 57 e is 0.2 to 1.0 μm, and the distance d ₁ between the lower insulating embedded electrodes 57 a to 57 e is 0.5 to 1.0 μm.
0 μm. An n ^- silicon single crystal layer 59 is provided between the insulating buried electrodes 57a to 57e. The n ^- silicon single crystal layer 59 is also located on the lower insulating buried electrodes 57a to 57e.

Upper insulating buried electrodes 61 a to 61 d are located on n ⁻ silicon single crystal layer 59 at intervals. The upper insulating buried electrodes 61a to 61d are formed between the lower insulating buried electrodes 57a to 57e and at positions overlapping the lower insulating buried electrodes 57a to 57e in a plane. Upper-layer insulating embedded electrodes 61a to 61d
Has a structure in which a polysilicon layer is covered with a silicon oxide layer. Thickness t of upper-layer insulating embedded electrodes 61a to 61d
₂ is 0.2 to 1.0 μm, and the upper insulating embedded electrode 6
1a~61d distance d ₂ is 0.5 to 1.0 [mu] m. The distance d ₃ between the upper insulating buried electrode 61a~61d and lower insulating buried electrode 57a~57e is 0.1 to 0.3 [mu] m. N ⁻ between the upper insulating insulating electrodes 61a to 61d.
There is a silicon single crystal layer 63. The n ^- silicon single crystal layer 63 is also located on the upper insulating buried electrodes 61a to 61d.

On the n ^- silicon single crystal layer 63, there is a metal layer 65. The n ^- silicon single crystal layer 63 and the metal layer 65 are in Schottky junction. Examples of the material of the metal layer 65 include Ti, Cr, Mo, Al, W, Pt, and Pt.
Si or the like.

FIG. 11 is a plan view of the Schottky diode 51. The electrode 67 is exposed. The electrode 67 is electrically connected to the lower insulating buried electrodes 57a to 57e and the upper insulating buried electrodes 61a to 61d. Electrode 6
Although not shown, 7 is electrically connected to the metal layer 65. Thus, the lower insulating buried electrode 57a
To 57e and the upper-layer insulating buried electrodes 61a to 61d have the same potential as the metal layer 65. FIG. 12 is a sectional view taken along line AA of FIG. In this section, an upper insulating buried electrode 61b and a lower insulating buried electrode 57c are shown. Through hole 69 is formed in n ^- silicon single crystal layer 63. Through holes 71 are formed in n ^- silicon single crystal layers 63 and 59. Through hole 6
Electrodes 67 are embedded in 9 and 71. An insulating film 73 is formed between the electrode 67 and the side surfaces of the through holes 69 and 71. The electrode 67 is electrically insulated from the n ^- silicon single crystal layers 59 and 63 by the insulating film 73.

{Description of Operation} The operation of the Schottky diode 51 will be described with reference to FIG. First, an operation when a forward voltage is applied to the Schottky diode 51 will be described. Positive voltage to the metal layer 65, a negative voltage to the n ⁺ silicon single crystal layer 53 is applied respectively, the carrier from the n ⁺ silicon single crystal layer 53 the n ^- through the silicon single crystal layer 55,59,63, metal Injected into layer 65. Since the lower insulating buried electrodes 57a to 57e and the upper insulating buried electrodes 61a to 61d are electrically connected to the metal layer 65, the lower insulating buried electrodes 57a to 57e are electrically connected to the metal layer 65.
A positive voltage is applied to e and the upper-layer insulating buried electrodes 61a to 61d. As a result, the lower insulating buried electrode 57
Accumulation layers are formed in the n ^- silicon single crystal layers 55, 59, and 63 near a to 57e and the upper insulating buried electrodes 61a to 61d. In FIG. 10, the lower insulating buried electrode 57c is shown.
Layer 75 formed by the process, lower insulating buried electrode 5
Only the storage layer 77 formed by 7d and the storage layer 79 formed by the upper insulating buried electrode 61c are shown. Illustration of other storage layers is omitted. Electrons are stored in the storage layer. Since the resistance of the n ^- silicon single crystal layers 59 and 63 is reduced by the accumulation layer, carriers are efficiently injected into the metal layer 65.

The operation when a reverse voltage is applied to the Schottky diode 51 will be described. Metal layer 65
When a negative voltage is applied to the n ⁺ silicon single crystal layer 53 and a positive voltage is applied to the n ⁺ silicon single crystal layer 53, the accumulation layer disappears. Instead, the n ^- silicon single crystal layers 55 and 5 near the lower insulating buried electrodes 57a to 57e and the upper insulating buried electrodes 61a to 61d.
A depletion layer is formed from 9, 63, and the depletion layer spreads. The depletion layer generated and spread from the vicinity of a certain lower insulating buried electrode comes into contact with the expanded depletion layer generated from the vicinity of the adjacent lower insulating buried electrode. The depletion layer generated and spread from the vicinity of a certain upper insulating buried electrode comes into contact with the expanded depletion layer generated from the vicinity of the adjacent upper insulating buried electrode. The depletion layer generated and spread from the vicinity of a certain lower insulating buried electrode comes into contact with the expanded depletion layer generated from the vicinity of the upper insulating buried electrode located above. These pinch off the current. In this state, the reverse voltage is held by these depletion layers. Further, when the reverse voltage increases, a depletion layer generated from the vicinity of the lower insulating buried electrode spreads to n ⁻ silicon single crystal layer 55. In this state, a reverse voltage is held by these depletion layers.

{Description of Manufacturing Method} A method of manufacturing the Schottky diode 51 will be described. As shown in FIG. 13, n ⁺ silicon single crystal layer 53 and n ⁻ silicon single crystal layer 5
5 is prepared. The impurity of n ⁺ silicon single crystal layer 53 is arsenic, phosphorus, antimony, or the like, and has a concentration of 1 × 10 ¹⁸ cm ⁻³ or more. The impurity in n ⁻ silicon single crystal layer 55 is phosphorus, and the concentration is 1 ×
It is 10 < ¹³ > ^-1 * 10 < ¹⁷ > cm < ^-3 >. The substrate 85 is usually
This is realized by forming an n ⁻ silicon single crystal layer 55 by epitaxial growth on a substrate composed of a high concentration n ⁺ silicon single crystal layer 53.

A silicon oxide layer 81 having a thickness of 0.05 to 0.2 μm is formed on n ^- silicon single crystal layer 55 by using, for example, thermal oxidation. On the silicon oxide layer 81, for example, C
A polysilicon layer 83 having a thickness of 0.5 to 2 μm is formed by using the VD method.

As shown in FIG. 14, the polysilicon layer 83 is patterned using, for example, photolithography and etching to form polysilicon electrodes 83a to 83e. The interval between the polysilicon electrodes 83a to 83e is, for example, 0.5 to 1.0 μm.

As shown in FIG. 15, the polysilicon electrode 8
A silicon oxide layer 87 having a thickness of 0.05 to 0.2 μm is formed around 3a to 83e by using, for example, thermal oxidation.
Thus, the lower insulating buried electrodes 57a to 57e are completed.

As shown in FIG. 16, the silicon oxide layer 81 between the lower-layer insulating buried electrodes 57a to 57e is removed by using, for example, photolithography and etching.
^- exposing the silicon single crystal layer 55. The exposed portion of the n ^- silicon single crystal layer 55 becomes the seed crystal portion 89.

As shown in FIG. 17, an amorphous silicon layer 91 having a thickness of 0.5 to 2.0 μm is formed by, for example, a CVD method so as to cover the insulating buried electrodes 57a to 57e.

As shown in FIG. 18, the amorphous silicon layer 91 is monocrystallized by solid phase epitaxial growth using the seed crystal part 89 as a seed crystal to form an n ^- silicon single crystal layer 59. As a method for forming the n ^- silicon single crystal layer 59, for example, a method of forming an n ^- silicon single crystal layer 59 by forming a film of amorphous silicon doped with phosphorus in advance and then performing single crystallization, or a method of forming an n ^- silicon single crystal layer 59 After the amorphous silicon is formed, the n ^- silicon single crystal layer 59 is monocrystallized and then doped with phosphorus by ion implantation or the like.
Is formed.

It is necessary to individually set the impurity concentration of n ^- silicon single crystal layer 59 according to the breakdown voltage of the diode.
By using the above method, it is possible to set a wide concentration of about 1 × 10 ¹² to 1 × 10 ¹⁷ cm ⁻³ . The temperature condition for the solid phase epitaxial growth is, for example, 550 to 620 ° C. Then, heat treatment at 900 to 1000 ° C. is performed to improve the film quality of n ⁻ silicon single crystal layer 59.

As shown in FIG. 19, a thickness of 0.05 to 0.5 mm is formed on n ^- silicon single crystal layer 59 by using, for example, thermal oxidation.
A 2 μm silicon oxide layer 93 is formed. On the silicon oxide layer 93, for example, a thickness of 0.5 to
A 0 μm polysilicon layer 95 is formed.

As shown in FIG. 20, the polysilicon layer 95 is patterned using, for example, photolithography and etching to form polysilicon electrodes 95a to 95d. The interval between the polysilicon electrodes 95a to 95d is 0.5 to 1.0 μm.

As shown in FIG. 21, the polysilicon electrode 9
A silicon oxide layer 97 having a thickness of 0.05 to 0.2 μm is formed around 5a to 95d by using, for example, thermal oxidation.
Thus, the upper insulating embedded electrodes 61a to 61d are completed.

As shown in FIG. 22, the silicon oxide layer 93 between the upper insulating buried electrodes 61a to 61d is removed by using, for example, photolithography and etching.
^- exposing the silicon single crystal layer 59. The exposed part of the n ^- silicon single crystal layer 59 becomes the seed crystal part 99.

As shown in FIG. 23, an amorphous silicon layer 98 having a thickness of 0.5 to 2.0 μm is formed by, for example, a CVD method so as to cover the upper insulating buried electrodes 61a to 61d.

As shown in FIG. 24, the amorphous silicon layer 98 is monocrystallized by solid phase epitaxial growth using the seed crystal part 99 as a seed crystal to form an n ^- silicon single crystal layer 63. As a method for forming the n ^- silicon single crystal layer 63, for example, a method of forming an n ^- silicon single crystal layer 63 by forming a film of amorphous silicon doped with phosphorus in advance and then performing single crystallization, or a method of forming an n ^- silicon single crystal layer 63. After the amorphous silicon is formed, the n ^- silicon single crystal layer 63 is monocrystallized and then doped with phosphorus by ion implantation or the like.
Is formed.

It is necessary to individually set the impurity concentration of n ^- silicon single crystal layer 63 according to the breakdown voltage of the diode.
By using the above method, it is possible to set a wide concentration of about 1 × 10 ¹² to 1 × 10 ¹⁷ cm ⁻³ . The temperature condition for the solid phase epitaxial growth is, for example, 550 to 620 ° C. Then, a heat treatment at 900 to 1000 ° C. is performed to improve the film quality of n ⁻ silicon single crystal layer 63.

As shown in FIG. 10, for example, by sputtering, the thickness is 0.1 to 1.0 μm, and the material is Ti, C
A metal layer 65 of r, Mo, Al, W, Pt, PtSi or the like is formed so as to form a Schottky junction with the n ^- silicon single crystal layer 63.

As shown in FIG. 11, the upper insulating buried electrodes 61a to 61d and the lower insulating buried electrodes 57a to 57d are formed by using, for example, photolithography and etching.
a through hole for exposing the polysilicon electrode of e n ^-
It is formed on silicon single crystal layers 59 and 63 (not shown).
An insulating layer (not shown) made of, for example, a CVD oxide film is formed on side surfaces of these through holes. The insulating layer the n ^-
This electrically separates the silicon single crystal layers 59 and 63 from an electrode 67 to be formed later. An aluminum layer is formed by, for example, a sputtering method so as to cover n ^- silicon single crystal layer 63 (not shown). Then, the aluminum layer is patterned using, for example, photolithography and etching to form the electrode 67. Thus, the Schottky diode 51 is completed.

{Description of Effect} The Schottky diode 51 according to the second embodiment of the present invention is (effect 1) to (effect 4) of the Schottky diode 1 according to the first embodiment of the present invention. And the following effects are produced.

As shown in FIG. 10, in the Schottky diode 51 according to the second embodiment of the present invention, the pinch-off of the current is caused by the lower insulating buried electrodes 57a-57.
e, a depletion layer between the upper insulating buried electrodes 61a to 61d and a depletion layer between the lower insulating buried electrodes 57a to 57e and the upper insulating buried electrodes 61a to 61d. The distance d ₂ between the upper insulating buried electrodes 61a-61d, is better the distance d ₁ and distance d ₃ between the upper insulating buried electrodes 61a-61d and the lower insulating buried electrodes 57a~57e between the lower insulating buried electrode 57a~57e small, It is possible to reliably pinch off the current. The distance d ₁ and the distance d ₂ depend on the photolithography technology. On the other hand, the distance d ₃ depends on the thin film forming technology. The thin film formation technology can be made finer than the photolithography technology. Therefore, the distance d ₃ can be made smaller than the distance d ₁ and distance d _2. For example, with the current photolithography technology, it is difficult to reduce the distance d ₁ and the distance d ₂ to 0.5 μm or less. In the thin film forming technique, the distance d ₃ can be set to 0.1 μm or less. Therefore, in the Schottky diode 51 according to the second embodiment of the present invention, the lower insulating buried electrodes 57a to 57e and the upper insulating buried electrodes 61a to 61e are provided.
Due to the depletion layer between d and d, the current can be pinched off more reliably.

Although the first and second embodiments have been described with reference to an n-type silicon layer, the present invention can be applied to a p-type silicon layer. In the first and second embodiments, silicon is used as the semiconductor, but the present invention can be applied to other semiconductors.

[Brief description of the drawings]

FIG. 1 is a sectional view of a rectifier according to a first embodiment of the present invention.

FIG. 2 is a plan view of the rectifier according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the rectifier shown in FIG. 2 taken along line AA.

FIG. 4 is a cross-sectional view of the substrate for describing a first step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the substrate for describing a second step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the substrate for explaining a third step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the substrate for describing a fourth step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of the substrate for explaining a fifth step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of a substrate for describing a sixth step of the method for manufacturing the rectifier according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view of a rectifier according to a second embodiment of the present invention.

FIG. 11 is a plan view of a rectifier according to a second embodiment of the present invention.

12 is a cross-sectional view of the rectifier shown in FIG. 11 taken along line AA.

FIG. 13 is a sectional view of a substrate for describing a first step of a method for manufacturing a rectifier according to a second embodiment of the present invention.

FIG. 14 is a cross-sectional view of a substrate for describing a second step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 15 is a sectional view of a substrate for describing a third step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 16 is a sectional view of a substrate for describing a fourth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view of a substrate for describing a fifth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view of a substrate for describing a sixth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 19 is a sectional view of a substrate for explaining a seventh step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view of a substrate for describing an eighth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 21 is a sectional view of a substrate for explaining a ninth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 22 is a cross-sectional view of a substrate for describing a tenth step of the method for manufacturing a rectifier according to the second embodiment of the present invention.

FIG. 23 is a cross-sectional view of a substrate for explaining an eleventh step of the method for manufacturing a rectifier according to the second embodiment of the present invention.

FIG. 24 is a cross-sectional view of a substrate for describing a twelfth step of the method for manufacturing the rectifier according to the second embodiment of the present invention.

FIG. 25 is a sectional view of a Schottky diode disclosed in Japanese Patent Application Laid-Open No. 9-82988.

[Description of Signs] 1, Schottky diode 3, n ⁺ silicon layer 5, n ⁻ silicon layer 7a to 7e, insulating buried gate electrode 9, metal layer 11, n ⁻ silicon layer 13, electrode 15, insulating layer 17, through Hole 19, accumulation layer 21, silicon substrate 23, silicon oxide layer 25, polysilicon layers 25a to 25e, polysilicon electrode 27, silicon oxide layer 29, amorphous silicon layer 31, seed crystal part 51, Schottky diode 53, n ⁺ silicon layer 55, n ⁻ silicon layers 57a to 57e, lower insulating buried gate electrode 59, n ⁻ silicon layers 61a to 61d, upper insulating buried gate electrode 63, n ⁻ silicon layer 65, metal layer 67, electrodes 69, 71 , Through hole 73, insulating layers 75, 77, 79, storage layer 81, silicon layer 83, polysilicon 83a to 83e, polysilicon electrode 85, silicon substrate 87, silicon oxide layer 89, seed crystal part 91, amorphous silicon layer 93, silicon oxide layer 95, polysilicon layer 97, silicon oxide layer 98, amorphous silicon layer 99, seed crystal part

Claims (5)

[Claims] 1. A semiconductor device comprising: a semiconductor layer; and first and second insulating buried electrodes formed in the semiconductor layer and formed to be spaced apart from each other, wherein the first and second insulating buried electrodes are provided. A rectifying device, comprising: a semiconductor layer formed on an electrode; and a metal layer formed on the semiconductor layer and in Schottky junction with the semiconductor layer. 2. The buried electrode according to claim 1, wherein the voltages of the first and second buried insulating electrodes are different from each other when a reverse voltage is applied to the rectifying element. A rectifier element, wherein a depletion layer is a voltage formed in the semiconductor layer so as to pinch off a current flowing between the rectifier element and the semiconductor layer. 3. The buried electrode according to claim 1, wherein the voltages of the first and second buried insulating electrodes are different from each other when a reverse voltage is applied to the rectifying element. A rectifier element, wherein a depletion layer capable of pinching off a current flowing between the first and second insulating buried electrodes is formed in the semiconductor layer, and the depletion layer is formed under the first and second insulating buried electrodes. 4. The buried electrode according to claim 1, wherein: a region between the first buried electrode and the second buried electrode;
A rectifying element, comprising: a third insulating buried electrode formed at a position overlapping the second insulating buried electrode in a plane. 5. A step of forming first and second buried insulated electrodes at intervals on the first semiconductor layer, and between the first buried insulated electrode and the second buried insulated electrode. Forming a second semiconductor layer on the first insulating embedded electrode and on the second insulating embedded electrode; and forming a Schottky junction with the second semiconductor layer on the second semiconductor layer. Forming a metal layer according to claim 1. A method for manufacturing a rectifying element, comprising: