JP2000307068A - Semiconductor device, use thereof, and method of testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily carry out a test where a high voltage is applied to a high- voltage circuit element in an integrated circuit chip where a low-voltage and a high-voltage circuit are mixedly provided. SOLUTION: A low-voltage circuit 12 is composed of buffer circuits 14 and 15 which form a logic circuit. A high-voltage circuit 13 is mainly composed of a P-channel MOSFET 16 and an N-channel MOSFET 17. The circuits 12 and 13 are formed on a semiconductor substrate of SOI structure, where a low-voltage ground terminal GNDL and a high-voltage ground terminal GNDH are electrically isolated from one another. The ground terminals GNDH and GNSL are connected in common outside when an integrated circuit chip is in use, and when a screening test is carried out, the high-voltage ground terminal GNDH is kept at a voltage of -50 V, a high-voltage power supply terminal VDDH is kept open, the low-voltage circuit 12 is kept under the same conditions as it is in use, by which a high voltage can be applied between the gate and source of the MOSFET 17 without having an adverse effect on a logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low-voltage circuit section and a high-voltage circuit section integrated on a semiconductor substrate, and a test method therefor.

[0002]

SUMMARY OF THE INVENTION In an integrated circuit or the like having a logic low-voltage circuit element and a high-breakdown-voltage n-channel FET integrated with each other, the high-breakdown-voltage n-channel FET is grounded at the source. When used, when screening is performed by applying a high voltage between the source and the gate, such a screening test cannot be performed as it is because a high voltage is simultaneously applied to circuit elements of a logic system. .

FIG. 4 shows an example of an integrated circuit having such a configuration, in which a logic circuit 1 and a high-voltage circuit 2 are provided integrally. The logic circuit 1 is provided with buffer circuits 3 and 4 to which power is supplied from the low-voltage power supply VDD, and to which complementary input signals Pin and Pinx are supplied. The high-voltage circuit 2 includes a p-channel MOSFET 5 and an n-channel MOSFET 6 connected in a push-pull manner between a high-voltage power supply VDDH and a ground terminal;
Bias resistor 7 for driving p-channel MOSFET 5 and n-channel MOSFET 8 for driving
It is composed of

When a high-level signal Pin is applied from a buffer circuit 3 to a driving n-channel MOSFET 8, a p-channel MOSFET 5 has a bias resistor 7.
, And a gate bias is applied to turn on. At this time, since the low-level signal Pinx is supplied to the buffer circuit 4, the n-channel MOSFET 6 is kept in the off state. As a result, the output terminal Q is connected to the high voltage power supply VDD.
H is supplied via the p-channel MOSFET 5.
When a low-level signal Pin is supplied to the buffer circuit 3 and a high-level signal Pinx is supplied to the buffer circuit 4, the p-channel MOSFET 5 is turned off, the n-channel MOSFET 6 is turned on, and the output terminal Q is electrically connected to the ground terminal. Becomes

In such a configuration, when performing a screening test of the manufactured integrated circuit, the high-voltage circuit 2
Since the n-channel MOSFET 6 is configured to receive a gate signal from the low-voltage logic circuit 1, a screening test in which a high voltage of, for example, 7 V or more is applied to the gate cannot be performed. I have. This is because the ground terminals of the logic circuit 1 and the high voltage circuit 2 are connected to a common semiconductor substrate (not shown), and a high voltage is also applied to the logic circuit. This is because elements constituting the logic circuit are destroyed.

In order to apply a high voltage to the gate of the n-channel MOSFET even in such a configuration, for example, a switch is provided between the logic circuit and the gate of the n-channel MOSFET. In a screening test, a configuration is considered in which a high voltage is applied to the gate in a state where the switching element is turned off. However, in this case, since the switching element is separately provided, the circuit area is increased by that amount, and the configuration of how to apply a high voltage to the switching element itself becomes a problem. This makes it difficult to adopt them.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a high-voltage element independently of a low-voltage element without increasing the circuit area in a chip. An object of the present invention is to provide a semiconductor device capable of applying a high voltage thereto and a method of testing the semiconductor device.

[0008]

According to the first aspect of the present invention, the low voltage system ground terminal (GNDL) of the low voltage system circuit section (12) can be electrically connected to the end of the semiconductor substrate (20). In addition to the above, the high voltage system ground terminal (GNDH) of the high voltage system circuit section (13) is electrically connected to the end of the semiconductor substrate (20).
A circuit element (17) connected to a high-voltage ground terminal (GNDH) when performing a screening test on circuit elements constituting the high-voltage circuit section (13).
Low voltage circuit section (12)
Can be connected so as not to apply an excessive voltage to the circuit elements (14, 15). As a result, the screening test can be performed as a configuration that does not require a special circuit element.

According to the second aspect of the present invention, the high voltage system circuit section (13) has a high withstand voltage n-channel type F as a circuit element.
Since the configuration is such that the ET (17) is used with the source grounded, a configuration suitable for performing a screening test by applying a high voltage to the gate of the FET (17) can be obtained.

According to the third aspect of the present invention,
SOI (Semiconductor On I) as a semiconductor substrate (20)
nsulator) substrate and a low-voltage circuit section (1
2) and the high-voltage circuit section (13)
Since the low-voltage ground terminal (GNDL) and the high-voltage ground terminal (GNDH) are formed on the OI layer to derive, the semiconductor substrate (20) itself is different from the common ground terminal. The low-voltage circuit section (12) and the high-voltage circuit section (13) may be provided with independent ground terminals (GNDL, GNDH). As a result, even when the above-described screening test is performed, the screening test can be performed without adding a circuit element for testing.

According to the fourth aspect of the present invention, when the semiconductor device having the above-described configuration is used, the low-voltage ground terminal (GNDL) and the high-voltage ground terminal (GND) are used.
And H) are used in a state where they are commonly connected by external terminals, so that they can be handled in the same manner as the conventional circuit in a normal circuit configuration. In this case, there is no particular addition in the circuit configuration. , Can be used without hindrance.

According to a fifth aspect of the present invention, a semiconductor device having the above configuration is used to provide a high voltage between the circuit element (17) of the high voltage system circuit section (13) and the high voltage system ground terminal (GNDH). When performing a test for applying a voltage, a high voltage is applied to the high voltage system ground terminal (GNDH) by applying a voltage on the negative side of the low voltage system ground terminal (GNDL). A test for applying a high voltage to the high-voltage circuit element (17) can be performed independently. Even in this case, the low-voltage circuit element (14,
With respect to 15), a test can be performed by preventing high voltage from being applied and preventing destruction.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows one electrical configuration of a large number of drive units 11 formed inside an integrated circuit chip.
Has a configuration in which a low-voltage circuit section 12 and a high-voltage circuit section 13 are provided.

The low voltage circuit section 12 configured as a logic circuit section includes buffer circuits 14 and 15 made of CMOS.
Is provided. The buffer circuits 14 and 15 are configured such that signals of complementary logical levels Pin and Pinx are supplied to input terminals, and output signals indicating the same logical level from output terminals in response to the signals. One of the power supply terminals of the buffer circuits 14 and 15 has a low-voltage power supply terminal VDD.
L, and the other is connected to the low-voltage ground terminal GNDL.

The high voltage system circuit section 13 includes a high voltage power supply terminal V
P-channel MOSFET 16 connected in a push-pull type between DDH and high voltage system ground terminal GNDH
And an n-channel MOSFET 17 as a main component. The MOSFETs 16 and 17 are both LDMOS (Lateral Double defused MOS) as described later.
It is formed on a semiconductor substrate 20 (see FIG. 2) as an element adopting the structure, and the terminals of the MOSFETs 16 and 17 can be provided independently.

These MOSFETs 16 and 17 are source-grounded circuits whose sources are connected to a high-voltage power supply terminal VDDH and a high-voltage ground terminal GNDH, respectively, and their drains are connected in common and used as output terminals Q. The gate terminal of the n-channel type MOSFET 17 is connected to the output terminal of the buffer circuit 15 of the low voltage system circuit section 12, so that on / off is controlled. As a drive circuit for controlling on / off of the p-channel MOSFET 16,
High voltage power supply terminal VDDH and high voltage system ground terminal GND
H, bias resistors 18a, 18b, 18c and a driving n-channel MOSFET 19 are connected in series.

The gate terminal of the n-channel MOSFET 19 is connected to the output terminal of the buffer circuit 14 of the low-voltage circuit section 12, so that on / off is controlled. It is connected so that a voltage obtained by dividing the bias resistors 18a to 18c is applied to the gate terminal of the p-channel MOSFET 16. In addition, each MOSFET
Each of 16, 17, and 19 has a structure in which diodes 16a, 17a, and 19a formed in a structure are connected between the drain and the source.

FIG. 2 is a schematic sectional view showing a state in which the above-mentioned drive unit 11 is formed on a silicon substrate 20 which is a semiconductor substrate, and this configuration will be briefly described below. An insulating film 21 such as SiO2 is formed on the entire surface of the silicon substrate 20, and a single-crystal silicon film 22 is formed thereon, and has an SOI (Silicon On Insulator) structure. The single-crystal silicon film 22 has a thickness of about 1 μm to about several μm and is formed as an n−− type in which a very small amount of n-type impurity is introduced, but is set to have a high resistance close to that of an intrinsic semiconductor. ing.

The low-voltage circuit section 12 and the high-voltage circuit section 13 described above are formed in the single crystal silicon film 22. FIG. 2 shows a low-voltage circuit section 1 for simplicity.
2 and a p-channel MOSFET configured as the high-voltage circuit 13
T16 and n-channel MOSFET 17 are shown as representatives.

The single crystal silicon film 22 is separated by trenches into element formation regions of the respective elements. The surface portion of the single crystal silicon film 22 enhances the insulation at the boundary between the element formation regions, and has a LOCOS 23 in a predetermined region within the element formation region. Are formed. The n-channel type MOSFET 24 and the p-channel type MOS 24
An FET 25 is formed. A p-type well 26 with a low impurity concentration and an n-type well 27 with a low impurity concentration are formed correspondingly, and an n-type source and a high impurity concentration are formed.
Drain regions 28a and 28b and p-type source / drain regions 29a and 29b having a high impurity concentration are formed.

A gate oxide film is formed between the source / drain regions 28a and 28b and between the source and drain regions 29a and 29b, and gate electrodes 30 and 31 made of polysilicon are formed in a predetermined shape. 3
3a and drain electrodes 32b and 33b are formed.
Source electrode 32a of n-channel MOSFET 24
Is formed with an electrode pattern (not shown) so as to be connected to the low-voltage ground terminal GNDL. The other electrodes 32b, 33a, 33b are formed with an electrode pattern (not shown) so as to be connected between circuit elements.

Next, in the element forming region of the n-channel type MOSFET 17, a low concentration n-type impurity is entirely introduced into the single crystal silicon film 22 to a predetermined depth.
An n-type region 34 having a relatively low impurity concentration is formed in the drain formation region at the center thereof, and an n-type region 35 having a high impurity concentration is double-diffused inside the region. In the peripheral portion, a p-type well region 3 having a low impurity concentration is formed in a source forming region.
6, a p-type channel region 37 is formed, and a p-type region 38 having a high impurity concentration and an n-type region 39 having a high impurity concentration are formed in an inner region thereof.

A gate oxide film is formed on the p-type channel region 37, and a gate electrode 40 made of polysilicon is formed thereon in a predetermined shape. The source electrode 41 extends over both the p-type region 38 and the n-type region 39.
Is formed, a drain electrode 42 is formed on the n-type region 35 of the drain formation region, and a gate extraction electrode 43 is formed on the gate electrode 40. The source electrode 41 of the n-channel MOSFET 17 is, as described above,
It is wired by an electrode pattern (not shown) so as to be connected to the high voltage system ground terminal GNDH.

Similarly, a p-channel MOSFET
Also in the 16 element formation regions, each region is formed in such a manner that the n-type and the p-type are interchanged. That is, p-type regions 44 and 45 are formed in the drain formation region, an n-type well region 46, an n-type channel region 47, an n-type region 48, and a p-type region 49 are formed in the source formation region. An electrode 50, a source electrode 51, a drain electrode 52, and a gate extraction electrode 53 are formed.

In the above configuration, the low-voltage circuit section 12
And the high-voltage circuit section 13 are provided independently as different ground terminals GNDL and GNDH, respectively, and are also provided on the semiconductor substrate 20 in a state of being insulated from the substrate side. Rather than having a common ground terminal structurally as in the conventional configuration, a common ground terminal can be used by connecting externally, or a different ground terminal can be used if necessary. Has become. In addition, a large number of the drive units 11 described above are provided, and the low-voltage ground terminals GNDL are connected in common, and the high-voltage ground terminals GNDH are also connected in common. I have.

When the integrated circuit chip is actually used, the low-voltage ground terminal GNDL and the high-voltage ground terminal GNDH described above are led out of the package as leads which are external terminals. ,
Wiring is performed such that these are connected in common and used.

The operation of the above-described circuit configuration is such that the input terminals Pin, Pinx
Are supplied with complementary input signals. For example, when Pin is a high-level signal and Pinx is a low-level signal, the following operation is performed.
Here, the low-voltage power supply terminal VDDL is supplied with a voltage of, for example, about 5 V, and the high-voltage power supply terminal VDDH is supplied with a voltage of, for example, about 200 V.

First, a high-level signal is output via the buffer circuit 14 in response to the input signal Pin, so that the n-channel MOSFET 19 of the high-voltage circuit section 13 is turned on. As a result, a current flows from the high-voltage power supply terminal VDDH to the bias resistors 18a to 18c, and the p-channel MOSFET 16 in the output stage is turned on when a gate bias is applied. Since the input signal Pinx is at a low level, an n-channel MOSFET at the output stage
17 is kept in the off state. As a result, the output terminal Q is connected to the high voltage power supply terminal V
The state becomes conductive with DDH.

On the other hand, when a low-level signal and a high-level signal are input to the input terminals Pin and Pinx, the n-channel MOSFET 19 is turned off, and the p-channel MOSFET 16 in the output stage is also turned off. . And an n-channel MOSFET 17
Is turned on when a gate bias is applied.
As a result, the output terminal Q is connected to the MOSFET 17
Through the high voltage system ground terminal GNDH.

Next, an n-channel type MOSFE of the output stage in the drive unit 11 of the integrated circuit chip having the above configuration.
The T17 gate screening test will be described.
FIG. 3 shows a connection state of each terminal in the screening test. In this test, different potentials are applied without connecting the low-voltage ground terminal GNDL and the high-voltage ground terminal GNDH.

More specifically, an n-channel MOSFET
In order to apply a DC voltage of 50 V between the gate and the source of No. 17, the low-voltage ground terminal GNDL is 0 V, the high-voltage ground terminal GNDH is -50 V, and the low-voltage power supply terminal V
The test is performed with DDL at 5 V and the high voltage power supply terminal VDDH open. At this time, the input signals Pin and Pinx to the low-voltage circuit section 12 are applied as a high level and a low level so that a low level, that is, 0 V is applied to the gate terminal of the n-channel MOSFET 17.

As a result, the gate of MOSFET 17
A voltage of 50 V can be relatively applied between the sources. At this time, since the low-voltage-system ground terminal GNDL is maintained at 0 V, a voltage of about the normal operation level is applied to each circuit element of the low-voltage-system circuit section 12, and the high Since the voltage of the voltage system circuit section 13 does not act, the screening test can be reliably and nondestructively performed. Also, a large number of drive units 11 formed on the integrated circuit chip
Are connected in common between the low-voltage ground terminals GNDL and the high-voltage ground terminals GNDH, respectively, so that the screening test can be performed simultaneously.

According to this embodiment, the low-voltage circuit section 12 and the high-voltage circuit section 13 are formed on the semiconductor substrate 20 adopting the SOI structure in a state of being insulated and separated from each other. Is the low voltage ground terminal GNDL
And a high-voltage system ground terminal GNDH, which is led out to an external terminal. Therefore, even when a high voltage is applied in the gate screening test of the n-channel MOSFET 17 of the high-voltage system circuit unit 13, the low-voltage system circuit unit The test can be performed without adversely affecting the twelve circuit elements, and when used, the circuit can be operated without any trouble by conducting between the external terminals. .

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. Although the case where the MOSFET is used as the circuit element of the high-voltage circuit unit 13 has been described, a configuration using a bipolar transistor or IGBT may be used.

The gate screening test has been described for the case where the low-voltage ground terminal GNDL is set to 0 V and the high-voltage ground terminal GNDH is set to -50 V. However, the present invention is not limited to this, and the potential of the high-voltage ground terminal GNDH is set to a low level. Similar effects can be obtained by setting the potential relatively lower than the voltage-system ground terminal GNDL.

The high-voltage circuit section 13 is not limited to a push-pull circuit, but can be applied to various other circuits.
A high voltage system ground terminal GNDH for a circuit element having a terminal electrically connected to a circuit element of the low voltage system circuit unit
The present invention can be applied to all types of tests in which a high voltage is applied between the test.

[Brief description of the drawings]

FIG. 1 is an electrical configuration diagram of a drive unit showing one embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a main part.

FIG. 3 is an explanatory diagram showing a state of each terminal in a screening test.

FIG. 4 is a diagram corresponding to FIG. 1 showing a conventional example.

[Explanation of symbols]

11 is a drive unit, 12 is a low voltage circuit, 13 is a high voltage circuit, 14 and 15 are buffer circuits, 16 is a p-channel MOSFET, and 17 is an n-channel MOS.
FETs, 18a to 18c are bias resistors, 19 is an n-channel MOSFET, 20 is a semiconductor substrate, GNDL is a low voltage ground terminal, GNDH is a high voltage ground terminal, VDDL is a low voltage power supply terminal, and VDDH is a high voltage power supply terminal. It is.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AV05 AV06 BE05 BE09 BH07 BH12 CD08 DT02 DT09 DT20 EZ06 EZ20 5F048 AA02 AB10 AC03 BA09 BB05 BC07 BE03 BG07 5F110 AA24 BB04 CC02 DD05 DD13 EE09 FF02 GG02 NN62

Claims (5)

[Claims] 1. A semiconductor device having a structure in which a low-voltage circuit section (12) and a high-voltage circuit section (13) are integrated on a semiconductor substrate (20). A low-voltage ground terminal (GNDL) of the low-voltage circuit section (12) that is electrically connected and a high-voltage circuit section that is electrically connected to an end of the semiconductor substrate (20); (13) A semiconductor device comprising the high-voltage system ground terminal (GNDH) independently of each other. 2. The semiconductor device according to claim 1, wherein the high-voltage circuit section is configured such that a high-breakdown-voltage n-channel FET is used as a circuit element by grounding the source. A semiconductor device. 3. The semiconductor device according to claim 1, wherein said semiconductor substrate (20) is formed of an SOI (Semiconductor On Semiconductor).
Insulator) substrate, the low-voltage circuit section (12) and the high-voltage circuit section (1)
3) are formed on different SOI layers, respectively, and the substrate region of each SOI layer is independent of the low-voltage ground terminal (GND).
L) and a high-voltage system ground terminal (GNDH). 4. The method of using the semiconductor device according to claim 1, wherein the low-voltage ground terminal (GNDL) and the high-voltage ground terminal (GNDH) are connected in common. A method for using a semiconductor device, wherein the method is used as a semiconductor device. 5. The method for testing a semiconductor device according to claim 1, wherein a circuit element of the high-voltage circuit section (13) and a high-voltage ground terminal (GNDH) are connected. When performing a withstand voltage test in which a high voltage is applied in between, the high voltage is applied to the high voltage ground terminal (GNDH) by applying a voltage more negative than the low voltage ground terminal (GNDL). A method for testing a semiconductor device, comprising applying a voltage.