JP2000306380A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [PROBLEMS] To provide a semiconductor integrated circuit device provided with a charge pump circuit that enables efficient charge pump operation up to a low voltage region. SOLUTION: Charge is charged up to a first capacitor by a precharge circuit in response to a first timing, and charge stored in the first capacitor via a transfer gate in response to a second timing. Charge pump circuit for transferring the current to the second capacitor holding the output voltage, wherein either the precharge circuit or the transfer gate is a P-channel MOSFET and an N-channel MOSFET.
It is composed of a parallel circuit of OSFETs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an internal circuit using a charge pump circuit in a semiconductor integrated circuit device such as a system LSI having a dynamic RAM (random access memory). The present invention relates to a technology that is effective when used in a power supply circuit.

[0002]

2. Description of the Related Art With the development of semiconductor technology, large-scale integrated circuits are moving toward a technique of combining large-scale macros (cores) in the same manner as the design of a printed circuit board combining components. Memory is indispensable in digital signal processing. In particular, a dynamic RAM has a feature that a large storage capacity can be obtained.
The above-mentioned large-scale integrated circuit plays an important role. Such large-scale LSIs for specific applications are described in Nikkei McGraw-Hill, March 11, 1996, "Nikkei Electronics", pp. 107-125.

[0003]

In the above-mentioned semiconductor integrated circuit device, at least the power supply voltage has been reduced for high-speed operation and low power consumption while responding to miniaturization of elements. . On the other hand, in a dynamic RAM,
Set the word line selection level higher than the power supply voltage to increase the read and write efficiency from the memory cell, or supply a negative back bias voltage to the substrate to increase the information retention time of the memory cell. Thus, in addition to the power supply voltage supplied from the outside, it is necessary to internally generate a boosted voltage higher than the power supply voltage or to generate a negative voltage by using a charge pump circuit.

As described above, as the power supply voltage of the semiconductor integrated circuit device decreases, the difference from the threshold voltage of the MOSFET formed therein becomes smaller as an absolute value. It has been clarified by the study of the present inventors that the temperature is reduced to a level that cannot be ignored. Also, in consideration of the current consumption of the charge pump circuit itself, it is necessary to realize a current supply operation corresponding to the operation mode of the internal circuit while reducing the circuit scale of the charge pump circuit.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device provided with a charge pump circuit that enables efficient charge pump operation up to a low voltage region. Another object of the present invention is to provide a semiconductor integrated circuit device having an internal power supply circuit capable of realizing a current supply operation corresponding to an operation mode of an internal circuit while reducing the circuit scale. Further objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

Means for Solving the Problems In the present application, an outline of a representative one of the disclosed inventions will be briefly described as follows. That is, the first capacitor is charged up by the precharge circuit in response to the first timing, and the charge stored in the first capacitor is output through the transfer gate in response to the second timing. In a charge pump circuit for transferring a voltage to a second capacitor for holding a voltage, one of the precharge circuit and the transfer gate is replaced with a P-channel type MOSFET.
It is composed of a parallel circuit of T and N-channel MOSFETs.

[0007]

FIG. 12 is a block diagram showing one embodiment of a dynamic memory (hereinafter simply referred to as DRAM) mounted on a semiconductor integrated circuit device to which the present invention is applied. This DRAM is, for example, a system LSI
(Semiconductor integrated circuit device) constitutes one module or functional unit.

Although the DRAM shown is not particularly limited,
A bank configuration is adopted so as to be compatible with large storage capacity. The number of memory banks can be changed, for example, with a maximum of 16 memory banks. One memory bank, for example, a first memory bank bank1, includes a memory cell array MA1,
It comprises a sense amplifier SA0, SA1 and a bit line precharge circuit (not shown) integrated with the sense amplifier, a timing generation circuit and a column selector TC1, a row decoder RD1, and a column switch circuit CS1.

An address bus / control bus ADCB for address signals and control signals is set for these plurality of memory banks, and a memory internal bus (I / O internal bus) IOB for data input / output is set. ing. A common memory input / output circuit MI / O is provided for the buses ADCB and IOB. Memory input / output circuit M-
The I / O has a port connected to the internal bus BUS of FIG. 13 therein.

The DRAM also includes a substrate bias switching circuit VBBM coupled to a substrate bias control circuit VBBC via a wiring group VL & CL, an internal power supply circuit IMVC, internal operation control signals mq and pmq, a reset signal resb, and a control bus CBUS. Memory control circuit MMC receiving various operation control signals through a power supply, and a power supply initialization circuit VINT
Hold C.

In the above description, a set of elements in a wider range can be regarded as being composed of fewer elements, depending on the convenience of a management unit of design data in design automation for configuring a semiconductor integrated circuit device. For example, a memory cell array (MA1), sense amplifiers (SA1 and SA2) in one memory bank,
Row decoder (RD1) and column switch (CS
1) can be regarded as constituting one memory mat, and a timing generation circuit and a column selector (TC)
1) can be regarded as constituting a bank control circuit. In this case, each memory bank is more simply regarded as comprising a memory mat and a bank control circuit.

In the illustrated DRAM, the memory mat and its selection circuit are almost the same as those of a known DRAM configured as an independent CMOS semiconductor integrated circuit device. Therefore, a detailed description of the internal configuration will be avoided, but a brief description thereof is as follows.

<Memory Cell Array MA1-MAn> A memory cell array such as the memory cell array MA1 includes a plurality of dynamic memory cells arranged in a matrix,
It includes a plurality of word lines to which selection terminals of corresponding memory cells are coupled, and a plurality of bit lines to which data input / output terminals of corresponding memory cells are coupled.

A selection MOSFET constituting a memory cell
Has a structure in which an N-type source region and an N-type drain region are formed in a P-type well region PWELL1 formed on a semiconductor substrate made of P-type single crystal silicon. Although not particularly limited, the semiconductor device is electrically separated from the semiconductor substrate by an N-type isolation semiconductor region having a relatively low impurity concentration. Such an isolation region is set to a positive potential such as the power supply terminal vdd of the circuit. The N-type isolation semiconductor region functions to protect the P-type well region PWELL1 from undesired carriers generated in the P-type semiconductor substrate due to α particles or the like.

A P-type well region P in which a memory cell is formed
WELL1 is supplied with a negative substrate bias voltage vbb formed by an internal power supply circuit IMVC in the DRAM. This allows the selection MOS in the memory cell
The tailing current or leakage current of the FET is reduced, and the information leakage of the information storage capacitor in the memory cell is reduced.

On P-type well region PWELL1, an information storage capacitor in a memory cell is formed via an insulating film such as a silicon oxide film. One electrode of the information storage capacitor is electrically coupled to an electrode region that can be regarded as a source region of the selection MOSFET. The other electrode of each of the plurality of information storage capacitors for the plurality of memory cells is a common electrode called a so-called plate electrode. The plate electrode has a predetermined potential vpl as a capacitance electrode.
Is given.

It is desirable that the information storage capacitor has a relatively small size so as to reduce the size of the memory cell array, and also has a large capacitance value so as to have a long information holding time by itself. It is. For the information storage capacitor, the dielectric film sandwiched between its electrodes is selected from a material having a relatively large dielectric constant, such as tantalum oxide or silicon oxide, and has a large capacitance value per unit area. The thickness is made extremely thin so as to increase the capacity of the device. The plate electrode potential vpl for the plurality of information storage capacitors is set to an intermediate potential equal to half of the power supply voltage vdd of the circuit formed by the voltage conversion circuit IMVC.

Thus, the case where a high level such as the power supply voltage vdd level is supplied according to the information to be stored in one electrode of the information storage capacitor and the one electrode is set to be equal to the ground potential of the circuit. The plate electrode potential vp regardless of whether the low level is supplied or not.
1 is set to almost half the potential of the power supply voltage vdd. That is, the voltage applied to the dielectric film is limited to a small value such as approximately half of the power supply voltage vdd. As a result, the dielectric film can have a reduced withstand voltage, and an undesired leak current can be reduced with a decrease in applied voltage.
The thickness can be reduced to a marginal thickness.

<Timing Generation and Column Selector> The timing generation and column selector such as the TC1 is a memory control circuit MCC.
The operation is controlled by an operation control signal from a global control circuit in the memory cell, and is activated or selected by a bank selection signal supplied via a bus ADCB. It forms various internal timing signals for controlling the operation of various circuits such as a decoder, a sense amplifier, and a column selector in itself. The operation of the column selector in the timing generation and column selector is controlled by an internal timing signal.
The column address signal supplied via B is decoded, and a decode signal for operating a column switch circuit in the bank such as the column switch circuit CS1 is formed.

The operation of a row decoder such as the row decoder RD1 is controlled by timing generation and a timing signal supplied from a column selector, decodes an address signal supplied via a bus ADCB, and outputs a corresponding memory cell array. Is selected.

The bit line precharge circuit is operated by a precharge timing signal at a timing before the row decoder is activated, and sets each bit line in the corresponding memory cell array to substantially half the power supply voltage vdd. Precharge to such a level.

<Sense Amplifier> Sense Amplifiers SA0 and S
A sense amplifier such as A1 is operated by a timing signal such as TC1 and a sense amplifier timing signal generated from a column selector circuit after a row decoder is activated, and a bit line is formed by a memory cell selected by the row decoder. , Ie, the read signal is amplified. Each of the plurality of unit sense amplifiers corresponding to each bit line in the sense amplifier has substantially the same configuration as a well-known CMOS configuration sense amplifier.

Each of the unit sense amplifiers has a gate
It has a pair of pMOSs whose drains are cross-connected and a pair of nMOSs whose gates and drains are also cross-connected. The drains of a pair of pMOS and the pair of nMOS are coupled to a corresponding pair of bit lines. A pair of p
The sources of the MOSs are commonly connected, and a switch MOSFE whose operation is controlled by a sense amplifier timing signal
An operating potential is applied via T. Similarly, a pair of nMO
The sources of S are commonly connected, and are supplied with an operating potential such as the ground potential of the circuit via a switch MOSFET whose operation is controlled by a sense amplifier timing signal.

As the operating voltage, for example, a power supply voltage vdd corresponding to the high level of the bit line and a boosted voltage vbs higher than that are used. A so-called overdrive system in which the sense amplifier starts an amplification operation and the amplification operation of the sense amplifier is performed by the boosted voltage vbs for a certain period until the potential of the bit line to be raised to a high level reaches a desired voltage. Is adopted. When the potential of the bit line reaches near the desired potential vdd, the operating voltage of the sense amplifier is switched to the power supply voltage vdd corresponding to the original high level of the bit line.

The arrangement of the two sense amplifiers across the memory cell array means the following configuration. That is,
The sense amplifier on one side of the memory cell array is coupled to discrete bit lines among a plurality of bit lines of the memory cell array, and the sense amplifier on the other side of the memory cell array is connected to a plurality of bit lines of the memory cell array. The remaining intermittent bit lines are coupled. This configuration is suitable for miniaturizing the pitch of a plurality of bit lines in a memory cell array when a plurality of MOSFETs constituting a sense amplifier must be arranged at a relatively large pitch according to a required size. It is effective.

<Column Switch Circuit> A column switch circuit such as the column switch circuit CS1 is operated by a selection signal output from a corresponding column selector. The bit line designated by the column selector among the plurality of bit lines in the memory cell array is selected by the column switch circuit, and is coupled to the memory internal bus IOB.

<Memory Input / Output Circuit M-IO> The memory input / output circuit M-IO is an internal bus BU of the semiconductor integrated circuit device.
S, receives an address signal and a control signal from the internal bus BUS, and transmits it to the internal bus ADCB. The memory input / output circuit M-IO also has a bus BU
Input / output of memory data between S and the memory internal bus IOB.

<Memory Control Circuit MCC> The memory control circuit MCC receives the internal first and second operation control signals mq and pmq and the reset signal resb of the semiconductor integrated circuit device, and performs a control operation according to those signals. . Although not particularly limited, the memory control circuit MCC receives a first operation control signal mq and a second operation control signal pmq, and forms an internal operation control signal bbcz accordingly, and a first operation control circuit MSW. Signal mq and reset signal re
sb and accordingly the substantial initialization control signal int
gb forming a second control logic circuit VINT.

(Substrate Bias Switching Circuit VBBM) The substrate bias switching circuit VBBM includes a substrate bias control circuit VBBM.
Various bias voltages v from BC via line group VL & CL
bp, vbn, vbpg, vbng, and control signal vb
cp, vbcn, and a control signal bbcz from the memory control circuit MCC, and supplies a bias voltage to a required circuit portion in the DRAM under the control of the bias voltage and the control signal.

(Voltage Conversion Circuit MVC) Voltage Conversion Circuit IM
VC is a power supply terminal VDD and a reference potential terminal VS of the DRAM.
S, the substrate bias voltage vbb for the memory cell array, the plate voltage vpl, the boost voltage vdh for setting the word line selection level, and the overdrive of the sense amplifier. Internal voltage such as a boosted voltage vbs for use. Although not particularly limited, the substrate bias voltage vbb for the memory cell array is formed in the circuit IMVC in the DRAM as a module. The circuit that forms the bias voltage vbb and the boosted voltages vdh and vbs at the negative potential level is designed to form a desired negative voltage even with a low power supply voltage, as described later.

In the configuration in which the bias voltage vbb is formed independently as in this embodiment, the information signal read from the dynamic memory cell is at a minute level, and the information signal read from the p-type well region pwell1 is not disturbed. This is advantageous in suppressing potential fluctuation. The circuit for forming the bias voltage vbb is obtained from the memory cell array by its p
Since the undesired leakage current flowing through the mold well region pwell1 is generally small and the output capability thereof can be relatively small, the power consumption of the device itself can be sufficiently reduced.

(Power supply initialization circuit VINTC) The power supply initialization circuit VINTC initializes the DRAM circuit under the operation control of the memory control circuit MCC. The configuration example of the power supply initialization circuit VINTC and the details of the initialization operation are not directly related to the present invention, and thus detailed description thereof is omitted.

In the above description, it is understood that the term "MOS" originally came to simply refer to a metal oxide semiconductor configuration. However, MOS by a general name in recent years includes those in which a metal in an essential part of a semiconductor device is replaced with a non-metal electric conductor such as polysilicon or an oxide is replaced with another insulator. I have. CMOS also uses M
It has come to be understood that it has a broad technical meaning according to the change in the way of thinking about the OS. MOSF
ET is not similarly understood in a narrow sense, but rather has a meaning including a broad sense of a configuration that can be considered as an insulated gate field effect transistor. The CMOS, MOSFET, etc. of the present invention follow a common name.

FIG. 13 shows a system L to which the present invention is applied.
1 is an overall circuit block diagram of an embodiment of an SI. The semiconductor integrated circuit device CHIP of the embodiment has a plurality of circuit blocks as shown in the figure, that is, an input / output circuit I / O, a substrate bias control circuit VBBC, a control circuit ULC, a read-only memory ROM, a D / A converter DAC, A / D converter AD
C, interrupt control circuit IVC, clock generation circuit CGC
Power management circuit SPMC having central processing unit, central processing unit CPU, static memory SRAM, DMA
Controller DMAC, Dynamic memory DRAM
including.

The circuit blocks are composed of an internal bus BU
S, which is coupled to the control bus CBUS. They are mounted on a semiconductor substrate (not shown) that forms a semiconductor integrated circuit device. The above system power management circuit SPM
C has a function of controlling power consumed in each module mounted on the system LSI.

The semiconductor integrated circuit device has an input / output circuit I / O
Input / output external terminals Tio1 to Tion connected to
An external terminal T1 to which a reset signal resb such as a negative logic level is supplied, a control external terminal T2, and a first operation control external terminal T3 to which a first operation control signal cmq is supplied.
A second operation control external terminal T4 to which the second operation control signal cpmq is supplied, a clock external terminal T5 to which the external clock signal clk is supplied, and a plurality of power supply voltages (vd
d, vccdr, vss) are supplied to the power supply external terminals T6, T7, T8.

Although not particularly limited, the power supply voltage vdd is
The power supply voltage is used for the operation of the internal circuit block.
Take a value like 8 volts ± 0.15 volts. The power supply voltage vccdr is a power supply voltage mainly set for the input / output circuit I / O according to the input / output level required for the semiconductor integrated circuit device, and is 3.3 volts ± 0.3 volts. It is made to take one of the values such as 5 volts ± 0.25 volts, and 1.8 volts ± 0.15 volts. The potential vss is a reference potential of a circuit which is called a so-called ground potential.

The illustrated semiconductor integrated circuit device has a so-called A
An SIC (Application Specific Integrated Circuits), that is, a special purpose IC is constituted. That is, most of the illustrated circuit blocks form so-called modules or macro cells as independent circuit functional units so as to facilitate the ASIC configuration. The size and configuration of each functional unit can be changed. AS
As the IC, circuit blocks that are not required by the electronic system to be realized among the illustrated circuit blocks can be prevented from being mounted on the semiconductor substrate. Conversely, a circuit block of a functional unit (not shown) can be added.

The semiconductor integrated circuit device is not particularly limited, but has a CMOS structure capable of a low power supply voltage so as to exhibit sufficient operation characteristics even under a low power supply voltage vdd such as 1.8 volts ± 0.15 volts. This is a semiconductor integrated circuit device.

The dynamic memory mounted on the semiconductor integrated circuit device may be operated by the power supply voltage vdd. However, in the semiconductor integrated circuit device of this embodiment, the power supply voltage vd
Along with d, a high power supply voltage generated from a voltage generation circuit operated by the power supply voltage vdd is used. In the dynamic memory, a circuit such as a row decoder for selecting a dynamic memory cell is operated at such a high power supply voltage, and the internal bus B of the semiconductor integrated circuit device is operated.
A circuit that inputs and outputs a signal to and from the US is operated by a power supply voltage such as a low power supply voltage vdd. This configuration increases the amount of charge as information provided to the dynamic memory cell. As a result, the information retention time characteristics of the dynamic memory can be improved. Similarly,
By driving the sense amplifier by the overdrive method using the boosted voltage vbs as described above, a high-speed read operation can be performed.

(Central Processing Unit CPU) Central Processing Unit CPU
Although not particularly limited, is configured similarly to a so-called microprocessor. That is, the central processing unit CPU
Although not shown in detail, an instruction register therein, a micro instruction ROM for decoding an instruction written in the instruction register and forming various micro instructions or control signals, an arithmetic circuit, a general-purpose register (RG6, etc.), an internal It has input / output circuits such as a bus driver and a bus receiver coupled to the bus BUS.

The central processing unit CPU reads an instruction stored in a read only memory ROM or the like, and performs an operation corresponding to the instruction. The central processing unit CPU captures external data input via the input / output circuit I / O,
Input / output of data to / from the control circuit ULC, reading of data such as fixed data required for executing instructions and instructions from the read-only memory ROM, D / A converter D
Supply of data to be subjected to D / A conversion to AC, reading of A / D converted data by A / D converter, static memory SRAM, dynamic memory DRAM
Read / write data to / from DMA controller D
It performs MAC operation control and the like. The control bus CBUS is used by the central processing unit CPU to control the operation of the illustrated circuit block, and is used to transmit a state instruction signal from a circuit block such as the DMA controller DMAC to the central processing unit CPU.

The central processing unit CPU performs necessary processing by referring to the operation control signal set in the instruction register RG5 or the like in the interrupt control circuit IVC via the internal bus BUS. The central processing unit CPU receives a system clock signal C2 generated from the clock generation circuit CGC, and operates at an operation timing and a period determined by the system clock signal C2.

The main part of the central processing unit CPU is constituted by a CMOS circuit, that is, a circuit composed of a pMOS and an nMOS. Although not particularly limited, a CMOS circuit constituting the central processing unit CPU is a CM (not shown).
A CMOS static circuit such as an OS static logic circuit or a CMOS static flip-flop capable of performing a static operation, and precharging of a charge to a signal output node and signal output to a signal output node are performed in synchronization with a system clock signal C2. Such a CMOS dynamic circuit.

The central processing unit CPU includes a clock generation circuit C
When the supply of the system clock signal C2 from the GC is stopped, the operation is stopped accordingly. In the stop state, the output signal of the dynamic circuit is undesirably changed by an undesired leak current generated in the circuit. A circuit such as a register circuit having a static flip-flop circuit configuration retains previous data even during a non-supply period of a system clock signal.

During the non-supply period of the system clock signal C2, signal level transition at various nodes in the static circuit inside the central processing unit CPU is stopped, and discharge or precharge at the output node in the dynamic circuit is not performed. Stopped. In this state, a relatively large current consumption, such as an operation current consumed by a CMOS circuit in an operation state, is supplied from a power supply line so as to give a signal displacement to stray capacitance and parasitic capacitance of various nodes and wirings connected to each node. The charge and discharge currents are substantially zero. From this, the central processing unit C
The PU flows only a small current equal to the leakage current of the CMOS circuit and enters a low power consumption state.

(Interrupt Control Circuit IVC) The interrupt control circuit IVC receives a reset signal such as a negative logic level at the external terminal T1, receives the first operation signal cmq via the external terminal T3, and receives via the external terminal T4. It receives the second operation control signal cpmq, and outputs a state instruction signal for instructing the operation state of the semiconductor integrated circuit device to the external terminal T2.
The interrupt control circuit IVC outputs the reset signal res
b, a register RG5 in which bits at respective positions are set corresponding to the operation control signals cmq and cpmq and the state instruction signal.

The state indicating signal in the register RG5 is
It is updated by the central processing unit CPU via the internal bus BUS. The operation control signals cmq and cpmq set in the register RG5 via the external terminals T3 and T4 are referred to by the central processing unit CPU via the internal bus BUS as described above.

Although not particularly limited, the interrupt control circuit I
The VC has a refresh address counter (not shown) therein for a refresh operation of the dynamic memory. The refresh address counter in the interrupt control circuit IVC operates in the first or third mode by the first and second operation control signals cmq and cpmq, that is, in the operation mode or the operation standby mode for the semiconductor integrated circuit device. If the mode is designated, the refresh address information is incremented and periodically updated based on the system clock signal from the clock generation circuit CGC.

(Clock Generation Circuit CGC) The clock generation circuit CGC receives the external clock signal clk via the external terminal T5, and forms a system clock signal C2 having a cycle corresponding to the external clock signal clk. In FIG. 12, the clock generation circuit CGC and the central control unit CPU
The system clock signal C2 is the same as the clock signal for a general processor because of the sequential operation of a circuit (not shown) in the central control unit CPU, although the signal line between the two is simplified. It should be understood that the signal comprises a polyphase signal.

The generation of the system clock signal C2 by the clock generation circuit CGC is performed when the mode signal MODE2 or the initial operation instruction signal IN responding to the first and second operation control signals cmq and cpmq from the interrupt control circuit IVC.
It is controlled by a control signal C1 such as TL and a control signal C3 from the central processing unit CPU. Operation control signal cmq
When the complete standby operation is instructed by the CPU, the central processing unit CPU performs necessary processing operations for shifting to the complete standby operation, including the operation of writing data to be statically stored in the static memory SRAM. Then, a control signal C3 for stopping the system clock generation operation is generated from the central processing unit CPU to the clock generation circuit CGC.

When the operation standby signal is instructed by the operation control signal cpmq, the central processing unit CPU includes a process of writing data to be held statically into the static memory SRAM, similarly to the complete standby operation. Such processing operations necessary for shifting to the operation standby operation are performed. The subsequent operation in this case is different from the case of the complete standby operation described above, in that the control signal C3 for selectively outputting the system clock signal from the central processing unit CPU to the clock generation circuit CGC is provided.
Is generated.

That is, from the clock generation circuit CGC to the interrupt control circuit IVC and the dynamic memory DRA
The supply of the system clock signal to M is continued, and the supply of the system clock signal to the other circuit blocks is stopped. When the operation control signals cmq and cpmq are changed to a state instructing the operation of the circuit, the clock generation circuit CGC changes the system clock signal C2 corresponding to the external clock signal clk by the corresponding control signal C1 from the interrupt control circuit IVC. It is controlled to occur.

(Input / output circuit I / O) Input / output circuit I / O
Receives a signal supplied from outside through a desired external terminal among the external terminals TiO1 to Tion, and outputs a signal to be output to a desired terminal among the external terminals TiO1 to Tion via the internal bus BUS. receive. The input / output circuit I / O has therein a control register RG4 such as a CMOS static circuit and a data register (not shown).

The control register RG4 is a central processing unit CPU
And the central processing unit CPU provides control data for the input / output circuit I / O, for example, control data such as a data input / output instruction and a high output impedance state instruction. The data register is used for transferring data between the external terminals Tio1 to Tion and the internal bus BUS. Bit width of external terminals Tio1 to Tion, that is, the number of terminals, and internal bus B
When the bit width of the US is different, the data register is made to have a bit number corresponding to the large bit width, and performs the bit number conversion according to the operation control by the central processing unit CPU.

For example, while the number of the external terminals Tio1 to Tion is 64, the internal bus BUS
Is a relatively large number such as 256 bits, the external terminal Tio has a 64-bit unit.
The serial data sequentially supplied to 1 to Tion are sequentially supplied to the data register under the serial-parallel data conversion control by the central processing unit CPU, and are converted into 256-bit data. Conversely, the 256-bit data set in the data register from the internal bus BUS is converted by the central processing unit CPU into parallel-serial data conversion control.
External terminals TiO1 to Ti0 are divided every 64 bits.
ON are sequentially supplied.

The circuit for inputting signals and the circuit for outputting signals of the input / output circuit I / O have their input and output operations controlled by the system clock signal. Therefore, when the system clock signal is no longer supplied, the input / output circuit I / O outputs the central processing unit CP.
As in the case of U, a low power consumption state is set.

(Control Circuit ULC) The control circuit ULC is a control circuit appropriately provided according to the needs of the electronic system. The control circuit ULC includes, for example, an electronic system to be realized such as a motor servo control in a hard disk device, a head tracking control, an error correction process, and a compression / expansion process of image and audio data in image and audio processing. It is provided appropriately according to. The operation of the ULC of the control circuit is controlled by a system clock signal, similarly to the central processing unit CPU.

(Read Only Memory ROM) As described above, the read only memory ROM is a central processing unit CPU.
The instruction to be read out and executed, and the fixed data are stored.

(D / A converter DAC) D / A converter DA
C has a register RG2 for receiving digital data to be converted into an analog signal supplied via the internal bus BUS, and forms an analog signal based on the digital data. The register RG2 includes a control circuit ULC
Alternatively, digital data is set by the central processing unit CPU. D / A conversion start timing of the D / A converter DAC, D / A conversion output timing of the D / A conversion result, etc.
The A conversion operation is controlled by a system clock signal. The analog signal formed by the D / A converter DAC is supplied to desired terminals of the external terminals T1 to Tn via the internal bus BUS and the input / output circuit I / O. Although the external terminals T1 to Tn are used as input / output terminals (pins) here, they may be provided separately for input terminals and output terminals.

The D / A converter DAC is not shown in detail, but when high-precision DA conversion is required,
A reference voltage source or a reference current source is used as a reference for an analog quantity to be obtained. Such a reference voltage source or a reference current source is considered to constitute a kind of analog circuit, and there is a danger of consuming a non-negligible current in the second mode and the third mode, that is, the complete standby mode and the operation standby. Have. Therefore, in order to reduce the current consumption in such a case, the second reference
In the mode and the third mode, a MOSFET switch which is turned off is set.

(A / D converter ADC) A / D converter AD
C receives a desired one of the external terminals T1 to Tn, an analog signal supplied via the input / output circuit I / O and the internal bus BUS, and receives the A / A signal by the control circuit ULC or the central processing unit CPU. The start of D conversion is controlled, the analog signal is converted into a digital signal under clock control according to the system clock signal C2, and the obtained digital signal is set in a register RG1.

Similarly to the D / A converter DAC, the A / D converter ADC also has a criterion such as a reference for a quantization level to be digitally converted when high-precision A / D conversion is required. It has a voltage source or a reference current source. Such a reference voltage source or reference current source in the A / D converter ADC also has the risk of consuming considerable current in the full standby mode and the operation standby mode. Therefore, in that case, the MO
An SFET switch is applied to such a reference voltage or current source.

(Static memory SRAM) The static memory SRAM is a CMOS static memory cell, that is, a CMOS latch circuit and a pair of transmission data for data input / output with respect to the CMOS latch circuit. It has a memory cell configured as a MOSFET. The CMOS static memory cell has a feature that it stores information in a static manner and requires a remarkably small operating current to hold the information.

Such a static type memory SRAM is
Practically, it constitutes a CMOS static random access memory. That is, the static memory SRAM includes a plurality of CMs arranged in a matrix.
A memory array comprising OS static memory cells;
A row address decode / drive circuit for decoding a row address signal supplied through the internal bus BUS and thereby selecting a word line in the memory array; and decoding a column address signal and thereby a column decode signal. A column address decode circuit to be formed, a column switch circuit operated by such a column decode signal to select a data line in the memory array and couple it to a common data line, and an input / output circuit coupled to the common data line; And a read / write control circuit.

The address associated with the memory array
A circuit such as a decode drive circuit, that is, a memory array peripheral circuit is constituted by a CMOS static circuit. Therefore, the static memory cell SRAM is placed in a relatively low power consumption state if only the information holding operation in which the reading and writing operations are not performed. Note that the CMOS static memory has a feature to be considered that the memory cell size is relatively large and the overall size is relatively large with respect to the storage capacity, and it is relatively difficult to increase the storage capacity. is there.

(DMA Controller DMAC) A DMA controller, that is, a direct memory access
The operation of the controller DMAC is controlled by the central processing unit CPU, and controls data transfer between the circuit blocks specified by the central processing unit CPU via the internal bus BUS instead of the central processing unit CPU. DMA
Since the details of the controller DMAC can be substantially the same as that of the DMA controller configured as an independent semiconductor integrated circuit device, further detailed description will not be given. However, the central processing unit CPU Data transfer control is performed based on setting information such as transfer source information, transfer destination information, and data transfer amount information that are set.

(Dynamic Memory DRAM) In a dynamic memory DRAM, its memory cell, that is, a dynamic memory cell, typically includes an information storage capacitor for storing information in the form of electric charge and a selection MOSFET. With such a small number of elements, a relatively small memory cell size can be achieved. Therefore, the dynamic memory can have a relatively small overall size even with a large storage capacity. As this dynamic memory DRAM, the one shown in FIG. 12 is used.

FIG. 1 shows the dynamic memory DRA.
FIG. 3 is a block diagram illustrating an embodiment of a voltage conversion circuit provided in M. This voltage conversion circuit is operated with the power supply voltage vdd and the ground potential vss of the circuit, and is reduced to half of the boosted voltages vbs, vdh, the negative voltage vbb, and the power supply voltage vdd, which are higher than the power supply voltage vdd. Plate voltage vp
1, four kinds of voltages consisting of the bit line precharge voltage vbm are formed.

The boosted voltage vbs is an operating voltage for overdrive of the sense amplifier, vdh is an operating voltage of a word line driver forming a word line selection signal, and vbb is a negative back bias applied to the substrate. Voltages, which are all formed using a charge pump circuit. On the other hand, the plate voltage vpl and the bit line precharge voltage vbm are formed by dividing the power supply voltage vdd by half.

A bit line to which a dynamic memory cell is connected has a relatively large parasitic capacitance by connecting a large number of such memory cells. In order to raise the potential of the bit line having such a relatively large parasitic capacitance at a high speed by the amplification operation of the sense amplifier, the boosted voltage vbs which is a substantial operating voltage during the amplification operation is used.
Requires a relatively large current driving capability. The timing at which such a current is required is limited to a certain time at the start of the operation of the sense amplifier.

The sense amplifier always operates when a word line is selected, and the information charge of the capacitor in the memory cell decreases or increases due to the charge dispersion with the precharge charge of the bit line due to the word line selection operation. Amplify the read signal generated by such charge dispersion,
The operation of returning the information charge of the memory cell to the original state is performed. In other words, the amplification operation of the sense amplifier
The operation of selecting a word line, in other words, the operation of selecting a row system is performed integrally.

In this embodiment, in order to efficiently form the boosted voltage and stabilize the boosted voltage, the boosted voltage vbs, which is the substantial operating voltage of the sense amplifier in the dynamic RAM, is selected by the row system. I thought about making it work according to the timing. That is, in the amplifying operation of the sense amplifier, the boosting voltage vbs formed by the charge pump circuit is generated by the current for charging the bit line up to the power supply voltage vdd level as described above.
, The charge pump operation is performed so as to compensate for this in advance.

The charge pump circuit performs a precharge operation on the capacitor, which is a preparatory operation for obtaining a boosted voltage, and boosts the voltage formed by the charge precharged on the capacitor by the bootstrap function to increase the voltage on the output side of the capacitor. This is performed by repeating the output operation of transferring the data. Therefore, when the charge pump circuit is operated by the bank activation signal, it is necessary to spend two cycles for the precharge operation and the output operation of one charge pump circuit. In order to perform the above output operation in response to continuous bank access, at least four charge pump circuits are required.

In addition to this, this embodiment provides an operation mode in which two banks are activated simultaneously, as described later. In this case, the two banks are activated at substantially the same time, and the operating current of the sense amplifier is doubled accordingly. Therefore, one charge pump circuit for the simultaneous activation of two banks is added, and a vbs power supply circuit including a total of five charge pump circuits is provided. These vbs power supply circuits are sequentially operated by the input timing signals clkbs <0> to <4>.

A total of five vbs power supply circuits having a vbs detection circuit are provided, and the timing signal clkb is provided.
boosted voltage vb formed by s <0> to <4>
When s is insufficient, the vbs power supply circuit enabled by the detection signal of the detection circuit outputs the timing signal c
It is additionally operated by lkbs <0> to <4>. In response to such a level of the output boosted voltage vbs, when one bank is activated, the vbs power supply circuit including the vbs detection circuit and the always-on operation operates. Also, as described later, when two banks are simultaneously activated, the two vbs power supply circuits that are always operating and correspond to the respective bank activation signals, and the vbs power supply circuit with the vbs detection circuit also operates when the boosted output voltage vbs is insufficient. A maximum of four circuits operate in a state.

By controlling the operation of the vbs power supply circuit, a small number of charge pump circuits can be used, and the fluctuation of the boosted voltage vbs can be minimized to stably increase the boosted voltage vbs.
bs can be formed. As described above, the boost voltage v
Since bs is a power supply voltage at the start of the amplification operation of the sense amplifier and overdrives the sense amplifier, the voltage change greatly changes the amplification time of the sense amplifier. By employing the power supply circuit as in this embodiment, the boosted voltage vbs can be stabilized, so that the substantial amplification operation of the sense amplifier can be performed at high speed.

The boost voltage vdh forming the word line selection level is formed by three vdh power supply circuits c-0 to c-2. Similarly, a vbb power supply circuit for forming a negative substrate voltage vbb is also formed by three circuits d-0 to d-2. Three-phase clock signals clk <0> to <2> are formed corresponding to these three circuits. Each clock signal clk <0> or <2>
Is a three-phase signal having a pulse duty of 33%. The high-level signal is precharged and the low-level signal is output. Therefore, the output period is twice as long as the precharge period, and the boosted or negative voltage held in the capacitor can be output for a long time. As a result, an efficient voltage generation operation can be performed as a charge pump circuit.

The vbm / vpl power supply circuit for forming a half of the power supply voltage vdd has a small output current, so that each of them is constituted by an output circuit. Since the two voltages vbm and vpl are set to the same voltage like vdd / 2, they are configured by a common circuit except for the output unit.

FIG. 2 is a timing chart for explaining the operation of the vbs power supply unit. The row-related commands include a bank active (bank active) and a bank active close (bank active / close). An X address signal and a row bank address are designated by bank active, a bank (memory mat) designated by the row bank address is activated, and a word line designated by the X address signal is selected and sensed. The amplifier is activated. This command (BA) is applied to / CA in a general-purpose DRAM.
When the S (column address strobe) signal is high level,
/ RAS (row address strobe) signal falls. That is, a row-related selection operation is performed, and a refresh operation is performed on the memory cells of the selected word line in the designated bank.

The X address signal is ignored by the bank active close, and the bank specified by the row bank address is precharged. That is,
While the selected word line is deselected, the sense amplifier SA is inactivated, and the complementary bit line and the common source line of the sense amplifier are set to the half precharge potential.

In this embodiment, there is provided an operation mode in which a bank active close command is not issued one by one, and it is only necessary to arbitrarily designate a bank in which read data exists. On the other hand, this operation mode is delayed by the time period from when the bank active is input to when the data is output to when the bank active close operation is automatically performed. On the other hand, after reading (or writing) of necessary data is completed, when a bank active close (BC) command is issued to the bank one by one, from the input of bank active to the output of data. Time can be faster.

In accessing a memory composed of a plurality of banks, an address corresponding to bank active / close using the above-mentioned command is used.
(Actlve to active) signal, ctam (close to activ)
e) The timing signals bs0 to bs4 are formed by pulses synchronized with the signals. Where atam or ct
m in am means that the signal is a signal corresponding to the m-th memory bank out of a maximum of 16 memory banks.

In FIG. 10A, ata (actlve to acti)
ve), and bs0 to bs4 are sequentially generated in synchronization with the change (rise and fall) of the ata signal. In the state of “ata”, the bank active is automatically executed as described above, and then the bank active is performed. Therefore, the timing is delayed by that amount. Charge pump circuits operate sequentially to increase the boosted voltage vbs
To form

In FIG. 10C, cta (close to activ
e), and in synchronism with the change (rising and falling) of the cta signal, bs0 to bs0 are sequentially
bs4 is generated. In the state of cta, since the bank active close is executed as described above,
The bank active timing is immediately performed, and in synchronization with the timing ctam, a total of five charge pump circuits sequentially operate to form the boosted voltage vbs.

In FIGS. 9B and 9D, ata (actlve
to active) and cta (close to active) are simultaneously activated and two banks are activated at the same time. Due to the time difference between the signals cta and ata as described above,
The vbs control unit generates pulses bs2 and bs3, bs1 and bs2, etc. continuously within a short time to prevent a drop in vbs when two banks are activated. In this case, two charge pump circuits operate simultaneously during one bank active period. Vbs by the sense circuit
Is determined to be insufficient, two more charge pump circuits operate simultaneously.

FIG. 3 is a timing chart of the clock generation circuit shown in FIG. 1, and FIG. 4 is a circuit diagram thereof.
The clock generation circuit includes the vdh power supply unit and vbb
Clock signal clk <0> or <
2> to perform the operation. As shown in the timing diagram, the input clock signal mclk is set to 3
The phase clock signals clk <0> to <2> are formed. Therefore, each of the clock signals clk <0> to <2
> Have approximately 33% pulse duty.

In FIG. 4, the clock signal mclk is
A ternary counter circuit is formed by a combination of a flip-flop circuit and a flip-flop circuit with a delay output, and its output is stored in a flip-flop circuit operated by an inverted signal of the clock signal mlk. The outputs of the circuits are combined and input to the logic gate circuit to form the three-phase clock signals clk <0> to <2> as described above.

As described above, each charge pump circuit has a clock signal clk <0> or <2> corresponding to the charge pump circuit.
Performs a precharge operation during a high level period, and performs an output operation during a low level period. Therefore, the output time can be twice as long as the time of the precharge operation, and the two charge pump circuits can have a period during which the output operation is performed at the same time. As a result, it is possible to form the boosted voltage vdh and the substrate voltage vbb with high efficiency while minimizing the voltage fluctuation. V of this embodiment
In the dh power supply unit and the vbb power supply unit, the boosting / transfer ratio is controlled by a clock of 1: 2, and the overlapping of the transfer periods is formed by a three-phase clock structure so that the boosting can be continued, so that the efficiency of the charge pump circuit is improved. It is intended to make it.

FIG. 5 is a circuit diagram showing one embodiment of the vbb power supply circuit. In the figure, a P-channel MOSFET QC52 and an N-channel MOSFET
The QC 53 forms a ground switch in a parallel configuration, and forms a transfer gate from which the N-channel MOSFET QC 58 outputs a negative voltage. When the inverter circuit INV51 is at a high level by the input clock signal clk,
The power supply voltage vdd is precharged to the capacitor QC61.

In the precharge, a negative voltage for turning on the P-channel MOSFET QC52 is generated by the latch-type P-channel MOSFETs QC50 and QC51 and the capacitors QC62 and QC63. That is, the negative voltage formed by the capacitor QC63 turns on the P-channel MOSFET QC52, turns on the latch-type P-channel MOSFET QC50, turns off the other P-channel MOSFET QC51, and turns off the negative voltage. This prevents the potential from falling to the ground potential vss.

In the output operation, the inverter circuit INV5
6 becomes low level (ground potential vss),
The latch type N-channel MOSFET QC54 is turned on, and the capacitor QC64 is charged with the negative voltage vbn. Therefore, when the output signal of the inverter circuit INV56 becomes a high level such as the power supply voltage vdd during the precharge, the gate voltage of the N-channel type switch MOSFET QC53 becomes v
dd-vbn to be turned on. At this time,
When the N-channel MOSFET QC55 is turned on, the capacitor QC65 is precharged with the negative voltage vbn, and the other MOSFET QC54 is turned off so that the voltage vdd-vbn does not drop to the negative voltage vbn.

When the inverter circuit INV51 changes to the low level, the electric charge precharged to the capacitor QC61 and the electric charge are transferred to the capacitor QC60, and a negative voltage reduced according to the capacitance ratio is generated. This negative voltage is output through an N-channel transfer gate MOSFET QC58 which is turned on at this time. The signal for turning on the transfer gate MOSFET QC58 is a latch-type MOSFET Q consisting of a circuit similar to a circuit for forming a control signal for the MOSFET QC 53.
C56 and QC57 and capacitors QC66 and QC67. In this embodiment, after the negative voltage is reduced by the above-described capacitance ratio, the MOSFET QC 58
Is transferred to a parasitic capacitance or the like in a substrate or a well region (not shown) and a desired substrate voltage vbn (for example, -0.75
V), so there is no waste.

When the power supply voltage vdd is as low as 1.8 V, the ground switch is connected to an N-channel type MOS.
If only the FET QC53 is used, only a low voltage of about 1 V can be applied to its gate. For this reason, the conductance becomes small, and the precharge operation to the capacitor QC61 becomes insufficient.
3 or a large number of charge pump circuits. On the other hand, when the P-channel MOSFET QC52 is connected in parallel, the power supply voltage vd
Since a negative voltage corresponding to d can be supplied to turn on, a relatively large current can flow. Therefore, in the above-described parallel configuration, particularly the low power supply voltage vd
Under the condition d, the negative voltage vbn can be efficiently formed with a simple configuration.

FIG. 6 is a circuit diagram showing one embodiment of the vbs power supply circuit. The vbs power supply circuit of this embodiment is designed as follows to efficiently generate the boosted voltage vbs under the low power supply voltage vdd.
In this embodiment, the transfer gate for outputting the boosted voltage formed by the booster has a parallel configuration of a P-channel MOSFET and an N-channel MOSFET. The booster is
It is composed of a capacitor C0 and an inverter circuit. In the precharge operation for the capacitor C0, a double boosted voltage is similarly formed, and an N-channel type precharge MOSFE
The gate voltage of T is set at 2 vdd so that the precharge operation can be performed at high speed and efficiently.

The double boosted voltage 2vdd formed by the capacitor C0 is a double boosted voltage 2vdd formed by a circuit composed of the capacitors C1 and C2 and the latch type N-channel MOSFETs Q1 and Q2. The transmission gate MOSFET is turned on to output. At the same time, a P-channel transmission gate MOSF
The ET is switched by a circuit formed by a latch-type P-channel MOSFET and a capacitor to perform the output operation. P-channel type switch MOSF
ET is a difference voltage v between the boosted voltage vbs and the power supply voltage vdd.
bs-vdd is supplied to the gate to be turned on. P
Since the boosted voltage 2vdd is supplied to the source of the channel type MOSFET, the voltage between the gate and the source becomes 3
A voltage such as vdd-vbs is applied.
The P-channel MOSFET and the N-channel MOSFET in the above-described parallel configuration form an N-channel MOSFET.
Since the boosted voltage 2vdd can be fully output without voltage loss due to the threshold voltage as in the case of using an FET, the boosting efficiency can be improved.

FIG. 7 is a circuit diagram showing one embodiment of the vdh power supply circuit. Under the low power supply voltage vdd,
The following contrivance has been made to efficiently form the boosted voltage vdh. In this embodiment, the boosting section is set to double boosting. That is, the capacitors C3 and C4 are precharged with the power supply voltage vdd, respectively, and connected in series to form a double boosted voltage 2vdd with the capacitors C3 and C4. By adding the high level (vdd) of the output voltage of the inverter circuit to this,
A triple boosted voltage 3vdd is formed.

The first-stage transfer gate forms a precharge signal for the capacitors C3 and C4. The next-stage transfer gate outputs the boosted voltage of the node n1 from which the triple boosted voltage 3vdd is obtained from the output terminal vdh. It is a transfer gate to make it. As the output transfer gate, a CMOS transfer gate using an N-channel MOSFET and a P-channel MOSFET is employed as in the embodiment of FIG. The combination of the tripled boosted voltage and the CMOS transfer gate makes it possible to supply the power supply voltage v
Even when the dd is as low as 1.8 V, the efficiency is 3.6 V.
It is possible to form a high voltage to the level of the word line selection level.

The delay circuits for forming the timing signals in FIGS. 5 to 7 are for forming non-overlapping complementary pulses, and are provided with MOS transistors in the form of latches.
When the operation of the FET is switched, the boosted voltage becomes the power supply voltage vdd.
Or to the ground potential vss.

That is, as shown in the timing chart of FIG. 8, based on the clock signal clk, each signal f0, its delay signal f0d, f1, its delay signal f1d, fs1, and its delay signal fs1d are formed. As shown by the dotted lines in the drawing, the signals s1 and s1b, s2 and s2b, and s3 and s3b are mutually non-overlapping and non-overlapping signals. The latch-type MOSFET is a timing signal transmitted to a connected capacitor.

In FIG. 7, the sensor circuit is a sensor circuit for monitoring the boosted voltage vdh without passing a direct current, and the boosted voltage vdh is connected to the diode-connected P in FIG.
The level-shifted voltage vdhd composed of the channel type MOSFET Q2 is taken in as an input voltage to be detected.

At the first timing, the node h is set to the low level by the clock signal clk to precharge the capacitor, the node g is precharged with the input voltage vdhd, and the capacitor and the node g are connected at the second timing. Is connected, and the potential of the node g is changed by a P-channel MOSFET that flows a current by a difference voltage between the input voltage vdhd and the power supply voltage vdd based on the voltage corresponding to the charge dispersion, and this is changed to the logic of the NAND gate circuit. Judge by the threshold voltage. Thus, in the sensor circuit,
Since a direct current path is not constantly formed, the boosted voltage vdh can be monitored with low current consumption.

FIG. 9 is a timing chart for explaining the operation of the sensor circuit. FIG. 9A shows a case where the vdh level is equal to or higher than the set value. The capacitor and the node g during the high level period of the signal a
Are combined with each other to cause charge dispersion and lower the potential of the node g. When the power supply voltage vdd is supplied to the gate, the potential of the node g is turned on in response to the potential difference from the detection voltage vdhd, and a P-channel MOSFET having a relatively large resistance value is turned on. It rises due to the charging current from the passed input voltage vdhd.

The operation of the NAND gate circuit is validated by the change of the signal b to the high level, and an output signal corresponding to the potential of the node g is formed. If the vdh level is equal to or higher than the set value as described above, the P-channel type M
Since the current from the OSFET is relatively large, the rise of the node g becomes faster and reaches the logical threshold voltage of the NAND gate circuit, and the potential of the output signal k decreases to form a low level signal. By the low level of the signal k, the timing signals s2, s2b and s3 and s3b are stopped,
Stop the operation of the charge pump circuit.

FIG. 9B shows a case where the vdh level is lower than the set value. When the vdh level is low, the input voltage vdh level-shifted accordingly.
d also decreases, and the potential difference from the power supply voltage vdd decreases. Therefore, the power supply voltage vdd is supplied to the gate, and the detection voltage vdhd is supplied to the source.
The current formed by the channel type MOSFET becomes small, and the potential of the node g is kept as it is.

The operation of the NAND gate circuit is validated by the change of the signal b to the high level, and when the potential of the node g does not change as described above, the NAND gate circuit remains at the logical threshold voltage of the NAND gate circuit or lower. Then, the output signal k is kept at the high level. In this state, since the timing signals s2, s2b, and s3 and s3b are formed, the charge pump circuit is activated and operates to increase the boosted voltage vdh. The sensor circuit includes:
It is also used in the vbs power supply circuit of FIG. However, in FIG. 6, the vbs voltage is monitored as an input voltage.

For example, in a high resistance type voltage division type static sensor circuit in which a MOS is connected to a series, the boosted voltage is reduced by a DC current, the charge pump circuit operates more than necessary, and the consumption current is large. Become. In this embodiment, each gate of the NMOS voltage division type is alternately switched. In the dynamic sensor based on the charge / discharge of the capacitance, for example, when the boosted level reaches a set value, the output node k goes low, the output of the flip-flop circuit FF goes low, and clk is not applied to the charge pump. . On the other hand, when the boost level falls below the set value, the output node k goes high, and the flip-flop circuit F
The output of F goes high, applying clk to the charge pump. By making such a sensor circuit operate dynamically, DC current can be cut and power in long cycle operation can be minimized.

FIG. 10 is a circuit diagram showing one embodiment of the vbm / vpl power supply circuit. The power supply voltage vdd is divided by a capacitor to form a voltage of vdd / 2, and a voltage which is leveled up by a diode-connected N-channel MOSFET around the center is applied to the gate of the N-channel MOSFET. Output voltages vpl and vbm are applied to the sources, respectively, and the N-channel MOSFET
Is turned on to charge a current from the power supply voltage vdd for correction. A voltage obtained by lowering vdd / 2 by a diode-connected p-channel MOSFET is applied to the gate of the P-channel MOSFET, and the MOSFET
Output voltages vpl and vbm are applied to the source of T, respectively, and the P-channel MOSFET
T is turned on to extract the current so as to lower the output voltages vpl and vbm.

In this embodiment, the ground potential and the power supply voltage vdd are charged up in the capacitors C10 and C12, respectively, during one level of the clock signal clk, and connected to the output point during the other period. vb
This prevents a sharp change in m / vpl. When the signal rsp is set to the low level, the above circuit stops its operation and cuts off the current path. Also, the signal wbib
Resets the output vpl / vbm to the ground potential of the circuit.

FIG. 11 shows the output characteristics of each of the power supply circuits. The power supply circuit of this embodiment has a power supply voltage vdd = 1.8 V, 25 with respect to the application of the external clk and the waiting time.
The temperature reaches a predetermined level in approximately 30 μs at 50 ° C. and a clk cycle time of 50 MHz. That is, under the power supply voltage vdd, the boosted voltage vdh that determines the word line selection level is set to 3.3 V, the overdrive voltage of the sense amplifier, in other words, the boosted voltage vbs of the bit line.
To 2.7V, bit line precharge, plate voltage v
bm / vpl to 0.9 V and substrate voltage vbb to-
It is set to 0.75V.

The effects obtained from the above embodiment are as follows. That is, (1) the first capacitor is charged up by the precharge circuit in response to the first timing, and the first capacitor is charged via the transfer gate in response to the second timing.
In the charge pump circuit for transferring the electric charge accumulated in the capacitor to the second capacitor holding the output voltage, either the precharge circuit or the transfer gate is a P-channel MOSFET and an N-channel MOSFET.
By configuring with a parallel circuit of ET, the precharge operation or the transfer operation can be performed efficiently even at a low voltage, and as a result, a desired output voltage can be obtained with a simple configuration.

(2) The first timing period and the second timing period
Is set to 1: 2, the charge held in the capacitor can be taken out as an output current without waste, and as a result, the efficiency of the charge pump circuit can be improved. Is obtained.

(3) A memory array in which dynamic memory cells for storing data are arranged in a matrix, a row decoder and a column switch for selecting the dynamic memory cells, and the selected dynamic memory cells The present invention is applied to a dynamic RAM having a sense amplifier for amplifying read data read out, and the charge pump circuit is used to select a word line selection signal formed by the row decoder and a sense amplifier overdrive. A high voltage higher than the power supply voltage used is formed, and an N-channel MOS
By forming a negative substrate back bias voltage applied to the semiconductor substrate or the well region where the FET is formed, it is possible to obtain the effects of increasing the operation speed, securing the memory retention time, and reducing power consumption. Can be

(4) A memory array including a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, and an address selection circuit for performing an operation of selecting the word lines and the bit lines. As a power supply circuit of a RAM module including a plurality of memory mats and a control circuit provided in common for the plurality of memory mats, thereby increasing the speed of operation, securing memory retention time, and reducing power consumption. Is obtained.

(5) An operation mode is provided in which the plurality of memory mats constitute a plurality of banks and a row-related circuit selection operation is simultaneously activated for the two banks, and the overdrive potential of the sense amplifier is reduced. Five charge pump circuits to be formed are sequentially operated in accordance with the bank operation detection signal, so that a small number of charge pump circuits can be used to cope with each bank activation and to simultaneously charge two banks at the same time. Since the output operation of the pump circuit can have a period during which the output operation overlaps, the operation can be stabilized, and the row-system selection operation can be speeded up.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the storage capacity of the memory array provided in one memory mat can take various embodiments. The memory array has a sense amplifier, precharge circuit,
And a shared sense amplifier system in which column switches are arranged and memory cells are arranged on both sides.

The pulse generating circuit for forming a pulse to be supplied to the charge pump circuit is a self-excited circuit such as a ring oscillator from a circuit mainly including a frequency dividing circuit receiving the external clock signal clk as a frequency dividing pulse. It can be composed of a circuit mainly including an oscillation circuit. Such an alternative configuration is effective, for example, when generating a pulse signal having a frequency significantly lower than the frequency of the external clock signal clk. That is, when the external clock signal clk is set to a high frequency due to a system request or the like, the operating frequency of the pulse generation circuit PGC can be reduced regardless of the external clock signal clk, and the power consumption can be reduced. Can benefit.

The memory mat mounted on the RAM module may use a static memory cell in addition to the dynamic memory cell as described above, or may use a cell such as a nonvolatile memory. It may be used. INDUSTRIAL APPLICABILITY The present invention can be widely used for a semiconductor integrated circuit device provided with a power supply circuit that forms a voltage higher than a power supply voltage by using a charge pump circuit or generates a voltage having a polarity opposite to the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a voltage conversion circuit provided in a dynamic memory DRAM.

FIG. 2 is a timing chart for explaining an operation of the vbs power supply unit of FIG. 1;

FIG. 3 is a timing chart of the clock generation circuit of FIG. 1;

FIG. 4 is a circuit diagram of the clock generation circuit of FIG. 1;

FIG. 5 is a circuit diagram showing one embodiment of a vbb power supply circuit of FIG. 1;

FIG. 6 is a circuit diagram showing one embodiment of the vbs power supply circuit of FIG. 1;

FIG. 7 is a circuit diagram showing one embodiment of a vdh power supply circuit of FIG. 1;

FIG. 8 is a timing chart for explaining the operation of the vdh power supply circuit of FIG. 7;

FIG. 9 is a timing chart for explaining the operation of the sensor circuit of FIG. 7;

FIG. 10 is a circuit diagram showing one embodiment of a vbm / vpl power supply circuit of FIG. 1;

FIG. 11 is a characteristic diagram of the power supply circuit according to the present invention.

FIG. 12 is a block diagram showing an embodiment of a dynamic memory mounted on a semiconductor integrated circuit device to which the present invention is applied.

FIG. 13 is an overall circuit block diagram showing an embodiment of a system LSI to which the present invention is applied.

[Explanation of symbols]

IO: input / output circuit, VBBC: substrate bias control circuit,
ULC: control circuit, ROM: read-only memory, DA
C: D / A converter, ADC: A / D converter, IVC: Interrupt control circuit, CGC: Clock generation circuit, CPU ...
Central processing unit, SRAM: Static memory, DMA
C: DMA controller, DRAM: Dynamic memory, BUS: Internal bus, CLC: Logic circuit, VL & CL
... wiring group, MA ... memory array, SA ... sense amplifier,
CS ... column switch, TC ... column secretor, RD ...
Row decoder, M-IO ... memory input / output circuit, VBBM
... Substrate bias switching circuit, IMVC ... Internal power supply circuit, M
MC: memory control circuit, VINTC: power supply initialization circuit,
IMVC: voltage conversion circuit, ADCB: address, control bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Sasaki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group of Hitachi, Ltd. (72) Inventor Yoshihiko Yasu Gojokamicho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Group (chome 20-1) (72) Inventor Kazumasa Yanagisawa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Company (72) Inventor Yuji Tanaka Tokyo Hitachi, Ltd. Semiconductor Group, Ltd. (72) Inventor Yasuto Igarashi 5-2-1, Kamizuhoncho, Tokyo, Japan 72) Inventor Hitoshi Tanaka 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems (72) Inventor Mariko Otsuka 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super SII Systems 5B024 AA01 AA15 BA09 BA10 BA13 BA23 BA27 CA07 CA16

Claims (6)

[Claims] 1. A precharge circuit for charging up a first capacitor in response to a first timing, and being turned on in response to a second timing to be turned on.
A transfer gate circuit for transferring the charge stored in the capacitor to a second capacitor for holding an output voltage, wherein one of the precharge circuit and the transfer gate circuit is a first conductive type of a parallel type. A semiconductor integrated circuit device comprising a charge pump circuit composed of one MOSFET and a second MOSFET of a second conductivity type. 2. The charge pump circuit according to claim 1, wherein the charge pump circuit operates at a positive power supply voltage, and supplies the boosted voltage raised above the power supply voltage to a semiconductor substrate or a well region where an N-channel MOSFET is formed. A negative substrate back bias voltage to be applied to the semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein a ratio between the first timing period and the second timing period is set to 1: 2. 4. The memory array according to claim 1, wherein a dynamic memory cell for storing data is arranged in a matrix, a row decoder and a column switch for selecting the dynamic memory cell. And a dynamic RAM having a sense amplifier for amplifying read data read from the selected dynamic memory cell. The charge pump circuit further comprises a word line selection signal formed by the row decoder. And a semiconductor substrate or a well region in which an N-channel MOSFET is formed. Forming a given negative substrate back bias voltage The semiconductor integrated circuit device characterized by comprising. 5. The dynamic type R according to claim 4,
The AM includes a memory array having a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, and a plurality of memory mats including an address selection circuit for selecting the word lines and the bit lines. And a RAM module including a control circuit commonly provided for the plurality of memory mats. 6. The plurality of memory mats according to claim 5, wherein the plurality of memory mats constitute a plurality of banks, and the selecting operation of the row-related circuit includes an operation mode for simultaneously activating two banks. A semiconductor integrated circuit device comprising: five charge pump circuits for forming an overdrive potential of a sense amplifier, which are sequentially operated in response to a bank operation detection signal.