JP2000305530A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: Provided is a liquid crystal display device using a timing control unit 5 that can be commonly used for a one-channel or two-channel data bus configuration and capable of reducing the number of components. SOLUTION: A TFT liquid crystal display panel including a liquid crystal display element and a TFT matrix driving section for scanning and driving the liquid crystal display element, a timing control section 5 for supplying a drive signal to the TFT liquid crystal display panel, and one or two of the timing control sections 5
A liquid crystal display device comprising a host control unit for supplying one-channel or two-channel display data signals via one data bus, wherein a timing control unit 5 is provided with an S / P conversion unit 1
0 and one or more signal selection units 9 ₁ and 9 ₂ are provided, and the host control unit supplies a switching signal corresponding to the supply of the display data signal of one channel or two channels to the timing control unit 5, and the timing control unit The switching unit 5 switches the signal selection units 9 ₁ and 9 _{2 according} to the switching signal, and outputs a display data signal of one or two channels as a drive signal of the same format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a case where a host control unit supplies a one- or two-channel display data signal to a timing control unit. The present invention relates to a liquid crystal display device capable of forming a drive signal for a thin film transistor liquid crystal display panel regardless of the type of a display data signal.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device comprises a liquid crystal display element and a thin film transistor (T) for scanning and driving the liquid crystal display element.
FT) a TFT liquid crystal display panel including a matrix driving unit, a timing control unit connected to the TFT liquid crystal display panel and supplying a driving signal to the TFT liquid crystal display panel, and a data bus connected to the timing control unit via a data bus. And a host control unit for supplying a display data signal to the timing control unit via the control unit. In the known liquid crystal display device, when transmitting a display data signal from the host control unit to the timing control unit via the data bus, a low-voltage data signal transmission unit (LVDS Tx) is provided on the host control unit side. The low voltage data signal receiving section (LVDS Rx) is disposed on the timing control section side. The low voltage data signal transmitting section transmits a display data signal through a data bus, and the low voltage data signal receiving section is disposed. The display data signal transmitted through the data bus is received.

The low-voltage data signal transmitting section and the low-voltage data signal receiving section used in this known liquid crystal display device initially have a data transmission frequency set to 33 MHz, and have recently become mainstream. A data transmission frequency set at 65 MHz has been developed, and in the near future, a data transmission frequency of 140 MHz has been set.
There is an increasing sign that the frequency set to Hz will be put to practical use.

By the way, the data transmission frequency is 33 MHz.
When using a low-voltage data signal transmission unit and a low-voltage data signal reception unit to display an extended graphic array (XGA) on a liquid crystal display panel, the low-voltage data signal transmission unit and the low-voltage data signal reception unit are compared with the display speed. , The number of bits (18 bits × 2) is set to twice the normal number of data bits (18 bits × 1), that is, the number of channels of the display data signal is set to 2 A low-voltage data signal transmission unit and a low-voltage data signal reception unit are respectively arranged on the data buses, and the data bus configuration has a two-channel data bus in order to make the data transmission speed comparable to the display speed as a whole.

Further, when a low-voltage data signal transmitting section and a low-voltage data signal receiving section having a data transmission frequency of 65 MHz are used to display an extended graphic array (XGA) on a liquid crystal display panel, the low-voltage data signal is lower than the display speed. Since the data transmission speeds of the signal transmission unit and the low-voltage data signal reception unit are sufficient, it is sufficient to use a one-channel data bus configuration with a normal number of data bits (18 bits × 1).

On the other hand, a super extended graphic array (SXGA) is provided on a liquid crystal display panel.
And when using the Ultra Extended Graphic Array (UXGA) display, even if a low-voltage data signal transmission unit and a low-voltage data signal reception unit with a data transmission frequency of 65 MHz are used, the low-voltage data signal is lower than the display speed. Since the data transmission speed of the transmission unit and the low-voltage data signal reception unit is low, it is necessary to use a two-channel data bus configuration in order to make the data transmission speed comparable to the display speed as a whole.

[0007] When an ultra-extended graphic array (UXGA) is displayed on a liquid crystal display panel, the data transmission frequency currently under development is 14
If a low-voltage data signal transmission unit and a low-voltage data signal reception unit of 0 MHz are used, a one-channel data bus configuration is sufficient.

FIG. 6 is a block diagram showing an example of the configuration of a two-channel data bus in a known liquid crystal display device.

In FIG. 6, 61 is a TFT liquid crystal module, 62 is a host control unit, 63A is an A channel data bus, 63B is a B channel data bus, 64 is a TFT liquid crystal display panel, 65 is a timing control unit, and 66A is A A channel-side low-voltage data signal transmission section, 66B is a B-channel side low-voltage data signal transmission section, 67A is an A-channel side low-voltage data signal reception section, and 67B is a B-channel side low-voltage data signal reception section.

Then, the TFT liquid crystal module 61
FT liquid crystal display panel 64, timing control unit 65,
Each of the outputs of the A-channel low-voltage data signal receiving section 67A and the B-channel low-voltage data signal receiving section 67B includes an A-channel low-voltage data signal receiving section 67A and a B-channel low-voltage data signal receiving section 67B. The terminal is connected to the input terminal of the timing control unit 65 and the timing control unit 6
5, a first output terminal is connected to a drain drive terminal of the TFT liquid crystal display panel 64, and a second output terminal of the timing controller 65 is connected to a gate drive terminal of the TFT liquid crystal display panel 64. The host control unit 62 has a built-in A-channel low-voltage data signal transmission unit 66A and a B-channel low-voltage data signal transmission unit 66B. A channel data bus 63
A is connected between the output terminal of the A-channel side low voltage data signal transmission unit 66A and the input terminal of the A channel side low voltage data signal reception unit 67A, and the B channel data bus 63B
It is connected between the output terminal of the B-channel side low voltage data signal transmission unit 66B and the input terminal of the B channel side low voltage data signal reception unit 67B.

In the above configuration, the host control unit 62
A via the A channel side low voltage data signal receiving section 67A
An 18-bit display data signal A and a clock signal A for one channel with a maximum frequency of 33 MHz are output to the channel data bus 63A. Similarly, the host control unit 62 transmits the signal via the B-channel low-voltage data signal transmission unit 66B. 18-bit, maximum frequency 3 on B channel data bus 63B
A display data signal B and a clock signal B for another channel of 3 MHz are output. Next, the display data signal A and the clock signal A for one channel are supplied to the display data signal B and the clock signal B for the other one channel via the A-channel low-voltage data signal receiving section 67A. The signals are supplied to the input terminals of the timing control unit 65 via the voltage data signal receiving unit 67B. At this time, the timing control unit 65 responds to the display data signal A and the display data signal B, and the clock signal A and the clock signal B, and outputs the data signal and the first clock signal from the first output terminal to the TFT liquid crystal display panel 64. , And the second clock signal is supplied to the gate drive terminal of the TFT liquid crystal display panel 64, so that a display image appears on the display surface of the TFT liquid crystal display panel 64.

Next, FIG. 7 is a block diagram showing an example of a data bus configuration of one channel in a known liquid crystal display device.

In FIG. 7, reference numeral 63 denotes a data bus, 66 denotes a low-voltage data signal transmitting unit, 67 denotes a low-voltage data signal receiving unit, and other components that are the same as those shown in FIG. Is attached.

The TFT liquid crystal module 61
FT liquid crystal display panel 64, timing control unit 65,
An output terminal of the low voltage data signal receiving unit 67 is connected to an input terminal of the timing control unit 65, and a first output terminal of the timing control unit 65 is connected to the low voltage data signal receiving unit 67.
The second output terminal of the timing control unit 65 is connected to the gate drive terminal of the TFT liquid crystal display panel 64. The host control unit 62 has a built-in low-voltage data signal transmission unit 66.
The data bus 63 is connected between an output terminal of the low-voltage data signal transmission unit 66 and an input terminal of the low-voltage data signal reception unit 67.

In the above configuration, the host control unit 62
An 18-bit, maximum frequency of 65 MHz 1 is connected to the data bus 63 via the channel side low voltage data signal receiving section 67.
It outputs display data signals and clock signals for the channels. The display data signal and the clock signal for one channel are supplied to the input terminal of the timing control unit 65 via the channel side low voltage data signal receiving unit 67. At this time,
The timing controller 65 responds to the display data signal and the clock signal, supplies the data signal and the first clock signal from the first output terminal to the drain drive terminal of the TFT liquid crystal display panel 64, and outputs the second clock signal to the TFT liquid crystal display panel 64. It is supplied to the gate drive terminal of the liquid crystal display panel 64 to make a display image appear on the display surface of the TFT liquid crystal display panel 64.

FIG. 8 shows a timing controller 6 used in the two-channel data bus configuration shown in FIG.
5 is a block diagram illustrating an example of the configuration of FIG.

In FIG. 8, reference numeral 68 denotes a drive signal conversion unit, and other components which are the same as those shown in FIG. 6 are given the same reference numerals.

The timing control section 65 has a drive signal conversion section 68 incorporated therein.

The drive signal conversion unit 68 supplies the 18-bit display data signal A and clock signal A for one channel having a maximum frequency of 33 MHz supplied to the first input terminal.
18 bits supplied to the input end, maximum frequency 33MH
The first output terminal responds to the display data signal B and the clock signal B for another one channel of z, respectively, and applies the data signal and the first clock signal to the drain driving of the TFT liquid crystal display panel 64 (not shown in FIG. 8). The second clock signal is supplied to a terminal of the TFT liquid crystal display panel 64 (not shown in FIG. 8).

FIG. 9 is a block diagram showing an example of the configuration of a timing control unit used in the one-channel data bus configuration shown in FIG.

In FIG. 9, reference numeral 69 denotes a serial / parallel (S / P) conversion unit, and other components that are the same as those shown in FIG.

The timing controller 65 has a serial / parallel (S / P) converter 69 and a drive signal converter 68 incorporated therein.

When a display data signal of one channel having a maximum frequency of 65 MHz is supplied to the input terminal of 18 bits at the input terminal, the serial / parallel converter 69 performs serial / parallel conversion on the display data signal of one channel. A display data signal A and a clock signal A for one channel having a maximum frequency of 33 MHz are output from the first output terminal and supplied to the first input terminal of the drive signal converter 68,
18 bits each from the second output end, the highest frequency 33
The display data signal B and the clock signal B for another one channel of MHz are output and supplied to the second input terminal of the drive signal converter 68. The subsequent operation is the same as the operation of the drive signal conversion unit 68 shown in FIG.
The display data signal A and the clock signal A for one channel supplied to the input terminal, and the other one supplied to the second input terminal.
In response to the display data signal B and the clock signal B for the channels, respectively, the data signal and the first clock signal are transmitted from the first output terminal to the TFT liquid crystal display panel 64 (not shown in FIG. 9).
The second clock signal is supplied to the gate drive terminal of the TFT liquid crystal display panel 64 (not shown in FIG. 9).

[0024]

The known liquid crystal display devices each have 18 bits and a maximum frequency of 33 MHz.
Display data signal A and clock signal A for one channel
And a timing control unit 65 used in a two-channel data bus configuration to which the display data signal B and the clock signal B for the other one channel are supplied. Control unit 6 used in a one-channel data bus configuration to which the display data signal and the clock signal are supplied.
5 differs from the timing control unit 65 used in the case of a two-channel data bus configuration in that the timing control unit 65 used in the case of the two-channel data bus configuration is different from the timing control unit 65 used in the case of the one-channel data bus configuration. 65, and conversely, the timing control unit 65 used in the case of a one-channel data bus
It could not be used for the timing control section 65 used in the case of a channel data bus configuration. That is, when changing the two-channel data bus configuration connecting the TFT liquid crystal module 61 and the host control unit 62 to a one-channel data bus configuration, or changing the one-channel data bus configuration to a two-channel data bus configuration. In this case, it is necessary to change not only the data bus configuration but also the configuration of the timing control unit 65.

As described above, the known liquid crystal display device includes:
Since the compatibility of the components is poor, a new low-voltage data signal transmission unit and a low-voltage data signal reception unit have been developed, and when the number of channels of the data bus configuration changes accordingly, the timing control unit 65 Must be developed, and the time required for development as a whole increases, and the development cost increases.

The present invention has been made in view of such technical background, and an object of the present invention is to use a timing control unit that can be used for a one-channel data bus configuration or a two-channel data bus configuration, and to provide a required configuration. An object of the present invention is to provide a liquid crystal display device capable of reducing the number of elements.

[0027]

In order to achieve the above object, a liquid crystal display device according to the present invention comprises a liquid crystal display element, a TFT liquid crystal display panel having a thin film transistor (TFT) matrix driving section for scanning and driving the liquid crystal display element. , TF
A timing control unit for supplying a drive signal to the T liquid crystal display panel; and a host control unit for supplying one or two channels of display data signals to the timing control unit via one or two data buses. The timing control unit includes a serial / parallel conversion unit and one or more signal selection units, and the host control unit supplies the timing control unit with a switching signal corresponding to transmission and supply of one or two channels of display data signals. The timing control unit includes means for switching the signal selection unit according to the supplied switching signal and outputting the supplied one-channel or two-channel display data signal as a drive signal of the same format.

According to the above means, the serial / parallel converter and one or more signal selectors are arranged in the timing controller, and the signal selection state of one or more signal selectors is supplied from the host controller. By switching with the switching signal, the timing control unit and the data bus are set to the state in which the data bus has one channel or the state in which the data bus has two channels.
When a timing control unit and a data bus can be shared by a one-channel data bus configuration and a two-channel data bus configuration, a low-voltage data signal transmission unit and a low-voltage data signal reception unit are newly developed. In addition, it is not necessary to change the configuration of the data bus and the configuration of the timing control unit in accordance therewith, and it is possible to enhance the compatibility of the components and reduce the time required for development and the cost required for development.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to the present invention.

In FIG. 1, 1 is a TFT liquid crystal module, 2 is a host control unit, 3A is an A channel data bus,
3B is a B channel data bus, 4 is a TFT liquid crystal display panel, 5 is a timing controller, 6A is an A channel side low voltage data signal transmitter, 6B is a B channel side low voltage data signal transmitter, and 7A is an A channel side low. The voltage data signal receiving section 7B is a B-channel side low voltage data signal receiving section.

The TFT liquid crystal module 1 has a TF
It includes a T liquid crystal display panel 4, a timing control section 5, an A-channel low-voltage data signal receiving section 7A, and a B-channel low-voltage data signal receiving section 7B. The A-channel low-voltage data signal receiving unit 7A has an output terminal connected to the first input terminal of the timing control unit 5, and the B-channel low-voltage data signal receiving unit 7B has an output terminal connected to the second input terminal of the timing control unit 5. Connected to input terminal. The timing control unit 5
The first output terminal is connected to the drain drive terminal of the TFT liquid crystal display panel 4, and the second output terminal is connected to the gate drive terminal of the TFT liquid crystal display panel 4. The host control unit 2 includes an A-channel low-voltage data signal transmission unit 6A and a B-channel low-voltage data signal transmission unit 6B. The A-channel data bus 3A is connected between the output terminal of the A-channel low-voltage data signal transmitting unit 6A and the input terminal of the A-channel low-voltage data signal receiving unit 7A. It is connected between the output terminal of the channel-side low-voltage data signal transmission unit 6B and the input terminal of the B-channel low-voltage data signal reception unit 7B.

In the above configuration, this liquid crystal display device is
When a channel data bus configuration is used, the host control unit 2
Outputs a display data signal A and a clock signal A for one channel, each having 18 bits and a maximum frequency of 70 MHz, to the A channel data bus 3A via the A channel side low voltage data signal transmitting section 6A. The host control unit 2 transmits the 18-bit display data signal B and the clock signal B for the other one channel of the maximum frequency of 70 MHz to the B channel data bus 3B via the B channel side low voltage data signal transmission unit 6B. Is output. Then
Display data signal A and clock signal A for one channel
The display data signal B and the clock signal B for the other one channel are transmitted via the A-channel low-voltage data signal receiving section 7A, and the timing control section 5 is transmitted via the B-channel low-voltage data signal receiving section 7B. Are supplied to the first input terminal and the second input terminal. At this time, the timing control unit 5
Responds to the display data signal A and the display data signal B, and the clock signal A and the clock signal B, and outputs the data signal and the first clock signal (horizontal synchronization signal) from the first output terminal to the drain of the TFT liquid crystal display panel 4. A second clock signal (vertical synchronization signal) is supplied to a gate drive terminal of the TFT liquid crystal display panel 4 so that a display image appears on the display surface of the TFT liquid crystal display panel 4.

On the other hand, when this liquid crystal display device has a one-channel data bus configuration, the host control unit 2 transmits 18-bit data to the A-channel data bus 3A via the A-channel low-voltage data signal transmitting unit 6A. Output a display data signal and a clock signal for one channel having a maximum frequency of 140 MHz. Next, the display data signal and the clock signal for one channel are supplied to the first input terminal of the timing control unit 5 via the A-channel low-voltage data signal receiving unit 7A. At this time, the timing control unit 5 serially / parallel converts the supplied display data signal for one channel, and displays the display data signal A and the clock signal A for one channel and the display data signal B for another channel. And a clock signal B, and then perform the same signal processing as in the case of a two-channel data bus configuration.
A data signal and a first clock signal (horizontal synchronization signal) are supplied from a first output terminal to a drain drive terminal of the TFT liquid crystal display panel 4, and a second clock signal (vertical synchronization signal) is supplied to a TF.
T is supplied to the gate drive terminal of the liquid crystal display panel
A display image appears on the display surface of the T liquid crystal display panel 4.

FIG. 2 is a block diagram showing a configuration of the timing control section 5 used in the liquid crystal display device shown in FIG. 1 according to the first embodiment.

In FIG. 2, 3AD is a data signal transmission path of an A channel data bus, 3AC is a clock signal transmission path of an A channel data bus, 3BD is a data signal transmission path of a B channel data bus, and 3BC is a data signal transmission path of a B channel data bus. A clock signal transmission line, 8 a drive signal converter, 9 ₁ a first signal selector (first selector), 9 ₂ a second signal selector (second selector), 10 a serial / parallel (S /
P) A conversion unit 11 is a switching signal line, and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The timing control unit 5 includes an A-channel low-voltage data signal receiving unit 7A, a B-channel low-voltage data signal receiving unit 7B, a drive signal converting unit 8,
A signal selecting section 9 _1, and the second signal selecting section 9 _2, serial /
And a parallel conversion unit 10. The A-channel first low-voltage data signal receiving section 7A has an input terminal connected to the data signal transmission path 3AD of the A-channel data bus and the clock signal transmission path 3AC of the A-channel data bus, respectively.
Output terminal connected to the first input terminal and a second input of the second signal selection unit 9 _2. The B-channel first low-voltage data signal receiving unit 7B has an input terminal connected to the data signal transmission line 3BD of the B-channel data bus and a clock signal transmission line 3BC of the B-channel data bus, and an output terminal connected to the first signal selection terminal. The unit 91 is connected to _one of the fourth input terminal of the pair and one of the third input terminal of the pair. The second signal selecting section 9 _2, the first output terminal and a second output terminal is respectively connected to the first input terminal and a second input terminal of the serial / parallel converter 10, a third output terminal a first signal selector 9 is connected to one of the second input terminal of the _first pair, the fourth output terminal the first signal selecting section 9
It is connected to one of the first input terminal of the _first pair. The serial / parallel converter 10 has a first output terminal which is a first signal selector 9 _1.
Are connected to the other of the second input terminals, and the second output terminal is connected to the first input terminal.
It is connected to the other of the fourth input terminal of the pair of signal selection unit 9 _1, respectively third output terminal to the other of the third input end of the other and a pair of first input terminals of the pair of first signal selector 9 ₁ Connected. First
Signal selection unit 9 _1, a first output terminal, a second output terminal, a third output terminal, the first input terminal of the fourth output terminal respectively driving signal converting unit 8, a second input terminal, a third input terminal, the Connected to 4 inputs. The switching signal line 1 derived from the host control unit 2
1 is connected to the first signal selecting section 9 ₁ and the second signal selector 9 _2.

The timing control section 5 having the above configuration operates as follows.

First, when the liquid crystal display device has a two-channel data bus configuration, the host control unit 2
1, a two-channel switching signal is output to the _first and second signal selectors 9 ₁ and 9 ₂ according to the two-channel switching signal.
Are switched so that each display data signal and each clock signal do not bypass the serial / parallel converter 10. At this time, the data signal transmission path 3AD and the clock signal transmission path 3A of the A channel data bus
C has 18 bits each and the maximum frequency is 70 MH
z display data signal A and clock signal A are supplied,
An 18-bit display data signal B and a clock signal B with a maximum frequency of 70 MHz are supplied to the data signal transmission path 3BD and the clock signal transmission path 3BC of the B-channel data bus, respectively.

The display data signal A is supplied through the A channel side low voltage data signal receiving unit 7A in the second signal selecting section 9 _2, clock signal A is also a second signal through the A channel side low voltage data signal receiving section 7A after being supplied to the selector 9 _2, respectively, it is supplied through the second signal selecting section 9 ₂ to the first signal selection unit 9 _1. Display data signal B, through B-channel side low voltage data signal receiving portion 7B is supplied to the first signal selector 9 _1, the clock signal B is also the first signal selector 9 through the B-channel side low voltage data signal receiving section 7B
Supplied to ₁ . The first signal selecting section 9 ₁ includes: a display data signal A and the clock signal A respective input and supplies display data signals B and clock signal B, respectively driving signal converting unit 8. The drive signal converter 8 converts the input display data signal A and display data signal B, and the clock signal A
And outputs a data signal and a first clock signal (horizontal synchronization signal) from the first output terminal in response to
The signal is supplied to the drain drive terminal of the FT liquid crystal display panel 4, the second clock signal (vertical synchronization signal) is output from the second output terminal, and supplied to the gate drive terminal of the TFT liquid crystal display panel 4.

Next, when the liquid crystal display device has a one-channel data bus configuration, the host control unit 2
1 outputs a one-channel switching signal to the _first and second signal selectors 9 ₁ and 9 ₂ according to the one-channel switching signal.
Are switched to correspond to one channel, that is, each display data signal and each clock signal pass through the serial / parallel converter 10. At this time, the data signal transmission line 3AD and the clock signal transmission line 3AC of the A channel data bus each have 18 bits and a maximum frequency of 140 MHz.
Are supplied.

The display data signal is supplied through the A channel side low voltage data signal receiving unit 7A in the second signal selecting section 9 _2, the clock signal A, after being fed directly to the second signal selecting section 9 _2, respectively It is supplied through the second signal selecting section 9 ₂ to the serial / parallel converter 10. Cereal/
The parallel conversion unit 10 performs serial / parallel conversion of each input display data signal and clock signal, and distributes and outputs the display data signal A and the clock signal A and the display data signal B and the clock signal B. 1 signal selector 9
_The signals are supplied to the drive signal conversion unit 8 via ₁ . The drive signal converter 8 responds to the input display data signal A and display data signal B, and the clock signal A and clock signal B, respectively, and outputs a data signal and a first clock signal (horizontal synchronization signal) from the first output terminal. ) Is supplied to the drain drive terminal of the TFT liquid crystal display panel 4, and a second clock signal (vertical synchronization signal) is output from the second output terminal and supplied to the gate drive terminal of the TFT liquid crystal display panel 4.

FIG. 3 is a block diagram showing a configuration of a timing control section 5 used in the liquid crystal display device shown in FIG. 1 according to a second embodiment.

In FIG. 3, the same components as those shown in FIG. 2 are denoted by the same reference numerals.

The timing control unit 5 according to the second embodiment is different from the timing control unit 5 according to the first embodiment.
, Except for the A-channel side low-voltage data signal receiving section 7A and the B-channel side low-voltage data signal receiving section 7B, although not shown, the A-channel side low-voltage data signal receiving section 7A and the B-channel side The low-voltage data signal receiving section 7B is external to the timing control section 5. The configuration of the timing control unit 5 according to the second embodiment is similar to that of the timing control unit 5 except that the timing control unit 5 does not include the A-channel low-voltage data signal receiving unit 7A and the B-channel low-voltage data signal receiving unit 7B. This is the same as the configuration of the timing control unit 5 according to the first embodiment. Therefore, the second
Regarding the configuration of the timing control section 5 according to the embodiment, further description is omitted.

The operation of the timing control unit 5 according to the second embodiment is as follows. When the liquid crystal display device has a two-channel data bus configuration, the display data signal A is transmitted to the A-channel side low-voltage data signal receiving unit 7A. instead, point that receives the output of the a channel side low voltage data receiving unit 7A disposed outside the second signal selecting section 9 _2, and the B channel side low voltage data signals received display data signal B received by Part 7B
Instead of receiving in, except that receives the output of the B channel side low voltage data signal receiving portion 7B which is provided outside the first signal selection unit 9 _1, timing according to the first embodiment of the aforementioned The operation is the same as that when the liquid crystal display device of the control unit 5 has a two-channel data bus configuration. When the liquid crystal display device has a two-channel data bus configuration,
Except that instead of receiving the display data signal by the A channel side low voltage data signal receiving unit 7A, a point that receives the output of the A channel side low voltage data receiving unit 7A disposed outside the second signal selecting section 9 ₂ For example, the operation is the same as that in the case where the liquid crystal display device of the timing control unit 5 according to the first embodiment has a one-channel data bus configuration. Therefore, further description of the operation of the timing control unit 5 according to the second embodiment will be omitted.

FIG. 4 is a block diagram showing a configuration of a timing control section 5 used in the liquid crystal display device shown in FIG. 1 according to a third embodiment, and includes a TFT liquid crystal module 1 and a host control section. 2 can be provided when an additional channel data bus 3F is provided in addition to the A channel data bus 3A and the B channel data bus 3B.

In FIG. 3, 3F is an additional channel data bus, 3FD is an additional channel data bus data signal transmission path, 3FC is an additional channel data bus clock signal transmission path, 7F is an additional channel side low voltage data signal receiving section, Reference numeral 9 denotes a signal selection unit (selector).
The same reference numerals are given to the same components as those shown in FIG.

The timing control section 5 includes an A-channel low-voltage data signal receiving section 7A, a B-channel low-voltage data signal receiving section 7B, an additional channel-side low-voltage data signal receiving section 7F, and a driving signal conversion section. A section 8, a signal selection section 9, and a serial / parallel conversion section 10 are provided. A
The channel-side first low-voltage data signal receiving unit 7A has an input terminal connected to the data signal transmission line 3AD of the A-channel data bus, and an output terminal connected to one of the pair of second input terminals of the signal selection unit 9. . B channel side low voltage data signal receiving section 7
B has an input terminal connected to the data signal transmission line 3BD of the B-channel data bus, and an output terminal connected to the fourth terminal of the pair of the signal selection unit 9.
Connected to one of the input terminals. The additional channel side low voltage data signal receiving section 7F has an input terminal connected to the data signal transmission line 3FD of the additional channel data bus, and an output terminal connected to the first input terminal of the serial / parallel converter 10. The serial / parallel converter 10 has a second input terminal connected to the clock signal transmission line 3FC of the additional channel data bus, a first output terminal connected to the other of the pair of second input terminals of the signal selection unit 9, and The two output terminals are connected to the other of the fourth input terminals of the pair of the signal selection unit 9, and the third output terminals are respectively connected to the other of the first input terminals of the pair of the signal selection units 9 and the other of the third input terminals of the pair. Connected. In the signal selector 9, one of the first input terminals of the pair is connected to the clock signal transmission line 3AC of the A channel data bus, and one of the third input terminals of the pair is connected to the clock signal transmission line 3BC of the B channel data bus. And the first output end,
The second output terminal, the third output terminal, and the fourth output terminal are connected to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the drive signal converter 8, respectively. The switching signal line 11 derived from the host control unit 2 is connected to the signal selection unit 9.

The timing control section 5 according to the third embodiment having the above configuration operates as follows.

First, when the liquid crystal display device has a two-channel data bus configuration, the host control unit 2
1, a two-channel switching signal is output, and the signal selector 9 is switched for two channels according to the two-channel switching signal. At this time, a display data signal A and a clock signal A having a maximum frequency of 70 MHz, each having 18 bits, are supplied to the data signal transmission path 3AD and the clock signal transmission path 3AC of the A channel data bus, respectively. The signal transmission path 3BD and the clock signal transmission path 3BC each have 18 bits and a maximum frequency of 7 bits.
A display data signal B and a clock signal B of 0 MHz are supplied.

The display data signal A is supplied to the signal selecting section 9 through the A-channel low-voltage data signal receiving section 7A, and the clock signal A is directly supplied to the signal selecting section 9. The display data signal B is supplied to the signal selection unit 9 through the B channel side low voltage data signal reception unit 7B, and the clock signal B is directly supplied to the signal selection unit 9. The signal selection unit 9 supplies the input display data signal A and clock signal A and the display data signal B and clock signal B to the drive signal conversion unit 8, respectively. Drive signal converter 8
Outputs a data signal and a first clock signal (horizontal synchronization signal) from a first output terminal in response to the input display data signal A and display data signal B, and the clock signal A and clock signal B. The signal is supplied to a drain drive terminal of the TFT liquid crystal display panel 4, a second clock signal (vertical synchronization signal) is output from a second output terminal, and supplied to a gate drive terminal of the TFT liquid crystal display panel 4.

Next, when the liquid crystal display device has a one-channel data bus configuration, the host control unit 2
1 outputs a one-channel switching signal, and switches the signal selector 9 to one channel according to the one-channel switching signal. At this time, the data signal transmission line 3FD and the clock signal transmission line 3FC of the additional channel data bus are respectively supplied with a display data signal and a clock signal having a maximum frequency of 140 MHz and 18 bits.

The display data signal is supplied to the serial / parallel converter 10 through the additional channel side low voltage data signal receiver 7F, and the clock signal is supplied directly to the serial / parallel converter 10. The serial / parallel converter 10 performs serial / parallel conversion on the input display data signal and clock signal, and distributes and outputs the display data signal A and the clock signal A and the display data signal B and the clock signal B. Are supplied to the drive signal conversion unit 8 respectively. The drive signal converter 8 responds to the input display data signal A and display data signal B, and the clock signal A and clock signal B, respectively, and outputs a data signal and a first clock signal (horizontal synchronization signal) from the first output terminal. ) To output TF
Supply to the drain drive terminal of the T liquid crystal display panel 4 and the second
A second clock signal (vertical synchronization signal) is output from the output terminal and supplied to the gate drive terminal of the TFT liquid crystal display panel 4.

FIG. 5 is a block diagram showing a configuration of a timing control section 5 used in the liquid crystal display device shown in FIG. 1 according to a fourth embodiment, in which a TFT liquid crystal module 1 and a host control are shown. This can cope with a case where an additional channel data bus 3F is provided between the unit 2 and the A channel data bus 3A and the B channel data bus 3B.

In FIG. 5, the same components as those shown in FIG. 4 are denoted by the same reference numerals.

The timing control unit 5 according to the fourth embodiment is different from the timing control unit 5 according to the third embodiment.
From the A-channel side low-voltage data signal receiving section 7A, the B-channel side low-voltage data signal receiving section 7B, and the additional channel-side low-voltage data signal receiving section 7F. Side low voltage data signal receiving section 7A, B channel side low voltage data signal receiving section 7
B and the additional channel side low voltage data signal receiving section 7F
Are externally attached to the timing control unit 5. The configuration of the timing control unit 5 according to the fourth embodiment is similar to that of the A-channel low-voltage data signal receiving unit 7.
The configuration is the same as that of the timing control unit 5 according to the third embodiment except that the A and B channel side low voltage data signal receiving units 7B and the additional channel side low voltage data signal receiving unit 7F are not provided. It is. Therefore, regarding the configuration of the timing control unit 5 according to the fourth embodiment,
Further description is omitted.

The operation of the timing control unit 5 according to the fourth embodiment is as follows. When the liquid crystal display device has a two-channel data bus configuration, the display data signal A is supplied to the A-channel side low-voltage data signal receiving unit. 7A, instead of receiving the display data signal B at the B-channel low-voltage data signal receiving unit 7B, instead of receiving it at the B-channel low-voltage data signal receiving unit 7B. Except for
The operation of the timing control unit 5 according to the third embodiment is the same as that when the liquid crystal display device has a two-channel data bus configuration, and when the liquid crystal display device has a one-channel data bus configuration. In this case, except that the display data signal is directly received by the serial / parallel converter 10 instead of being received by the additional channel side low voltage data signal receiver 7F, the timing control according to the third embodiment described above is performed. The operation is the same as that when the liquid crystal display device of the unit 5 has a one-channel data bus configuration. Therefore, further description of the operation of the timing control unit 5 according to the fourth embodiment will be omitted.

As described above, in the first to fourth embodiments, the serial / parallel converter 10 and one or more signal selectors 9, 9 ₁ and 9 ₂ are arranged in the timing controller 5, and One or more of the signal selector 9, 9 _1, 9 ₂ signal selection state switching by a switching signal supplied from the host controller 2, the timing control unit 5 and a data bus, the state at the time of the data bus configuration of 1 channel Alternatively, since the state is set at the time of the two-channel data bus configuration, the timing control unit 5 and the data bus can be shared by the one-channel data bus configuration and the two-channel data bus configuration.

In the first to fourth embodiments, the number of bits of the display data signal and the clock signal supplied from the host control unit 2 to the timing control unit 5 is one.
8 bits with a maximum frequency of 70 MHz or 140
Although the description has been given by taking the example of MHz, the number of bits and the highest frequency of the display data signal and the clock signal used in the present invention are not limited to those described above, and other bits and the highest frequency are selected. Of course, it may be.

[0061]

As described above, according to the present invention, the serial / parallel converter and one or more signal selectors are arranged in the timing controller, and the signal selection state of one or more signal selectors is changed. Since the timing control unit and the data bus are set to the state when the data bus has one channel or the state when the data bus has two channels by switching by the switching signal supplied from the host control unit. , A timing control unit and a data bus
When the low-voltage data signal transmission unit and the low-voltage data signal reception unit are newly developed, the data bus configuration and the timing control can be shared by the channel data bus configuration and the two-channel data bus configuration. This eliminates the need to change parts, thereby improving the compatibility of the components and reducing the development cost.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing a configuration according to a first embodiment of a TFT control unit in the liquid crystal display device shown in FIG.

FIG. 3 is a block diagram showing a configuration according to a second embodiment of the TFT control unit in the liquid crystal display device shown in FIG.

FIG. 4 is a block diagram showing a configuration of a TFT control unit in the liquid crystal display device shown in FIG. 1 according to a third embodiment.

FIG. 5 is a block diagram showing a configuration of a TFT control unit in the liquid crystal display device shown in FIG. 1 according to a fourth embodiment.

FIG. 6 is a block diagram showing an example of a two-channel data bus configuration in a known liquid crystal display device.

FIG. 7 is a block diagram showing an example of a one-channel data bus configuration in a known liquid crystal display device.

8 is a block diagram illustrating an example of a configuration of a TFT control unit used in the two-channel data bus configuration illustrated in FIG. 6;

9 is a block diagram illustrating an example of a configuration of a TFT control unit used for the one-channel data bus configuration illustrated in FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Thin film transistor (TFT) liquid crystal module 2 Host control part 3A A channel data bus 3AD Data signal transmission line of A channel data bus 3AC Clock signal transmission line of A channel data bus 3B B channel data bus 3BD Data signal transmission of B channel data bus Path 3BC Clock signal transmission path of B channel data bus 3F Additional channel data bus 3FD Data signal transmission path of additional channel data bus 3FC Clock signal transmission path of additional channel data bus 4 Thin film transistor (TFT) liquid crystal display panel 5 Timing controller 6A A Channel side low voltage data signal transmission section 6B B channel side low voltage data signal transmission section 7A A channel side low voltage data signal reception section 7B B channel side low voltage data signal reception section 7F Additional channel side low voltage data transmission section Data signal reception unit 8 drive signal converting unit 9 signal selector (selector) 9 ₁ first signal selector (first selector) 9 ₂ second signal selector (second selector) 10 serial / parallel (S / P) conversion Part 11 switching signal line

Continued on front page F term (reference) 2H093 NA16 NA80 NC22 NC23 NC27 NC28 NC34 NC49 NC59 NC90 ND20 ND38 ND39 ND43 ND49 ND50 ND55 NE03 NH16 5C006 BB16 BC16 BF16 BF24 EB05 FA01 FA13 FA16 FA43 FA51 5C080 AA10 BB05 DD08

Claims (3)

[Claims] 1. A thin-film transistor liquid-crystal display panel comprising a liquid-crystal display element and a thin-film transistor matrix driving section for scanning and driving the liquid-crystal display element, a timing control section for supplying a drive signal to the thin-film transistor liquid-crystal display panel, and a timing control section. In a liquid crystal display device comprising a host control unit for supplying one or two channels of display data signals via one or two data buses, a serial / parallel conversion unit and one or more signals are provided to the timing control unit. A selection unit, wherein the host control unit supplies a switching signal corresponding to the transmission supply of the one-channel or two-channel display data signal to the timing control unit, and the timing control unit The signal selector is switched by a signal, and the supplied one channel Alternatively, a liquid crystal display device which outputs display data signals of two channels as drive signals of the same format. 2. The liquid crystal display device according to claim 1, wherein the thin film transistor liquid crystal display panel and the timing controller are integrated to form a thin film transistor liquid crystal module. 3. The liquid crystal display device according to claim 2, wherein the thin film transistor liquid crystal module includes a low voltage data signal receiving unit connected to an input terminal of the timing control unit.