JP2000358363A - Apparatus and method for multi-phase voltage conversion - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain smooth operation with minimized ripple voltage and ripple current, even in single phase by actuating a variety of voltage converter circuits to convert DC voltage level in staggered phase relation. SOLUTION: A multi-phase back converter 70 is provided with two back converters 72 and 74 which operate in shifted phases, and each of the back converters 72 and 74 is provided with a plurality of boosting circuits constituted in parallel, and a control circuit containing a power-factor adjustment circuit and at least one delay circuit. The power-factor adjustment circuits and the delay circuits are so constituted that a plurality of phase signals with their phases shifted relative to each other are generated collectively. By having each of the phase signals applied to one of the boost circuits, a corresponding boost output circuit is driven, and the back converters 72 and 74 produce a single output 80, using a single input 76 with respect to common 78. The back converters 72 and 74 are driven by control circuit 82 and operates with having a phase difference of 180 deg. between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] This application is a co-pending application of the "Polyphase Switch Mode P"
US Provisional Patent Application No. 60 / 134,45, filed May 17, 1999, entitled "Power Converter".
No. 2 and "Polyphase Switch M
Ode Converter ", June 1999
No. 60 / 138,339, filed on May 9, the entire disclosure of which is incorporated herein by reference.

[0002]

FIELD OF THE INVENTION The present invention relates generally to the field of power conversion, and more particularly to a polyphase switch mode power conversion system and method.

[0003]

2. Description of the Related Art A variety of switch mode power conversion circuits including buck and boost converters are well known in the art. Buck converters operate to reduce the direct current (DC) voltage from one level to another lower level, while boost converters operate to increase the DC voltage from one level to a higher level. . These converter circuits are well known and operate relatively simply and very efficiently, but the semiconductor switching devices used, such as field effect transistors (FETs) and insulated gate bipolar transistors (IBGTs) According to the rating of
Power handling capacity is limited. Thus, operation at high power levels may require multiple switching devices to operate in parallel. Similarly, inductors are required to be easy to produce, small in size and more economical, so that in a converter circuit designed to operate at relatively high power levels, both parallel switching devices and parallel inductors are used. Use is common. The parallel operation of the components allows operation at the desired high power level, while the parallel operation of the components results in high levels of ripple current and at the input and output terminals of these converters. It does not lower the voltage.

[0004] The benefits of multi-phase operation in rotating machinery such as power distribution, transformers, motors and generators have long been understood. Three-phase power distribution is as common as the use of three-phase motors, generators, rectifiers, battery chargers and power supplies. It has long been known and understood that polyphase power provides smoother operation of motors and generators. This is because there are six instead of two power pulses per cycle, just as a six cylinder engine is inherently smoother than a two cylinder engine of equal power. For devices that produce a DC output, such as rectifiers, battery chargers and power supplies, using polyphase power is particularly advantageous. This is because the phase overlap greatly reduces the need to filter the DC output to achieve a smooth, low ripple DC output voltage and current.

[0005]

SUMMARY OF THE INVENTION In the prior art,
It has been common to use multiple switch mode converters connected to a polyphase power system for each phase. For example, three converters have been used in three-phase power systems. All three phases of this three-phase power system contribute to a single output. Unfortunately, similar advantages were not seen with the single phase.

[0006]

SUMMARY OF THE INVENTION In view of the above,
The present invention provides a system and method for converting a DC voltage from a first voltage level to a second voltage level by operating various voltage converter circuits in a staggered phase relationship. The smoothest operation with minimum ripple voltage and ripple current is obtained when each converter is equally phase shifted during operation from the immediately preceding and following converters. Assuming a full cycle consists of 360 electrical degrees, and if the number of transducers used is "N", each transducer will be phase shifted by 360 / N from its neighbor. For example, if three transducers are used (N =
3) Each converter is phase shifted by 120 ° from the adjacent converter. The four phases have a 90 ° phase shift, etc.
Not only is ripple greatly reduced, but ripple at a frequency N times the frequency at which the converter operates further simplifies and reduces any filtering required.

[0007] The invention can also be viewed as a method of converting a DC voltage. Methods in this regard generally include the following steps. That is, including a step of arranging a number of voltage converter circuits in a parallel direction, a step of generating a number of phase signals together with a control circuit, and a step of applying each phase signal to each voltage converter circuit, The voltage converter circuit can generate an output waveform. The method may further include offsetting the phase signal by a predefined phase interval.

[0008] A system for converting a voltage according to the present invention comprises a plurality of boost circuits configured in parallel; a control circuit including a power factor correction circuit and at least one delay circuit; And the at least one delay circuit is configured to collectively generate a plurality of phase signals that are phase shifted with respect to each other, each of the phase signals being applied to a respective one of the boost circuits. This drives the corresponding boost circuit output.

The power factor correction circuit and the at least one
The phase signals generated by the two delay circuits may be offset in phase at a predetermined phase interval.

The power factor correction circuit and the at least one
The phase signals generated by the two delay circuits may drive each of the boost circuits in a discontinuous mode.

The power factor correction circuit and the at least one
The phase signals generated by the two delay circuits may drive each of the boost circuits in a critical conduction mode.

[0012] One of the phase signals is a master phase signal generated by the power factor correction circuit, and at least one of the phase signals is the master phase signal.
It may be a slave signal generated by two delay circuits.

Each of the boost circuits is a switching device having a control input, a power input, and a switch output, the switch output being a switching device electrically coupled to a common; An inductor electrically coupled between the power input and a diode electrically coupled between the power input and the output of the boost circuit may be further provided.

[0014] The power factor correction circuit may further include a master phase output electrically coupled to a switching input of one of the boost circuits.

[0015] The at least one delay circuit has a phase input and at least one slave output, the at least one slave output being electrically coupled to a corresponding switching input of the boost circuit. You may.

[0016] The switching device may further include an insulated gate bipolar transistor.

A method for converting a voltage according to the present invention includes a plurality of boost circuits configured in parallel; a power factor correction means for generating a first phase signal of the plurality of phase signals; At least one delay means for generating a second phase signal of at least one of said phase signals, said phase signals being phase shifted with respect to each other, each of said phase signals being Applied to each one of the circuits to drive the corresponding boost circuit output.

The apparatus may further include means for offsetting the phase signal at a predetermined phase interval.

A method for converting voltages according to the present invention, comprising: electrically coupling a plurality of boost circuits in parallel; and a control circuit including a power factor correction circuit and at least one delay circuit with respect to each other. Collectively generating a plurality of phase shifted phase signals,
Driving each of the phase signals to a respective one of the boost circuits to drive a corresponding boost circuit output.

The method may further include the step of offsetting the phase signal at a predetermined phase interval.

[0021] The method may further include driving each of the boost circuits in the discontinuous mode by the phase signal.

The method may further include driving each of the boost circuits in the critical conduction mode according to the phase signal.

The step of collectively generating a plurality of phase signals by the control circuit including the power factor correction circuit and at least one delay circuit includes the step of generating a master phase signal by the power factor correction circuit;
Generating a slave signal by two delay circuits.

Providing the boost circuit, comprising: providing a switching device having a control input, a power input, and a switch output, wherein the switch output is electrically coupled to common. Electrically coupling an inductor to the input of the boost circuit and the power supply input; and electrically coupling a diode between the power supply input and the output of the boost circuit. It may further include.

[0025] The method may further comprise providing a master phase output from the power factor correction circuit electrically coupled to a switching input of one of the boost circuits.

Providing a phase input of the at least one delay circuit and at least one slave output, the at least one slave output being electrically connected to a corresponding switching input of the boost circuit. Steps that are combined may further be included.

[0027] Providing a switching device having the control input may further include providing an insulated gate bipolar transistor.

Other features and advantages of the present invention will become apparent to one with skill in the art upon reading the following figures and detailed description. All additional features and benefits are
Included herein within the scope of the present invention.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily shown to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, like reference numerals in the figures indicate corresponding parts throughout the several views.

Referring to FIG. 1, a prior art buck converter circuit 10 is shown. Buck converter circuit 10 is shown in schematic form and includes a switching device 16 shown as a field effect transistor (FET). Switching device 16, and corresponding switching devices shown with reference to the other figures, may be shown as field effect transistors, but any such switching device may be replaced by any other suitable switching device (eg, a bipolar transistor). , Insulated gate bipolar transistors, or various other devices).

According to FIG. 1, an input voltage is applied between an input 12 and a common connection 14, which is common to both the input and output of the circuit. Transistor 16
Switched on and off by a control circuit (not shown), the output voltage obtained at output 24 is typically at a desired level, which is lower than the level of the input voltage. When transistor 16 is "on," current flows from the input voltage source through inductor 20 and to output 24 and common 1
4 flows through a load (not shown) connected between the power supply 4. As current flows through the inductor, energy is stored in the inductor's magnetic field. After a period of time defined by the control circuit, the transistor turns "off". At this time, the energy stored in the inductor field is
Current flows through the inductor, the load, and the diode 18
To force the stored energy to continue flowing until it is exhausted or until the transistor is turned "on" again. If transistor 16 is turned on again before the energy in the inductor field is depleted, the circuit will operate in continuous mode, since the current through the inductor will not drop to zero. The circuit may also operate in a discontinuous mode, in which case the inductor current may fall to zero for a period of time during each cycle. In addition, the circuit can operate in critical conduction mode, in which the inductor current just reaches zero before the transistor is turned "on" again in order to start the next cycle and immediately increase the inductor current. It is possible to go down.

Referring to FIG. 2, there is shown a graph of two waveforms present in the circuit of FIG. For the purpose of illustration, this waveform has been chosen to represent a circuit operating in continuous mode with a voltage of one to four step-downs, for example, a 48 volt DC input and 12 volts.
Circuit with DC output of volts. Waveform 30 corresponds to transistor 16, diode 18 and inductor 2 of FIG.
Represents the voltage at the junction between zero and zero. This point rises to the potential of the input voltage source 12 when the transistor is on, and falls to a junction below zero due to conduction of the diode 18 when the transistor is off. In continuous mode of operation, the output voltage at 24 will be equal to the average value of the voltage 30, and for a 12 volt output and a 48 volt input, the duty cycle (ie, the temporal transistor relative to the sum of on and off times) Is 1/4 or 25%.

When the transistor 16 is on, the waveform 32
The inductor current ramps up from a minimum to a maximum as energy is stored in the magnetic field of the inductor. When transistor 16 is off, the inductor current ramps down to its minimum as shown. In certain instances, the circuit operates in a continuous conduction mode, but near critical conduction point, since the minimum value is selected close to zero (but always above zero). Note that while the desired output of the circuit is a smooth DC voltage, the current through the inductor is a sawtooth waveform. The capacitor 22 shown in FIG. 1 serves the purpose of providing a path for the AC (ripple) component of the inductor current. The amount of ripple voltage at the output of the circuit is a function of the ripple current, the size of the capacitor, and the ripple frequency. The average DC component of the inductor current is shown by dashed line 34 in FIG. The ripple current that must pass through the output capacitor 22 shown in FIG.
And the actual inductor current 32. The circuit shown in FIG. 1 and the waveforms in FIG. 2 reflect the prior art and are well known and will be understood.

Referring to FIG. 3, a boost converter 40 according to the prior art is shown. The input voltage is
Generated between output 54 and common 44. For purposes of illustration, assume that the transducer has a one-to-three step-up ratio (eg, a 12 volt input and a 36 volt output). As in the case of the buck converter described above, the boost converter may operate in a continuous mode, a discontinuous mode, or a critical conduction mode. In operation, transistor 48 is turned on or off by a control circuit (not shown), typically in response to a voltage level at output 54, and when transistor 48 is on, current flows from input 42 to inductor 46 and transistor 4
Flow through 8. Transistor 48 is "on" as in the buck converter circuit 10 (FIG. 1) described above.
At this time, the current in the inductor 46 increases as the energy stored in the magnetic field of the inductor increases. When transistor 48 is “off”, current flows from the input through inductor 46 and then continues to flow through diode 50 to output 54. Capacitor 52 is connected across output 54 and common 44 of boost converter circuit 40, which provides a path for the AC (ripple) component.

Referring to FIG. 4, transistor 48 (FIG. 3), diode 50 (FIG. 3) and inductor 46
The average (ie, DC component) of the current through inductor 46 as shown by voltage waveform 60 at the junction of FIG. 3 and inductor current waveforms 62 and 64.
Is shown. Voltage 60 drops to near zero when transistor 48 is on. At the same time, the inductor current 6
2 ramps up to the maximum value reached when transistor 48 is off. In this example, the inductor current cannot flow through transistor 48 and must flow through diode 50 to output 54 and from there to the load (not shown). Buck converter circuit 10
The boost converter circuit 40, as in the case according to FIG.
Is well known in the art.

Referring to FIG. 5, a polyphase buck converter 70 according to an embodiment of the present invention is shown. Polyphase buck converter 70 includes two buck converters 72 and 74 operating in a phase shifted relationship. Each of the buck converters 72 and 74 operates as described with respect to FIGS. Buck converters 72 and 74 use one input 76 with respect to common 78 and produce one output 80. Buck converters 72 and 74 are connected to control circuit 8.
2 and the buck converters 72 and 74 operate 180 degrees out of phase with each other. The control circuit 82
It may be realized by discrete components or may be an integrated circuit as described in more detail with reference to FIG.

Referring to FIG. 6, there is shown a graph of a number of waveforms illustrating the phase shifting operation of the polyphase buck converter 70 (FIG. 5). The following description of the operation of the polyphase buck converter 70 assumes a 1 to 4 voltage step down ratio. Waveforms 90 and 94 are buck converters 72 and 7
4 respectively represent the voltage waveforms obtained at the junction of each transistor, diode and inductor. Waveforms 90 and 94 substantially correspond to waveform 30 (FIG. 2). Similarly, waveform 92
And 96 are the inductor current waveforms in the two buck converters 72 and 74, each with waveform 32
(FIG. 2). According to the prior art, operation of buck converter circuit 10 (FIG. 1) at twice the power level, or operation of two such circuits in parallel, results in twice the inductor current as shown by waveform 98. . According to the invention, two buck converters 72 in a polyphase configuration (ie, shifted phase as described).
The operation of and 74 results in a composite current shown by waveform 100, which is the sum of the individual inductor currents 92 and 96. Waveform 102 shows the average of the output of polyphase buck converter 70 (ie, the DC component).

It is clear that waveform 100 is smoother and has a significantly lower AC current component (ie, ripple) than waveform 98 representing the prior art.
Furthermore, by using the present invention, not only is the magnitude of the ripple reduced, but the frequency is also doubled, and as such, filtering this ripple to obtain smooth DC input and output currents To facilitate. The increase in ripple frequency is a linear function of the number of phases used, and if there are N phases, the ripple frequency is multiplied by N. The reduction in the magnitude of the ripple is not only a function of the number of phases, but also of the voltage conversion ratio of the converter.

Referring to FIG. 7, there is shown a polyphase boost converter 110 according to an embodiment of the present invention. The polyphase boost converter 110 includes two phases, but a larger number of phases may be used in accordance with the principles of the present invention. The DC voltage is
Applied between input 112 and common 114. Inductor 118, transistor 122, and diode 1
36 operates as a first phase, the inductor 120, the transistor 12
4, and a second boost circuit composed of a diode 138 operates as a second phase. The second phase is shifted 180 degrees (ie, one half cycle) from the first phase. An output voltage is generated at output 142 with respect to common 114. Input capacitor 11
6 provides a path for input ripple current flow, while output capacitor 140 provides a path for output ripple current flow and filters the output.

The boost converter circuit is driven by control circuit 134 in a manner similar to control circuit 82 (FIG. 5). The control circuit 134 operates as shown in FIG.
22 and 124 are activated via the registers 126 and 128, and the output voltage of the polyphase boost converter 110 is
The adjustment is made in response to a feedback voltage divider that includes resistors 130 and 132. The control circuit 134 can be a double-ended pulse width modulation converter intended for push-pull inverter applications, which are well known in the art. This is, for example, Unitode Corporation
"Current Mode PW
M Controller "(model number UC1846
/ 7), which is Unitrod dated January 1997.
e, "Current Mode PWM"
Controller "(model number UC1864 /
This is the subject of 7). Further details regarding the operation and connection of the Unitode controller are provided in the aforementioned publications, which are incorporated herein by reference.

Next, referring to FIG. 8, the multi-phase boost (bo
ost) of the converter 110 (FIG. 7).
ent) shows the waveform. For illustrative purposes, assume that the polyphase boost converter 110 is operated at a conversion ratio of 1: 2 and that the output voltage is twice the input voltage. Duty cycle 5
This can be achieved by continuous mode operation, where the transistor is turned on or conducting for 0%, ie half of the period of each cycle. Voltage waveforms 150 and 1
52 generally corresponds to the voltage waveform 60 (FIG. 4). The inductor current waveforms 154 and 156 correspond to the current waveform 62
(FIG. 4). Waveform 158 is the sum of current waveforms 154 and 156. Polyphase boost converter 110-2
One boost converter has 50 with 180 degree phase separation.
Operating at a% duty cycle, current waveform 154 also rises at the same rate, while current waveform 156 falls. The same applies to the opposite case. As a result, current waveform 158, which is the sum of these currents, does not include an AC component or ripple.

Referring to FIG. 9, there is shown a graph of the ripple current generated in a multi-phase boost converter using, for example, four boost converter circuits 40 (FIG. 3) operating in the critical conduction mode to illustrate the principles of the present invention. Provides further explanation. The graph shows a period of two complete cycles, ie, 72
Inductor current 16 of four boost converters during 0 degree
0, 162, 164 and 166. Generally, the current flowing through each inductor of the multi-phase boost converter of this embodiment ramps from a minimum of 0 amps to a maximum of 8 amps and back to 0 amps. By adding these four currents, a waveform 16 which is a composite current, that is, an effective current is obtained.
8 is generated. According to prior art implementations, either a single converter or four parallel converters requires a current ramp of 0 to 32 amps to produce an average DC component of 16 amps and a peak to peak 32 amps AC or ripple. Generate a current component.

According to the present invention, the resultant current 168 has a mean (DC) component of 16 amps as desired,
The C (ripple) current component is reduced to 2 amps peak to peak. The operation of the four boost converters 40 in a multi-phase configuration evenly shifted in phase with each other has reduced the undesirable ripple current component by a factor of 16. In addition, the frequency of the ripple current has increased fourfold. Since the impedance of the output filter capacitor located at the output of the polyphase boost converter, similar to output filter capacitor 140 (FIG. 7), is inversely proportional to frequency, a four-fold increase in the frequency of the ripple current is due to the efficiency of the capacitor as a filter. Is increased 4 times. This is the ripple size 16
Combined with a reduction by a factor of one, when compared to prior art converters, 64
Reduce ripple by a factor of one. In other words, the size of the filter capacitor can be reduced by a factor of 64, but the ripple remains the same as in the prior art.

The control circuit 134 (FIG. 7) described with reference to the polyphase boost converter 110 (FIG. 7) is useful for implementation in two-phase operation, but if more than two phases, additional transistors And an additional circuit for generating an excitation signal for the inductor. Generally, when N phases are used, N phase excitation signals are required, one for each phase. These phase excitation signals can be derived from a single master control signal. Obviously, there are numerous circuit configurations that can achieve this desired result, including the use of a microprocessor controller. One such circuit includes a circuit described with reference to FIG. 10 that relies on a digital shift register to derive a slave excitation signal from a master excitation signal, which circuit includes a suitable phase excitation signal. Is not the only circuit that can be used for the purpose of generating

Referring to FIG. 10, a schematic diagram of a four-phase boost conversion circuit 170 according to the present invention is shown. For details, see FIG.
Shows the use of the present invention as a power factor correction circuit. Power factor correction circuits are well known in the art and typically use a boost converter that modulates the input current of the converter in such a way that the input current is always proportional to the input voltage. For example, if the input voltage is a rectified sine waveform, the input voltage of the converter is also a rectified sine waveform. In this manner,
The power factor at the transducer input is modified or as if the transducer were a resistive load. Such a power factor correction circuit is known, for example, from Schaumbu, Illinois, USA
rg Motorola, Inc. Is a power factor control circuit manufactured by Power Factor Co.
ntrollers "Model Nos. MC342
62 / MC33262 (1996), Motorola, Ind., Which is incorporated herein by reference in its entirety.
c. Model number M described in the data sheet issued by
It is typically controlled by an integrated circuit control device specially manufactured for this purpose, such as C34262.

Referring again to FIG. 10, four-phase boost conversion circuit 170 includes power factor controller 175 and Moto
Uses Rola model number MC34262 (feature)
Power factor control circuit 174 and associated components shown in simplified schematic form. In the elements or devices of FIG. 10, where reference is made to, or for reference to, the manufacturer's publication, the manufacturer's pin number for the reference element is indicated in the figure. This includes a power factor controller 175, indicated by the manufacturer's pin numbers 1, 3, 4, 5 and 7. The omitted pins are simply connected to the supply voltage or common and are therefore not shown in the figure.

In addition to the power factor control circuit 174, the four-phase boost converter 170 includes a clock oscillator 172, a first shift register 178, a second shift register 176, a counter 180, and a four-phase It further includes a boost converter 188. Four-phase boost converter 188
Are, as shown, individual inductors 202, 20
4, 206 and 208, as well as transistor 21
It includes a separate boost converter having 0, 212, 214 and 216. Although a four-phase boost converter 188 is illustrated with a separate boost converter, the four-phase boost converter 188 may be replaced by a four-phase buck (buc) in accordance with the principles of the present invention.
k) It is understood that it can be replaced by a transducer.

Referring to power factor controller 175, pin 3 is connected to converter input 190, pin 1 (VFBK) is connected to converter output 194, and pin 5 (zero) is connected to the output circuit of the counter. The output pin 7 is connected to the shift register 17
8 and connected to the driver for transistor 210 for the first inductor 202 in the master phase, and all circuits of the referenced elements are connected to circuit common 192. The operation of the power factor controller 175 is based on Motorola
Described similarly to the publications, they operate in an intermittent conduction mode and differ only in that they are excited at a constant master cycle frequency determined by the clock circuit rather than by voltage or current. This is because in the critical conduction mode, i.e., when the excitation output of the controller is generated at the same time that the inductor current of the cycle reaches zero voltage, the Motoro
This contrasts with the operation of the power factor controller 175 described in the La publication.

The clock signal is connected to one connected to achieve a buffered RC oscillator, as is well known in the art.
It is obtained from a clock generator 172 composed of a hexadecimal inverter circuit. The clock signal from the clock oscillator 172 is, for example, Sch, Illinois, USA
Motorola, Inc. of Aumburg. 12-bit Binary Counter Model No. MC1404
A control counter 180, which is a conventional digital counter such as OB, is excited. This 12-bit binary counter is based on the publication Motorola CMOS Logic.
Data (1995). Other suitable counters are well known in the art and are commercially available, and are 12-bit binary counters model number MC14040B.
Are given as examples.

As shown in FIG. 10, the selected output of counter 180 is coupled to logic 186 to obtain a start pulse from counter 180 and to provide a predetermined number of clock cycles from clock oscillator 172. After that, the output of pin 7 of the power factor controller 175 is activated. Thus, the master cycle involves four phases shifted with respect to each other, as described herein, but the counter 1
80 activates only each subsequent master phase via an output to power factor controller 175.

In a typical phase operation, the power factor control circuit 17
4 is buffered by an amplifier and used to excite transistor 48 (FIG. 3) of boost conversion circuit 40 (FIG. 3) to charge inductor 46 (FIG. 3).
In the four-phase boost converter 170, the output at pin 7 of the power factor controller 175 is buffered by one of the two amplifiers contained in the double buffer package 184. Double buffer package 184 is available, for example, from Motorola, Schaumburg, Illinois, USA.
Inc. May be included. This amplifier package is M
otorola's publication "High Speed Du"
al MOSFET Drivers "MC34152
~ MC34152 (1996).
Other suitable buffers are well known in the art and are commercially available, and are available in a dual buffer package model number MC341.
Reference numeral 52 is given as an example. The output of the amplifier is used to excite transistor 210 as shown.

The output from power factor controller 175 is called the master phase or first phase of the master cycle. The output of the controller 174 also excites the data input D of the first shift register 178. The first and second shift registers 178 and 176 are, for example, Motorola, In of Schaumburg, Illinois, USA
c. Manufactured by Motorola Inc. "Du, published by U.S.A. and incorporated herein by reference in its entirety.
al 64-Bit Static Shift Re
gister "(1995).
l 64-Bit Static Shift Res
It may be included in the interter model number MC14517B. Therefore, the first and second shift registers 178 and 17
6 are shown as separate components, but are actually included in the same integrated circuit for convenience. As shown, first and second shift registers 178 and 17
6 generally comprises the remaining transistors 212, 214,
And 216 function to delay the individual phase signals applied to them. As is well known to those skilled in the art, to generate a delayed phase signal from a master phase signal, a first
It will be appreciated that there are many other elements in place of the second shift registers 178 and 176.

In summary, shift register 178 shown in FIG. 10 receives a signal at its data input D,
This signal is digitally shifted on each cycle of the clock signal from clock oscillator 172, thereby delaying the received signal. The delayed or shifted signal is applied to pins 1, 6, 2, 5, 15, 10, 10 of the illustrated first and second bit shift registers 178 and 176, depending on the number of delay stages that process the signal. , 14 and 11. To obtain a longer delay, the first and second bit shift registers 1
As with 78 and 176, shift registers 176 and 178 may be cascaded such that the input of the subsequent shift register is connected to one of the outputs of the earlier shift register. As shown, the first shift register 178 provides an output delay of 16, 32, 48 and 64 clock cycles, and the second shift register 176 adds a delay to the former, thereby providing 80, 9
This results in a delay of 6, 112 and 128 clock cycles.

To obtain the desired four phases equally spaced from one another, a master phase output signal is generated by power factor controller 175 and applied directly to transistor 210 without delay to the first phase. Start the phase. This master phase output signal is supplied to the first shift register 178
Of the cascaded first and second shift registers 178 and 176.
Set delay outputs of 2, 64 and 96 clock cycles. In this way, each phase is 3
It is shifted by two clock cycles. Selected outputs of the first and second shift registers 178 and 176 are:
As described above with respect to the master phase, the buffer circuit 18
Buffered by two and 184 amplifier stages. As with the master phase, each of these slave phases is connected to transistor 21 of four-phase boost converter 188.
Drive one of 2, 214 or 216. As described above, the four-phase boost converter 188 includes the inductor 202,
It includes four boost converters including 204, 206 and 208. Each phase inductor has a respective transistor switch 210, 212, 214 and 216, each connected to the output by a diode 219. These transistor switches are sequentially turned on and off to provide a four-phase output, thereby providing a four-phase output
A phase power factor correction boost circuit is realized.

Referring to FIG. 11, a four-phase boost converter circuit 170 is shown. 11, the four-phase boost converter circuit 170 has the same components as shown in FIG. 10, with the power factor controller 175 shown in more detail, with the addition of a full-wave rectifier 224 as shown. ing. The power factor controller 175 includes a latch driving member 217, a comparator 22
6, a multiplier 222, and several components including a cycle averaging circuit and an error amplifier circuit 225. Controller 175 for transistor switch 210
The drive output on pin 7 is latched by setting a latch in latch drive member 217, which is high during the duty-on time of transistor switch 210 and off when the latch drive member is reset. The output of pin 7 remains off until the start of the next master cycle by counter 180.

The output of the controller on pin 7 is also connected to the D input of the first shift register 178. This allows multiple logic “1” s to be clocked into first shift register 178 while transistor 210 is in the “on” state. When transistor 210 is in the “off” state, a zero is clocked into first shift register 178. Thus, transistors 212, 214 and 216 are turned on by a "1" shifted through each output stage to which the driver of each of the transistors 212, 214 and 216 is connected, and transistors 212, 214 and 216 are again zeroed Turns off at each stage when appears.

From the power factor controller 175 to the first shift register 178 and the first phase transistor switch 210
Is turned off when the inductor current flowing through transistor 210 exceeds a threshold. This threshold is determined by the voltage derived by multiplier 222 from the input at pin 3 of power factor controller 175. At pin 3, multiplier 222 monitors the full wave haver sine of full wave rectifier 224, which provides its input to each boost converter. Multiplier 222 also has an input from cycle averaging and error amplifier 225. A cycle averaging circuit and error amplifier circuit 225 averages the feedback from the converter output over a plurality of processing cycles, thereby providing an error signal representing an output voltage error. The input of the cycle averaging and error circuit 225 is connected to pin 1 of the controller where the feedback voltage is set. The output of the multiplier is the product of this input and each signal derived from the averaging and error signal circuit.

To compare the current in the first phase inductor 202 with a threshold voltage determined by the multiplier, the first
Ground reference resistor in the source circuit of the phase transistor switch 210 of FIG.
The current flowing through R7 is controlled by the controller 175.
Terminal CS, input on pin 4 is set. Pin 4 is connected to the source circuit of transistor 210 at a point between transistor 210 and resistor R7, as shown. The terminal CS is connected to the comparator circuit 226. In the comparator circuit 226, the voltage derived from the current flowing through the resistor R7
22 is compared with the threshold voltage set. If the current sense voltage is above the threshold, the latched drive output is reset and transistor 210 is turned off.

In the case of the Motorola type power factor controller 175 described above, the zero current monitoring process at pin 5 (zero) is typically performed with the current sense input at pin 4 so that the input at pin 5 is Provides a critical mode of operation for initiating a drive output from the controller at. This is because when the current peak at pin 4 exceeds the threshold level set by the multiplier 222, the inductor current falls to zero, and then terminates the drive output, thereby turning off the switch. Occur.

The present invention does not use a current circuit configuration that provides an input to controller pin 5. Instead, the output of clock counter 180 is applied to pin 5, thereby initiating an operation to turn on the drive output to master phase transistor 210. At this time, the other transistors 212, 2
Both 14 and 216 are turned on and off by the delayed clock signal as slaves of the first phase transistor 210. As described above, the counting of the counter delays the start of the next master cycle by a few clock counts, thereby ensuring a discontinuous mode of operation of the transistor switch for the master phase.

In the preferred embodiment, the counter 180
Provides the output from logic circuit 186 in the form of a positive pulse at a given count. This positive pulse preferably spans multiple counting cycles. When the trailing edge of this pulse falls to zero,
This pulse is detected by the zero start amplifier 230. Motorol related to the above power factor controller 175
As described in publication a, the zero-start amplifier 230 is basically a comparator having a positive bias of about 1 and 1.5 volts on the negative input.
With this detection, the drive output from the controller turns on transistor 210 and starts the next master clock. As mentioned above, the width of the pulse from the logic circuitry for the counter output preferably spans several clock signals, thereby introducing a delay between master cycles and having discontinuities for the master cycle. Operation is guaranteed, thereby ensuring discontinuous operation for the master phase and the slave phase. Thus, the period between the trailing edges of successive counter pulses will be larger than the clock pulses that would be required for critical operation.
Note that to provide good power factor correction, in addition to being equally spaced within the master cycle, the phase converter should have substantially the same charge and discharge characteristics.

Before the master inductor discharges,
It should be understood that a continuous operating mode can be obtained if the cycle turns on again. Those skilled in the art will appreciate that continuous or discontinuous operation is a function of various factors including the inductor value of the converter, the operating frequency, and the input and output voltages. . Also, if you are a person skilled in the art,
It would be possible to provide a polyphase boost or buck converter operating in accordance with the invention in any of the other modes.

The first and second shift registers 1
Note that 78 and 176 have enough output to drive eight phases if needed, and that more phases can be driven by cascading additional shift registers. For example, at high power levels, or in applications requiring particularly smooth input and output currents, such an increased number of phases may be desirable.

As can be seen from the above, the polyphase operation of the switch mode converter according to the present invention not only minimizes the ripple current, but also, as shown in FIGS. 10 and 11, an improved power factor correction circuit. It is an improvement that provides.
Further, the polyphase switch mode converter disclosed in the present application is:
It can also be used advantageously for power factor correction.

A system and method are provided for converting a DC voltage from a first voltage level to a second voltage level by operating a plurality of voltage converter circuits in a staggered phase relationship. The smoothest operation with minimum ripple voltage and ripple current is obtained when each converter is equally phase shifted from the previous converter and follows that operation. Assuming that the full cycle consists of 360 electrical angles, if the number of transducers used is "N", each transducer will be phase shifted 360 / N degrees to its neighbors. For example, if three converters are used (N = 3), each converter is phase shifted 360 / N degrees with respect to its neighbors. For example, if three converters are used (N = 3), each converter is phase shifted 120 degrees with respect to its neighbors. With four phases, a 90 degree phase shift is obtained, and not only a very reduced ripple is obtained, but also the operating frequency N of the converter.
Double frequency ripple is obtained, and filtering is simpler and less required.

Many variations and modifications can be made to the above-described embodiments of the invention without departing substantially from the spirit and principles of the invention. All such variations and modifications are intended to be included within the scope of the present invention.

[0067]

The system and method of the present invention converts a DC voltage from a first voltage level to a second voltage level by operating a plurality of voltage converter circuits in a staggered phase relationship. Systems and methods are provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a conventional buck converter circuit according to the prior art.

FIG. 2 is a graph of selected waveforms of the circuit in FIG.

FIG. 3 is a schematic diagram of a conventional boost converter circuit according to the prior art.

FIG. 4 is a graph of selected waveforms of the circuit in FIG.

FIG. 5 is a schematic diagram of a two-phase buck converter circuit according to the present invention.

FIG. 6 is a graph of a selected waveform of the circuit in FIG.

FIG. 7 is a schematic diagram of a two-phase boost converter circuit according to the present invention.

8 is a graph of a selected waveform of the circuit in FIG.

FIG. 9 is a graph of selected waveforms of a four-phase boost converter circuit according to the present invention.

FIG. 10 is a schematic diagram of a four-phase boost power factor correction converter circuit according to the present invention.

11 is an expanded view of the controller corresponding to FIG.

[Explanation of symbols]

 70 polyphase buck converter 72, 74 buck converter 76 input 78 common 80 output 82 control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (71) Applicant 500213845 580 Turnes Avenue, Elyria, Ohio 44035, United States of America

Claims (20)

[Claims] 1. A system for converting a voltage, comprising: a plurality of boost circuits configured in parallel; and a control circuit including a power factor correction circuit and at least one delay circuit. The circuit and the at least one delay circuit are configured to collectively generate a plurality of phase signals that are phase shifted with respect to each other, each of the phase signals being applied to a respective one of the boost circuits. By driving the corresponding boost circuit output, the system. 2. The phase signal generated by the power factor correction circuit and the at least one delay circuit is offset in phase at a predetermined phase interval.
System. 3. The phase signal generated by the power factor correction circuit and the at least one delay circuit drives each of the boost circuits in a discontinuous mode.
System. 4. The system of claim 1, wherein the phase signal generated by the power factor correction circuit and the at least one delay circuit drives each of the boost circuits in a critical conduction mode. 5. One of the phase signals is a master phase signal generated by the power factor correction circuit,
The system of claim 1, wherein at least one of the phase signals is a slave signal generated by the at least one delay circuit. 6. Each of the boost circuits is a switching device having a control input, a power input, and a switch output, the switch output being a switching device electrically coupled to a common; and an input of the boost circuit. 2. The power supply of claim 1, further comprising: an inductor electrically coupled between the power supply input; and a diode electrically coupled between the power supply input and an output of the boost circuit. System. 7. The system of claim 5, wherein said power factor correction circuit further comprises a master phase output electrically coupled to a switching input of one of said boost circuits. 8. The at least one delay circuit has a phase input and at least one slave output, the at least one slave output being electrically coupled to a corresponding switching input of the boost circuit. The system of claim 5, wherein the system is configured to: 9. The system of claim 6, wherein said switching device further comprises an insulated gate bipolar transistor. 10. A method for converting a voltage, comprising: a plurality of boost circuits configured in parallel; a power factor correction means for generating a first phase signal of the plurality of phase signals; At least one delay means for generating a second phase signal of at least one of the plurality of phase signals, the phase signals being phase shifted with respect to each other, wherein each of the phase signals is A method of driving a corresponding boost circuit output by being applied to each one of the boost circuits. 11. The method of claim 10, further comprising means for offsetting said phase signal by a predetermined phase interval. 12. A method for converting a voltage, the method comprising: electrically coupling a plurality of boost circuits in parallel; and controlling a phase with respect to each other by a control circuit including a power factor correction circuit and at least one delay circuit. Collectively generating a plurality of shifted phase signals, each of the phase signals being applied to a respective one of the boost circuits to drive a corresponding boost circuit output. Including, methods. 13. The method of claim 12, further comprising the step of offsetting the phase signal by a predetermined phase interval. 14. The method of claim 12, further comprising driving each of said boost circuits in a discontinuous mode with said phase signal. 15. The method of claim 12, further comprising driving each of said boost circuits in a critical conduction mode with said phase signal. 16. The power factor correction circuit and at least one
Collectively generating a plurality of phase signals by a control circuit including one delay circuit; generating a master phase signal by the power factor correction circuit; and generating a slave signal by the at least one delay circuit. 13. The method of claim 12, further comprising: 17. The providing of the boost circuit, comprising: providing a switching device having a control input, a power input, and a switch output, wherein the switch output is electrically coupled to a common. Electrically coupling an inductor to the input of the boost circuit and the power input; and electrically coupling a diode between the power input and the output of the boost circuit. 13. The method of claim 12, further comprising: 18. The method of claim 16 further comprising providing a master phase output from said power factor correction circuit electrically coupled to a switching input of one of said boost circuits. 19. Providing a phase input and at least one slave output of the at least one delay circuit, the at least one slave output comprising:
17. The method of claim 16, further comprising the step of electrically coupling to a switching input of a corresponding one of the boost circuits. 20. The method of claim 17, wherein providing a switching device having a control input further comprises providing an insulated gate bipolar transistor.