JP2000358017A - Method and system for communicating digital data and terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system for digital data and a terminal with which a plurality of terminals can be synchronized under easy control when synchronizing them for communicating digital data. SOLUTION: While using a cycle timer signal set to be communicated at regular intervals by communication controllers 16 and 26, in respective pieces of terminal equipment 10 and 20, a prescribed operating clock(CLK) is turned to this cycle timer signal and signal processing (encode processing or decode processing) related to MPEG data is performed on the basis of this operating CLK so that signal processing related to digital data can be synchronized between the plurality of terminals 10 and 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is useful when applied to a system for communicating digital data between a plurality of terminal devices. For example, a plurality of time-series digital data such as voice data and moving image data together with text data. The present invention relates to a technique that is particularly useful when applied to a system that performs processing between terminal devices.

[0002]

2. Description of the Related Art As a system for communicating digital data between a plurality of terminal devices, for example, a personal computer is connected to peripheral devices such as a printer, a digital camera, a VTR and other devices for handling moving image data, and digitally communicates between these devices. There are systems that transfer and use data. In such a system, if the operation clock frequency of the data processing is slightly shifted between the data transmission side and the reception side, an overflow or underflow of the data buffer occurs and continuous data transfer and moving image reproduction cannot be performed. For example, there are problems such as a screen drop where data is clogged and display of one screen is skipped, and a frame drop where data is interrupted and reproduction for one frame period is stopped.

[0003] Therefore, a technique has been developed to avoid overflow or underflow of the data buffer by synchronizing the signal processing of digital data between the transmitting side and the receiving side of digital data.
No. 213, JP-A-9-270994, JP-A-8-79
744 and the like.

[0004] As shown in FIG. 7, each of these techniques converts an image signal from a video camera 11 into an MPEG signal, for example.
A control signal generation circuit 56 is provided outside the communication controllers 16 and 26 such as an encoder 55 for converting data into data.
A clock carrier signal or a control signal for clock synchronization is generated in software or hardware, and these signals are transmitted together with digital data such as moving image data via the communication controllers 16 and 26, and based on these signals. By adjusting the operating clock frequencies of the transmission-side device and the reception-side device, the two are synchronized.

[0005]

However, according to the above-mentioned prior art, when a clock carrier signal or a control signal is generated or extracted in a hardware manner, a dedicated signal generation circuit (for example, a control signal generation circuit shown in FIG. 7) is used. 56 and the synchronization timer waveform extraction circuit 59) are required, which increases the space occupied by the circuit and increases the cost.

Further, in the above-mentioned conventional technology, since both digital data and control data are transmitted and received, the receiving device such as the MPEG decoder 58 separates the control data,
A synchronization circuit that synchronizes based on the separated control data (for example, the synchronization timer waveform extraction circuit 5 shown in FIG. 7)
9. Frequency / phase synchronization oscillator 61 and frequency divider 62
And the like, and the control data separation process needs to be performed simultaneously with the digital data processing such as the moving image data decoding process, so that the control system interrupts frequently occur during the processing of the digital data. The problem that control became very complicated occurred.

Further, since a clock carrier signal and a control signal are transmitted together with digital data such as moving image data, there arises a problem that the transmission capacity of a communication path is lost correspondingly. For example, if an attempt is made to apply the above technology to a system using a bus of the IEEE (American Institute of Electrical and Electronics Engineers) 1394 standard, the control signal is also complicated and large because many other types of signals pass through the IEEE 1394 bus. It is necessary to increase the amount of data and the frequency of transmitting and receiving control signals in order to achieve synchronization. As a result, the bus transmission capability of IEEE 1394 is reduced to a considerable extent.

[0008] An object of the present invention is to solve the above-mentioned problem, and when a plurality of terminal devices performing digital data communication synchronize with each other, it is predetermined to communicate regularly between communication controllers in advance. Provided are a digital data communication method, a communication system, and a terminal device which can achieve synchronization by easy control without using a signal to transmit and receive a new signal such as a clock carrier signal and a control signal. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, using a reference signal set in advance by the communication controller so as to be communicated at regular intervals, each terminal device tunes its operation clock to the reference signal, and based on the operation clock, By performing signal processing (for example, encoding processing, decoding processing, reading processing, and writing processing) on digital data, signal processing on digital data is synchronized by a plurality of terminal devices.

According to such means, synchronization is achieved between a plurality of terminal devices using the reference signal previously communicated by the communication controller, so that a new signal for synchronization is generated and digital data It is not necessary to perform communication by including the data in the data transmission, so that the original data transmission capability is not reduced. Since the reference signal is a signal preset in the communication controller, the digital data and the reference signal are transferred from the communication controller to the signal processing unit of the terminal device in a separated state. Therefore, the processing for synchronization and the signal processing of digital data can be performed independently of each other, and the control content is simplified as a whole.

Further, when there is fluctuation in the transmission timing of the reference signal, and the reference signal includes time data (such as IEEE 1394 cycle timer data) related to the transmission timing of the reference signal, the above-mentioned time data is used. By compensating the output timing of the operation clock, a stable operation clock can be generated even if the transmission timing of the reference signal fluctuates. Further, by allowing the reference signal to fluctuate, it is possible to provide a margin for data communication.

Specifically, in the IEEE 1394 standard having the isochronous transfer mode in which the communication controller performs data transfer at regular intervals, the communication controller can be realized by using a cycle start signal in the isochronous transfer mode as the reference signal. Other communication standards can also be realized by using time data according to the IEEE 1394 cycle start signal as a reference signal.

Further, the digital data is time-series digital data such as audio data and moving image data. While the first terminal device performs digital data encoding processing based on the operation clock, the first terminal device encodes the digital data. After communicating from one terminal device to the second terminal device,
This is particularly effective in a system in which digital data is decoded based on the operation clock in the second terminal device. For example, even if the encoding process and the decoding process are performed in real time, the processes are synchronized. It is possible to avoid problems such as so-called screen drop and frame dropout.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a communication system suitable for applying the present invention, and FIG. 2 is a block diagram showing an example of an application form which can be constituted by the communication system of the embodiment.

In FIG. 1, reference numeral 10 denotes a first terminal device including a video camera 11, and reference numeral 20 denotes a second terminal device including a video monitor 21. In this embodiment, both are IE
A bus is connected by a communication bus 80 conforming to the EE (American Electrical and Electronic Engineers Association) 1394 standard to constitute a communication system.

As shown in FIG. 2, the IEEE 1394 communication bus 80 includes a digital video camera device 10, a digital television monitor device 20, a digital VTR device 30, a digital broadcast receiver 40, a digital audio device 50,
A plurality of terminal devices such as the printer 60 and the personal computer 70 are connected, and digital data can be transmitted and received between the plurality of terminal devices.

The digital video camera device 10 includes a video camera 11 for converting an image into an electric signal, a digital image signal, and an MPEG (Motion Picture Exposure).
ertsGroup) an MPEG encoder 12 (signal processing means) for compression, a communication control unit 16 which is a communication controller conforming to the IEEE 1394 standard, a timing compensation circuit 15 as a compensation means characteristic of the present invention, and an operation clock tuning means. And the like. Although not particularly limited, in this embodiment, the communication control unit 16, the timing compensation circuit 15, and the PLL circuit 14 constitute a one-chip LSI controller 13 formed as a semiconductor integrated circuit on one semiconductor chip. I do.

The digital television monitor 20 is an MPE
In addition to an MPEG decoder 22 for expanding G-compressed video data and demodulating it into a video signal, a video monitor 21 for outputting video based on the video signal, a communication control unit 26, a timing compensation circuit 25, and a PLL circuit 24 and the like.

Although not shown in FIG. 1, these digital video camera device 10 and digital television monitor device 2
0 is provided with an independent clock generation circuit for generating a system clock φs oscillating at, for example, about 27 MHz. Since these system clocks φs are independent of each other, there may be a slight deviation from each other.

The communication control units 16 and 26 are based on IEEE 139
This is a controller that conforms to the 4 standards and includes an IEEE 1394 physical layer, a link layer, and a transaction layer. The communication control units 16 and 26 are provided with 32-bit cycle timer registers 16a and 26a, and count up by the system clock φs of each terminal device. IEEE 1394 has an isochronous transfer mode in which each node (terminal device) transfers data in real time.

In the isochronous transfer mode, one of the nodes serves as a cycle master to perform central control of isochronous transfer. Specifically, the node that has become the cycle master transmits a cycle start signal to the bus 80 at regular cycles (every 125 μsec), starts one cycle of isochronous transfer, and sends a signal to each node during this one cycle. The priority of the bus is given to perform the data transfer. By repeating this cycle, each node performs data transfer in real time.

The cycle start signal is several bytes of packet data, and the data includes a 32-bit cycle timer signal (cycle timer data).
This cycle timer signal indicates the data value of the cycle timer registers 16a and 26a of the node that has become the cycle master. The cycle start signal is usually transmitted every fixed cycle period (125 μsec), but is delayed and transmitted when data transfer of all nodes is longer than one cycle period of isochronous transfer.
When the cycle start is postponed, the cycle master postpones the postponed time of the cycle start as a quadlet request packet to the cycle timer registers 16a, 26a,... Of all nodes. By this processing, all nodes are synchronized within a certain error.

The communication controllers 16 and 26 of this embodiment are configured to output a cycle timer signal to the timing compensation circuits 15 and 25 when receiving the cycle start signal.

Each of the PLL circuits 14 and 24 includes a frequency-phase synchronous oscillation circuit 14a, 24a and a frequency dividing circuit 14b, 24b.
The 27 MHz operation clock CLK is generated in synchronization with the reference clock signal φref based on the reference clock signal φref of
It outputs to the decoder 22 (digital data signal processing means).

More specifically, the frequency and phase synchronization oscillators 14a and 24a multiply the reference clock signal φref by a predetermined factor (for example, 3375) to generate a clock of a predetermined frequency (for example, 27 MHz), and generate a frequency dividing circuit. 1
4b and 24b divide the frequency by the same scale (for example, 3375) and return it to the frequency / phase synchronous oscillation circuits 14a and 24a. The frequency and phase synchronization transmission circuit 4a compares the frequency and the phase of the reference clock signal φref from the timing compensation circuit 5 with the signal from the frequency dividing circuit 4b, and controls its own oscillation so that the two frequencies match. By this control, even when the period of the reference clock signal φref fluctuates or the system clock φs of the terminal device has a specific frequency deviation with respect to the reference clock signal φref, the reference clock signal φref and the operation clock CLK
Synchronization with is achieved.

FIG. 3 shows a timing compensation circuit 1 according to the embodiment.
It is a block diagram which shows the detailed example of a structure of 5, 25.

The timing compensating circuits 15 and 25 receive a reference clock signal φref synchronized with the cycle timer signal based on the cycle timer signal from the communication control units 16 and 26.
When the output phase of the cycle timer signal fluctuates to a relatively moderate level, this circuit buffers this fluctuation and converts it into a small phase fluctuation (for example, a phase fluctuation of one cycle of the system clock φs). is there. However, control is performed so that the average period of the reference clock signal φref matches the cycle timer signal.

With the function of suppressing the phase fluctuation to a small value,
Even if the response characteristics of the PLL circuits 14 and 24 are lowered, erroneous operation can be prevented, and at the same time, the control speed of the PLL circuits 14 and 24 can be reduced, and the accuracy of the frequency of the operation clock CLK can be increased.

More specifically, as shown in FIG. 3, the timing compensating circuits 15 and 25 are provided with a CYC counter 4 for counting a system clock φs of, for example, about 27 MHz.
1 or the frequency of the system clock φs (for example, 3375
A reference clock generation counter 43 for generating the 8 kHz reference clock signal φref by dividing the frequency, and a value for controlling the count of the reference clock generation counter 43 by comparing the data value of the cycle timer signal with the count value of the CYC counter 41. It comprises a comparator 42 and the like.

The reference clock generation counter 43 counts a count value (for example, 3375) corresponding to a target frequency of 8 kHz of the reference clock signal φref, and counts the count value according to a shift of the system clock φs with respect to the cycle timer signal. It has a function of adjusting the frequency by "+1" or "-1". Specifically, instead of using a circuit for setting “−1”, the count control signal Sg3 from the value comparator 42 is reset by “3376” which is “1” greater than “3375”.
The count value is set to “+1” or “+” based on Sg5.
A function to add an extra 2 ”is provided. And
In the standard state, that is, when the frequency of the cycle timer signal matches the frequency of the system clock φs, the count control signal Sg4 is input every reset cycle to cause the reference clock generation counter 43 to count “+1” more. It is possible to operate as a counter which is reset by 3376 clocks smaller than the actual one. When the frequency of the system clock φs is low, the count control signal Sg for keeping the count value of the reference clock generation counter 43 as it is, that is, “+0”.
By inputting 3, the reset cycle can be shortened by one clock to increase the frequency of the reference clock signal φref. When the frequency of the system clock φs is high, the count control signal Sg5 for increasing the count value by “+2” is input. By doing so, the frequency of the reference clock signal φref can be reduced by lengthening the count cycle by one clock.

The CYC counter 41 is a 32-bit counter similar to the cycle timer data and counts up by the system clock φs. That is, the cycle timer register 1 of the communication control units 16 and 26
The frequency is increased at the same frequency as 6a and 26a. Also,
It has a function of loading the data value of the cycle timer signal by the load signal Sg6 from the value comparator 42.

The value comparator 42 compares the data value of the cycle timer signal with the count value of the CYC counter 41 when the cycle timer signal is input, and outputs a count control signal Sg4 if they match, and outputs “+1”. And the reset cycle of the reference clock generation counter 43 is kept at a predetermined cycle. If the count value of the CYC counter 41 is larger, the count control signal Sg5 is output and “+2” is added to reset the reference clock generation counter 43. The cycle is shortened by one clock, and if the count value of the CYC counter 41 is smaller, a count control signal Sg3 is output and “+
By adding “0”, the reset cycle of the reference clock generation counter 43 is lengthened by one clock.

That is, even if the system clock φs has a relative phase shift with respect to the cycle timer signal and the reference clock signal φref is delayed or advanced by this control, the phase of the cycle timer signal and the reference clock signal φref can be reduced. By controlling the reference clock generation counter 43 so as to match the phase, the phase of the reference clock signal φref is advanced or delayed by one clock of the system clock φs to perform phase compensation. As described above, in this embodiment, even when the phase of the cycle timer signal is greatly shifted, one cycle of the system clock φs is used.
Until the phase of the cycle timer signal and the phase of the reference clock signal φref match, phase compensation for increasing or decreasing the phase of the reference clock generation counter 43 is performed slowly.

The value comparator 42 receives the comparison trigger signal Sg2 at the rise of the reference clock signal φref, and if the input timing of the comparison trigger signal Sg2 matches the cycle timer signal, the value comparator 42 outputs the load signal. Sg6 is output to perform control to replace the value of the CYC counter 41 with the data value of the cycle timer signal.

That is, if this control is not performed, even if the cycle timer data and the count value of the CYC counter 41 deviate and the phase compensation of the reference clock generation counter 43 is performed, this phase compensation is reflected on the CYC counter 41. In this case, the cycle timer data and the count value of the CYC counter remain forever. However, if the phase of the cycle timer signal and the reference clock signal φref match, the cycle timer data and the CYC counter
The count value of the counter is set to the same value, and the phase compensation of the reference clock signal φref is stopped.

FIG. 4 is a time chart of each signal in the timing compensation circuit of FIG.

As shown in the figure, in the timing compensation circuits 15 and 25, the frequency of the cycle clock signal from the reference clock generation counter 43 (for example, 8
kHz) is output, and a comparison trigger signal Sg2 is output when the reference clock signal φref rises.

As described above, the CYC counter 4
The count value of 1 is compared with the data value when the cycle timer signal is input, and if both are the same, a count control signal (CNTCTRL1) Sg4 is output, and the CYC counter 4
If the count value of 1 is larger, the count control signal (CNTCTRL2) Sg5 is output and the CYC counter 41
If the count value is smaller, a count control signal (CNTCTRL3) Sg3 is output.

FIG. 5 is a time chart for explaining the phase compensation control of the reference clock signal φref performed by the timing compensation circuit. 11A shows a case where the cycle timer signal and the system clock φs are synchronized, FIG. 10B shows a case where the system clock φs is delayed, and FIG. 10C shows a case where the system clock φs is advanced. Things.

In FIG. 5, the system clock φs is indicated by hatching every n clocks. n is the number (for example, 3375) of system clocks φs to be output in one cycle of the cycle timer signal.

As shown in FIG. 5A, while the system clock φs is not shifted and the cycle timer signal is transmitted at the same cycle as a predetermined number (for example, 3375) of system clocks φs, the cycle timer signal is transmitted. Is equal to the count value of the CYC counter 41, and the reference clock signal φref is output without being phase-compensated and synchronized with the system clock φs.

On the other hand, as shown in FIG. 5B, when the cycle timer signal is delayed from the reference clock signal φref due to a shift of the system clock φs or a change in the output timing of the cycle timer signal, the CYC counter 41
Becomes larger than the data value of the cycle timer signal, and the phase compensation control of the reference clock signal φref is performed. This phase compensation is performed by the reference clock signal φref
Is compensated by one system clock φs for every one cycle of the reference clock signal φref.
Continue until synchronized. As a result, the phases of the reference clock signal φref and the cycle timer signal gradually match.

Similarly, as shown in FIG. 5C, when the cycle timer signal is ahead of the reference clock signal φref due to a shift of the system clock φs or a change in the output timing of the cycle timer signal, the CYC counter 4
The count value of 1 becomes smaller than the data value of the cycle timer signal, and phase compensation control of the reference clock signal φref is performed. This phase compensation is performed by the reference clock signal φre
Compensation that advances by one system clock φs for each cycle of f
Continue until synchronized. As a result, the phases of the reference clock signal φref and the cycle timer signal gradually match.

Various modifications can be considered for the method of comparing the CYC counter 41 with the cycle timer data. For example, latch the cycle timer data,
The comparison can be performed when the comparison trigger signal Sg2 is input. Also, the cycle timer data to be compared is not set as the cycle timer data of the cycle start signal, and the cycle timer register 1 provided at each node is used.
6a and 26a. Since the cycle timer data of the cycle start signal is broadcast and updated in the cycle timer registers 16a and 26a, even if this data is used, synchronization can be obtained between a plurality of terminal devices.

As described above, according to the digital data communication system and the terminal device of the above embodiment, the cycle start signal or the cycle start signal set in advance so as to be transmitted at regular intervals by the communication control units 16 and 26 is provided. Since synchronization is performed between a plurality of terminal devices by using the cycle timer signal (reference signal) therein, it is necessary to generate a new signal for synchronization and include it in digital data for communication as in the related art. And the data transmission capacity of IEEE 1394 is not reduced. Further, since the cycle start signal is already separated from the MPEG data in the transaction layer of the communication controllers 16 and 26, the process for synchronizing with the cycle start signal and the signal processing of the MPEG data can be performed independently. Control processing is simplified.

Further, there is fluctuation in the output timing of the cycle start signal, and the cycle start signal includes cycle timer data relating to the output timing. The output timing of the reference clock signal φref is determined based on the cycle timer data. To compensate,
Even if the output timing of the cycle start signal fluctuates, a stable operation clock CLK can be generated.

Further, the moving image signal obtained by imaging
Since the present invention is applied to a communication system between a digital video camera that performs EG end processing and a digital television monitor that decodes transferred MPEG data and outputs a video, even in the case of real-time moving image playback, a so-called so-called Problems such as dropped screens and missing frames can be avoided.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the present invention is not limited to a communication system constituted by a digital video camera device and a digital television monitor device. For example, a system for performing communication between terminal devices for reading and writing digital data, The present invention is also useful when applied to a system that performs communication between terminal devices that perform various signal processing on data. In addition, although the MPEG decoding process and the MPEG encoder process have been illustrated as the signal processes related to the digital data, it goes without saying that various other types of decoding and encoding processes are also included. And various signal processing such as processing.

In the above embodiment, the reference signal and the operation clock are synchronized by generating the operation clock based on the reference signal (cycle start signal). It is also possible to control to generate and tune the reference signal based on the clock. Specifically, the communication control unit 16 of a predetermined terminal device (for example, a VTR device) is fixed so as to be a cycle master, and the operation clock of the MPEG encoder 12 is generated using the system clock φs of the terminal device. Cycle timer register 16a in communication control unit 16 using the same system clock φs
Or MPEG
This is achieved by guiding the operation clock of the encoder 12 to the communication control unit 16, generating a clock signal of the cycle timer register 16a from the operation clock, and performing counting.

Further, by making the PLL circuits 14 and 24 have a response performance that can sufficiently follow the phase fluctuation of the cycle start signal, the phase compensation function (the CYC counter 41 and the value comparator) can be provided from the timing compensation circuits 15 and 25. 42) can be omitted, and the timing compensation circuits 15 and 25 can only generate the reference clock signal φref.

FIG. 6 shows a modification of the terminal device suitable for applying the present invention.

In the above-described embodiment, the communication control unit 16, the timing compensation circuit 15, and the PLL circuit 14 are integrated into one chip and described as the control LSI 13. However, for example, as shown in FIG. Fifteen
And a PLL circuit 14 integrated on one chip to form an LSI 13
6A. Alternatively, as shown in FIG. 6B, a signal processing unit such as a timing compensation circuit 15, a PLL circuit 14, and an MPEG encoder 12 is integrated on a single chip to form an LSI.
13B may be used. Also, as shown in FIG.
A signal processing unit such as the communication control unit 16, the timing compensation circuit 15, the PLL circuit 14, and the MPEG encoder 12 can be integrated into one chip to form an LSI 13C.

In the above description, the invention made mainly by the present inventor is based on the field of use which is the background of the IEEE.
Although the communication system conforming to the E1394 standard has been described, the present invention is not limited to this. The present invention can be used for other communication systems having an isochronous transfer mode. It can be widely used for communication systems of various standards.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, when transmitting and receiving digital data between a plurality of terminal devices and performing signal processing on the digital data, the transmission capability of data communication is not burdened, and With simple control contents, it is possible to synchronize the signal processing performed between the plurality of terminal devices.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a communication system suitable for applying the present invention.

FIG. 2 is a block diagram illustrating an example of an application mode that can be configured by the communication system according to the embodiment.

FIG. 3 is a block diagram illustrating a detailed configuration example of a timing compensation circuit according to the embodiment;

FIG. 4 is a time chart showing changes in signals of the timing compensation circuit of FIG. 3;

5A and 5B are time charts for explaining compensation control of a phase of a reference clock signal φref performed by a timing compensation circuit, wherein FIG. 5A shows a case where a cycle timer signal and a system clock φs are synchronized, and FIG. (C) shows a case where the system clock φs is advanced, and (c) shows a case where the system clock φs is advanced.

FIG. 6 is a block diagram showing a modified example of a communication system suitable for applying the present invention.

FIG. 7 is a block diagram illustrating an example of a conventional communication system.

[Explanation of symbols]

 Reference Signs List 10 digital video camera device 12 MPEG encoder (signal processing means) 13, 23 control LSI 14, 24 PLL circuit (operation clock tuning means) 15, 25 timing compensation circuit (compensation means) 16, 26 communication control unit (communication controller) 16a , 26a Cycle timer register 20 Digital television monitor 22 MPEG decoder (signal processing means) φref Reference clock signal CLK Operation clock

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiki Watanabe 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Super SII Systems Co., Ltd. (72) Inventor Haruhiko Imada Tokyo 5-22-1, Kamimizu Honcho, Kodaira City Within Hitachi Cho SII Systems, Inc. (72) Inventor Kazunori Nakamura 5-221-1, Kamimizu Honcho, Kodaira City, Tokyo Hitachi, Ltd. LSI Systems Inc. (72) Inventor Takaaki Morita 3-2-1 Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Media Links Co., Ltd. (72) Inventor Eiichi Hayashi Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture 3-2-1 F-term in Media Links Co., Ltd. (reference) 5C059 MA00 PP04 RB02 RC03 RC32 RC34 SS06 SS30 UA10 5K047 AA01 BB05 DD01 DD02 GG06 GG41 MM03 MM12 </ S> </ s> </ s>

Claims (9)

[Claims] 1. A digital data communication method, wherein digital data is transmitted and received between a plurality of terminal devices via a communication controller having a predetermined protocol, and a reference signal is communicated at regular intervals by the communication controller. In each of the terminal devices, each operation clock is synchronized with the reference signal, and the signal processing of the digital data is performed based on the operation clock, thereby synchronizing the signal processing of a plurality of terminal devices. Characteristic digital data communication method. 2. The digital data communication method according to claim 1, wherein the reference signal includes data relating to time, and the timing of the operation clock is adjusted based on the time data. 3. The communication controller according to claim 1, wherein said communication controller is IEEE 139.
3. The digital data according to claim 1, wherein the digital data has an isochronous transfer mode for performing data transfer at regular intervals in accordance with four standards, and the reference signal is a cycle start signal in the isochronous transfer mode. Communication method. 4. The digital data communication method according to claim 2, wherein said time data is cycle timer data conforming to the IEEE 1394 standard. 5. The digital data is time-series digital data such as audio data and moving image data, and the first terminal device encodes the digital data based on the operation clock, and encodes the digital data in the first terminal device. After communication from one terminal device to the second terminal device, the second
2. The terminal device according to claim 1, wherein the digital data is decoded based on the operation clock.
5. The communication method for digital data according to any one of claims 1 to 4. 6. A plurality of terminal devices provided with a communication controller for communicating digital data based on a predetermined protocol and communicating predetermined reference signals at regular intervals, and connecting the plurality of terminal devices via the communication controller. A communication means for transmitting and receiving digital data between the plurality of terminal devices, wherein the plurality of terminal devices have an operation for tuning their operation clocks to the reference signal. A digital data communication system, comprising: clock tuning means; and signal processing means for performing signal processing of the digital data based on the operation clock. 7. A communication controller configured to communicate digital data based on a predetermined protocol and to communicate a predetermined reference signal at regular intervals, and a clock synchronization for synchronizing a predetermined operation clock with the reference signal. And a signal processing means for performing signal processing on the digital data based on the operation clock, wherein the terminal apparatus is configured to perform the signal processing in synchronization with the operation clock. 8. The terminal according to claim 7, wherein said reference signal includes data relating to time, and further comprising compensating means for compensating timing of said operation clock based on said time data. apparatus. 9. The communication controller according to claim 1, wherein the communication controller is an IEEE 139.
9. The terminal device according to claim 7, wherein the terminal device has an isochronous transfer mode for performing data transfer at regular intervals in accordance with the four standards, and the reference signal is a cycle start signal in the isochronous transfer mode. .